1,056 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/cyfitter.h
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88 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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@@ -122,39 +122,33 @@ static void CyClockStartupError(uint8 errorCode)
}
#endif

#define CY_CFG_BASE_ADDR_COUNT 31u
#define CY_CFG_BASE_ADDR_COUNT 29u
CYPACKED typedef struct
{
uint8 offset;
uint8 value;
} CYPACKED_ATTR cy_cfg_addrvalue_t;

#define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)
#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x4800007Cu)

/* UDB_1_4_1_CONFIG Address: CYDEV_UCFG_B0_P1_U0_BASE Size (bytes): 128 */
#define BS_UDB_1_4_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000620u)
#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000074u)

/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x480006A0u)
#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x480003FCu)

/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480006A8u)
/* IOPINS0_7 Address: CYREG_PRT12_DM0 Size (bytes): 8 */
#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x48000404u)

/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480006B4u)
/* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */
#define BS_IOPINS0_8_VAL ((const uint8 CYFAR *)0x4800040Cu)

/* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */
#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480006BCu)
#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000418u)

/* IOPINS0_4 Address: CYREG_PRT4_DR Size (bytes): 10 */
#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480006C4u)

/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480006D0u)
#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000420u)

/* CYDEV_CLKDIST_ACFG0_CFG0 Address: CYREG_CLKDIST_ACFG0_CFG0 Size (bytes): 4 */
#define BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL ((const uint8 CYFAR *)0x480006D8u)
#define BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL ((const uint8 CYFAR *)0x4800042Cu)


/*******************************************************************************
@@ -220,26 +214,23 @@ static void ClockSetup(void)
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x0033u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x5DBFu);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x18u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG4_CFG0), 0x5DBFu);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG4_CFG0), 0xBB7Fu);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG4_CFG0 + 0x2u), 0x18u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG5_CFG0), 0xBB7Fu);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG5_CFG0 + 0x2u), 0x18u);

/* Configure Analog Clocks based on settings from Clock DWR */
CYCONFIGCPY((void CYFAR *)(CYREG_CLKDIST_ACFG0_CFG0), (const void CYFAR *)(BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL), 4u);

/* Configure ILO based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_CR), 0x08u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);

/* Configure IMO based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x03u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));

/* Configure PLL based on settings from Clock DWR */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0008u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0708u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
/* Wait up to 250us for the PLL to lock */
pllLock = 0u;
@@ -260,10 +251,13 @@ static void ClockSetup(void)
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);

/* Configure USB Clock based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DLY1), 0x04u);

CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x3Fu)));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x1Fu)));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG1), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG1) | 0x01u)));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG0), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x80u)));
}
@@ -293,9 +287,9 @@ static void AnalogSetDefault(void)
uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
CY_SET_XTND_REG8((void CYFAR *)CYREG_PRT3_AG, 0x20u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_DSM0_SW0, 0x20u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_BUS_SW0, 0x20u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PRT3_AG, 0x80u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_DSM0_SW0, 0x80u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_BUS_SW0, 0x80u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
}

@@ -425,32 +419,18 @@ void cyfitter_cfg(void)
uint16 size;
} CYPACKED_ATTR cfg_memset_t;


CYPACKED typedef struct {
void CYFAR *dest;
const void CYFAR *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;

static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 36u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
{(void CYFAR *)(CYREG_PRT5_DR), 16u},
{(void CYFAR *)(CYREG_PRT15_DR), 16u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 512u},
{(void CYFAR *)(CYDEV_UCFG_B0_P1_U1_BASE), 3456u},
{(void CYFAR *)(CYREG_PRT1_DR), 32u},
{(void CYFAR *)(CYREG_PRT5_DR), 32u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
};

static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UCFG_B0_P1_U0_BASE), BS_UDB_1_4_1_CONFIG_VAL, 128u},
};

uint8 CYDATA i;

/* Zero out critical memory blocks before beginning configuration */
@@ -460,16 +440,6 @@ void cyfitter_cfg(void)
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}

/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPY(destPtr, srcPtr, numBytes);
}

cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);

/* Perform normal device configuration. Order is not critical for these items. */
@@ -487,11 +457,10 @@ void cyfitter_cfg(void)

/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPY((void CYFAR *)(CYREG_PRT0_DM0), (const void CYFAR *)(BS_IOPINS0_0_VAL), 8u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DM0), (const void CYFAR *)(BS_IOPINS0_7_VAL), 8u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DM0), (const void CYFAR *)(BS_IOPINS0_3_VAL), 8u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT4_DR), (const void CYFAR *)(BS_IOPINS0_4_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);
/* Switch Boost to the precision bandgap reference from its internal reference */
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));

@@ -501,7 +470,6 @@ void cyfitter_cfg(void)
ClockSetup();
/* Set Flash Cycles based on newly configured 24.00MHz Bus Clock. */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x81u : 0x80u));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PANTHER_WAITPIPE), 0x01u);

/* Perform basic analog initialization to defaults */
AnalogSetDefault();
1,056 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
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1,056 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
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1,056 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
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352 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/cymetadata.c
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15 alpaca-bms/alpaca-bms.cydsn/Generated_Source/PSoC5/project.h
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@@ -35,7 +35,6 @@
#include "timer_clock.h"
#include "current_timer.h"
#include "EEPROM_1.h"
#include "LCD.h"
#include "SS_aliases.h"
#include "SS.h"
#include "poll.h"
@@ -45,22 +44,26 @@
#include "OK_SIG_aliases.h"
#include "OK_SIG.h"
#include "DEBUG_UART.h"
#include "DEBUG_UART_audio.h"
#include "DEBUG_UART_cdc.h"
#include "DEBUG_UART_hid.h"
#include "DEBUG_UART_midi.h"
#include "DEBUG_UART_pvt.h"
#include "WDT_timer.h"
#include "WDT_timer_clock.h"
#include "WDT_ISR.h"
#include "red_led_1_aliases.h"
#include "red_led_1.h"
#include "timer_clock_1.h"
#include "Can_Update_Timer.h"
#include "Can_Update_ISR.h"
#include "LTC68_IntClock.h"
#include "LCD_LCDPort_aliases.h"
#include "LCD_LCDPort.h"
#include "ADC_current_AMux.h"
#include "ADC_current_Ext_CP_Clk.h"
#include "ADC_current_IRQ.h"
#include "ADC_current_theACLK.h"
#include "DEBUG_UART_IntClock.h"
#include "DEBUG_UART_Dm_aliases.h"
#include "DEBUG_UART_Dm.h"
#include "DEBUG_UART_Dp_aliases.h"
#include "DEBUG_UART_Dp.h"
#include "core_cm3_psoc5.h"
#include "core_cm3.h"
#include "CyDmac.h"
BIN +30 KB (130%) alpaca-bms/alpaca-bms.cydsn/TopDesign/TopDesign.cysch
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BIN +6.14 KB (110%) alpaca-bms/alpaca-bms.cydsn/alpaca-bms.cydwr
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409 alpaca-bms/alpaca-bms.cydsn/alpaca-bms.cyprj
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9,547 alpaca-bms/alpaca-bms.cydsn/alpaca-bms.svd
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18 alpaca-bms/alpaca-bms.cydsn/cell_interface.c
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@@ -52,7 +52,7 @@ Copyright 2013 Linear Technology Corp. (LTC)
#define OVER_VOLTAGE (0x4000)
#define UNDER_VOLTAGE (0x1000)

#define DEBUG_LCD 0
//#define DEBUG_LCD 0

#define OVER_TEMP (20000)
#define UNDER_TEMP (10000)
@@ -135,14 +135,14 @@ uint8_t check_cells(){
for (i_cell=0;i_cell<12;i_cell++){
if ((((int16_t)cell_pu[i_IC][i_cell+1]-(int16_t)cell_pd[i_IC][i_cell+1]) < -400) && (CELL_ENABLE&(0x1<<i_cell))){
fatal_err |= CELL_VOLT_UNDER;
LCD_Position(1u,0u);
LCD_PrintString("big ");
//LCD_Position(1u,0u);
//LCD_PrintString("big ");
return 1;
}
if (cell_pu[i_IC][0]==0){
fatal_err |= CELL_VOLT_UNDER;
LCD_Position(1u,0u);
LCD_PrintString("eq 0");
//LCD_Position(1u,0u);
//LCD_PrintString("eq 0");
return 1;
}
if (cell_pd[i_IC][11]==0){
@@ -243,22 +243,28 @@ uint8_t get_cell_temp(){
error = LTC6804_rdaux(0,TOTAL_IC,aux_codes); // Set to read back all aux registers
if (error == -1)
{
#ifdef DEBUG_LCD
LCD_Position(0u,10u);
LCD_PrintString("ERROR");
#endif
return 1;
}

for (i=0;i<12;i++){
if (aux_codes[0][i]>OVER_TEMP){
#ifdef DEBUG_LCD
LCD_Position(1u,0u);
LCD_PrintString("OVER TEMP");
#endif
// error_IC = ic;
// error_TEMP = i;
fatal_err |= PACK_TEMP_OVER;
return 1;
}else if (aux_codes[0][i]<UNDER_TEMP){
#ifdef DEBUG_LCD
LCD_Position(1u,0u);
LCD_PrintString("UNDER TEMP");
#endif
warning_err |= PACK_TEMP_UNDER;
return 1;
}else{
@@ -269,10 +275,12 @@ uint8_t get_cell_temp(){
}
}

#ifdef DEBUG_LCD
LCD_Position(1u,10u);
print_cells(aux_codes[0][0]);
LCD_Position(0u,10u);
LCD_PrintString("OK");
#endif
return 0;
}// get_cell_temp()
//void balance_cells(){}// balance_cells()
32 alpaca-bms/alpaca-bms.cydsn/main.c
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@@ -26,14 +26,14 @@ int main(void)
{
CyGlobalIntEnable;
//WDT_init();
red_led_1_Write(1);
CyDelay(100);
red_led_1_Write(0);
CyDelay(100);
red_led_1_Write(1);
CyDelay(100);
red_led_1_Write(0);
LCD_Start();
//red_led_1_Write(1);
//CyDelay(100);
//red_led_1_Write(0);
//CyDelay(100);
//red_led_1_Write(1);
//CyDelay(100);
//red_led_1_Write(0);
//LCD_Start();
DEBUG_UART_Start();

//WDT_init();
@@ -45,12 +45,12 @@ int main(void)



LCD_ClearDisplay();
LCD_Position(0u, 0u);
LCD_PrintString("BMS DEMO");
//LCD_ClearDisplay();
//LCD_Position(0u, 0u);
//LCD_PrintString("BMS DEMO");
DEBUG_UART_PutString("BMS DEMO START\n");
LCD_Position(1u,0u);
LCD_PrintString("System OK");
//LCD_Position(1u,0u);
//LCD_PrintString("System OK");
CyDelay(500);
// TODO Watchdog Timer

@@ -64,7 +64,6 @@ int main(void)
uint16_t temp[NUM_TEMP];
uint16_t battery_current;
uint8_t battery_status;
red_led_1_Write(0);

//initialize err event
fatal_err = NO_ERROR;
@@ -116,15 +115,14 @@ int main(void)

for(;;){
uint8_t event_index=0;
LCD_Position(0u, 0u);
LCD_PrintString("FATAL ERR FATAL ERR FA");
//LCD_Position(0u, 0u);
//LCD_PrintString("FATAL ERR FATAL ERR FA");
for (;;){
//fatal error
CyDelay(500);
if (WDT_should_clear()) {
WDT_clear();
}//even in fatal error, the bms should keep alive
red_led_1_Write(1);
OK_SIG_Write(0);

for (event_index =0; event_index<16;event_index++){