{"payload":{"header_redesign_enabled":false,"results":[{"id":"732417406","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"ujjwal-2001/HDL-Bits-Solutions","hl_trunc_description":"This repo contains HDL-bits solutions","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":732417406,"name":"HDL-Bits-Solutions","owner_id":149869490,"owner_login":"ujjwal-2001","updated_at":"2024-05-13T15:50:50.141Z","has_issues":true}},"sponsorable":false,"topics":["hdl","verilog-hdl","practice-verilog","hdl-bits","hdl-bits-solutions"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":62,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aujjwal-2001%252FHDL-Bits-Solutions%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ujjwal-2001/HDL-Bits-Solutions/star":{"post":"TwhTXu6_ib2Tka_448vUURWjr26CqQAq6uTGSoA4IfkhN8aBzG4k4W3Mv18Arz1WbpJgE3mpzWgs4I7c-VfdGw"},"/ujjwal-2001/HDL-Bits-Solutions/unstar":{"post":"IrEcs8ro8VBWg-ERsIMEWNnsqHlV_TwcRV9CcKhNL5816ptNO86WDkNGqnBM3hX26CmSJWqYto-xELY_mIkhzg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"PwqVIMq5zaKg1TQun8Hc8hca4lQHtpeIPwwO0hbWt_2DqJhYzbalA80sMIA_25Ht8tEQwnOu9L_2WsBf1YTTRw"}}},"title":"Repository search results"}