From 09767476372d2982a547ff512c90a3c77a8bec4d Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Sat, 19 Jun 2010 18:21:40 +0200 Subject: [PATCH] Joyrider Dingux port --- src/Makefile | 2988 +---------------------- src/Makefile.linux | 283 +-- src/asfont.cpp | 124 + src/asfont.h | 49 + src/cpu.cpp | 98 + src/cpu.h | 24 + src/dirdialog.cpp | 16 +- src/filedialog.cpp | 8 +- src/filelister.cpp | 4 +- src/filelister.h | 2 +- src/gmenu2x.cpp | 367 ++- src/gmenu2x.h | 18 +- src/imagedialog.cpp | 2 +- src/jz4740.h | 5212 ++++++++++++++++++++++++++++++++++++++++ src/linkapp.cpp | 60 +- src/linkapp.h | 6 + src/menu.cpp | 29 +- src/menusetting.h | 2 +- src/menusettingint.cpp | 7 +- src/menusettingint.h | 4 +- src/selector.cpp | 2 +- src/selectordetector.h | 4 +- src/sfontplus.cpp | 232 +- src/sfontplus.h | 38 +- src/surface.cpp | 8 +- src/surface.h | 5 +- src/textdialog.cpp | 4 +- 27 files changed, 5973 insertions(+), 3623 deletions(-) create mode 100644 src/asfont.cpp create mode 100644 src/asfont.h create mode 100644 src/cpu.cpp create mode 100644 src/cpu.h create mode 100644 src/jz4740.h diff --git a/src/Makefile b/src/Makefile index 840bf49..09dd5e3 100644 --- a/src/Makefile +++ b/src/Makefile @@ -1,5 +1,5 @@ -CHAINPREFIX=$(OPEN2X) -CROSS_COMPILE=$(CHAINPREFIX)/bin/arm-open2x-linux- +CHAINPREFIX=/opt/mipsel-linux-uclibc/usr +CROSS_COMPILE=$(CHAINPREFIX)/bin/mipsel-linux- CC= $(CROSS_COMPILE)gcc CXX = $(CROSS_COMPILE)g++ @@ -45,2987 +45,3 @@ shared: $(OBJS) $(TXML_OBJS) clean: -rm -f $(OBJDIR)/*.o $(OBJDIR)/tinyxml/*.o $(TARGET) - -depend: - makedepend -p$(OBJDIR)/ -- $(CFLAGS) -- *.cpp -# DO NOT DELETE - -../objs/gp2x/button.o: button.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_main.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_stdinc.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_config.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_platform.h -../objs/gp2x/button.o: /usr/include/sys/types.h /usr/include/features.h -../objs/gp2x/button.o: /usr/include/sys/cdefs.h /usr/include/bits/wordsize.h -../objs/gp2x/button.o: /usr/include/gnu/stubs.h /usr/include/gnu/stubs-32.h -../objs/gp2x/button.o: /usr/include/bits/types.h -../objs/gp2x/button.o: /usr/include/bits/typesizes.h /usr/include/time.h -../objs/gp2x/button.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/gp2x/button.o: /usr/include/bits/byteswap.h /usr/include/sys/select.h -../objs/gp2x/button.o: /usr/include/bits/select.h /usr/include/bits/sigset.h -../objs/gp2x/button.o: /usr/include/bits/time.h /usr/include/sys/sysmacros.h -../objs/gp2x/button.o: /usr/include/bits/pthreadtypes.h /usr/include/stdio.h -../objs/gp2x/button.o: /usr/include/libio.h /usr/include/_G_config.h -../objs/gp2x/button.o: /usr/include/wchar.h /usr/include/bits/stdio_lim.h -../objs/gp2x/button.o: /usr/include/bits/sys_errlist.h /usr/include/stdlib.h -../objs/gp2x/button.o: /usr/include/bits/waitflags.h -../objs/gp2x/button.o: /usr/include/bits/waitstatus.h /usr/include/xlocale.h -../objs/gp2x/button.o: /usr/include/alloca.h /usr/include/string.h -../objs/gp2x/button.o: /usr/include/strings.h /usr/include/inttypes.h -../objs/gp2x/button.o: /usr/include/stdint.h /usr/include/bits/wchar.h -../objs/gp2x/button.o: /usr/include/ctype.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/iconv.h -../objs/gp2x/button.o: /usr/include/errno.h /usr/include/bits/errno.h -../objs/gp2x/button.o: /usr/include/linux/errno.h /usr/include/asm/errno.h -../objs/gp2x/button.o: /usr/include/asm-generic/errno.h -../objs/gp2x/button.o: /usr/include/asm-generic/errno-base.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/begin_code.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/close_code.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_audio.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_error.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_endian.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mutex.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_thread.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_rwops.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cdrom.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cpuinfo.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_events.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_active.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keyboard.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keysym.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mouse.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_video.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_joystick.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_quit.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_loadso.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_timer.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_version.h -../objs/gp2x/button.o: FastDelegate.h /usr/include/memory.h gmenu2x.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/dense_hash_map -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/sparsehash/sparseconfig.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/sparsehash/densehashtable.h -../objs/gp2x/button.o: /usr/include/assert.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/type_traits.h -../objs/gp2x/button.o: surfacecollection.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/dense_hash_map -../objs/gp2x/button.o: surface.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_image.h -../objs/gp2x/button.o: utilities.h -../objs/gp2x/button.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_gfxPrimitives.h -../objs/gp2x/button.o: /usr/include/math.h /usr/include/bits/huge_val.h -../objs/gp2x/button.o: /usr/include/bits/huge_valf.h -../objs/gp2x/button.o: /usr/include/bits/huge_vall.h /usr/include/bits/inf.h -../objs/gp2x/button.o: /usr/include/bits/nan.h /usr/include/bits/mathdef.h -../objs/gp2x/button.o: /usr/include/bits/mathcalls.h iconbutton.h -../objs/gp2x/button.o: translator.h touchscreen.h /usr/include/fcntl.h -../objs/gp2x/button.o: /usr/include/bits/fcntl.h /usr/include/bits/uio.h -../objs/gp2x/button.o: /usr/include/sys/stat.h /usr/include/bits/stat.h -../objs/gp2x/button.o: inputmanager.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_main.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_stdinc.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_config.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_platform.h -../objs/gp2x/dirdialog.o: /usr/include/sys/types.h /usr/include/features.h -../objs/gp2x/dirdialog.o: /usr/include/sys/cdefs.h -../objs/gp2x/dirdialog.o: /usr/include/bits/wordsize.h -../objs/gp2x/dirdialog.o: /usr/include/gnu/stubs.h -../objs/gp2x/dirdialog.o: /usr/include/gnu/stubs-32.h -../objs/gp2x/dirdialog.o: /usr/include/bits/types.h -../objs/gp2x/dirdialog.o: /usr/include/bits/typesizes.h /usr/include/time.h -../objs/gp2x/dirdialog.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/gp2x/dirdialog.o: /usr/include/bits/byteswap.h -../objs/gp2x/dirdialog.o: /usr/include/sys/select.h -../objs/gp2x/dirdialog.o: /usr/include/bits/select.h -../objs/gp2x/dirdialog.o: /usr/include/bits/sigset.h /usr/include/bits/time.h -../objs/gp2x/dirdialog.o: /usr/include/sys/sysmacros.h -../objs/gp2x/dirdialog.o: /usr/include/bits/pthreadtypes.h -../objs/gp2x/dirdialog.o: /usr/include/stdio.h /usr/include/libio.h -../objs/gp2x/dirdialog.o: /usr/include/_G_config.h /usr/include/wchar.h -../objs/gp2x/dirdialog.o: /usr/include/bits/stdio_lim.h -../objs/gp2x/dirdialog.o: /usr/include/bits/sys_errlist.h -../objs/gp2x/dirdialog.o: /usr/include/stdlib.h /usr/include/bits/waitflags.h -../objs/gp2x/dirdialog.o: /usr/include/bits/waitstatus.h -../objs/gp2x/dirdialog.o: /usr/include/xlocale.h /usr/include/alloca.h -../objs/gp2x/dirdialog.o: /usr/include/string.h /usr/include/strings.h -../objs/gp2x/dirdialog.o: /usr/include/inttypes.h /usr/include/stdint.h -../objs/gp2x/dirdialog.o: /usr/include/bits/wchar.h /usr/include/ctype.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/iconv.h -../objs/gp2x/dirdialog.o: /usr/include/errno.h /usr/include/bits/errno.h -../objs/gp2x/dirdialog.o: /usr/include/linux/errno.h /usr/include/asm/errno.h -../objs/gp2x/dirdialog.o: /usr/include/asm-generic/errno.h -../objs/gp2x/dirdialog.o: /usr/include/asm-generic/errno-base.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/begin_code.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/close_code.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_audio.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_error.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_endian.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mutex.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_thread.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_rwops.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cdrom.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cpuinfo.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_events.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_active.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keyboard.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keysym.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mouse.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_video.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_joystick.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_quit.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_loadso.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_timer.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_version.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_gfxPrimitives.h -../objs/gp2x/dirdialog.o: /usr/include/math.h /usr/include/bits/huge_val.h -../objs/gp2x/dirdialog.o: /usr/include/bits/huge_valf.h -../objs/gp2x/dirdialog.o: /usr/include/bits/huge_vall.h -../objs/gp2x/dirdialog.o: /usr/include/bits/inf.h /usr/include/bits/nan.h -../objs/gp2x/dirdialog.o: /usr/include/bits/mathdef.h -../objs/gp2x/dirdialog.o: /usr/include/bits/mathcalls.h -../objs/gp2x/dirdialog.o: /usr/include/sys/stat.h /usr/include/bits/stat.h -../objs/gp2x/dirdialog.o: /usr/include/dirent.h /usr/include/bits/dirent.h -../objs/gp2x/dirdialog.o: /usr/include/bits/posix1_lim.h -../objs/gp2x/dirdialog.o: /usr/include/bits/local_lim.h -../objs/gp2x/dirdialog.o: /usr/include/linux/limits.h dirdialog.h gmenu2x.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/dense_hash_map -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/sparsehash/sparseconfig.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/sparsehash/densehashtable.h -../objs/gp2x/dirdialog.o: /usr/include/assert.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/type_traits.h -../objs/gp2x/dirdialog.o: surfacecollection.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/dense_hash_map -../objs/gp2x/dirdialog.o: surface.h -../objs/gp2x/dirdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_image.h -../objs/gp2x/dirdialog.o: utilities.h iconbutton.h button.h FastDelegate.h -../objs/gp2x/dirdialog.o: /usr/include/memory.h translator.h touchscreen.h -../objs/gp2x/dirdialog.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h -../objs/gp2x/dirdialog.o: /usr/include/bits/uio.h inputmanager.h filelister.h -../objs/gp2x/filedialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL.h -../objs/gp2x/filedialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_main.h -../objs/gp2x/filedialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_stdinc.h -../objs/gp2x/filedialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_config.h -../objs/gp2x/filedialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_platform.h -../objs/gp2x/filedialog.o: /usr/include/sys/types.h /usr/include/features.h -../objs/gp2x/filedialog.o: /usr/include/sys/cdefs.h -../objs/gp2x/filedialog.o: /usr/include/bits/wordsize.h -../objs/gp2x/filedialog.o: /usr/include/gnu/stubs.h -../objs/gp2x/filedialog.o: /usr/include/gnu/stubs-32.h -../objs/gp2x/filedialog.o: /usr/include/bits/types.h -../objs/gp2x/filedialog.o: /usr/include/bits/typesizes.h /usr/include/time.h -../objs/gp2x/filedialog.o: /usr/include/endian.h /usr/include/bits/endian.h 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-../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_error.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_endian.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mutex.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_thread.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_rwops.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cdrom.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cpuinfo.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_events.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_active.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keyboard.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keysym.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mouse.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_video.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_joystick.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_quit.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_loadso.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_timer.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_version.h -../objs/gp2x/utilities.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_gfxPrimitives.h -../objs/gp2x/utilities.o: /usr/include/math.h /usr/include/bits/huge_val.h -../objs/gp2x/utilities.o: /usr/include/bits/huge_valf.h -../objs/gp2x/utilities.o: /usr/include/bits/huge_vall.h -../objs/gp2x/utilities.o: /usr/include/bits/inf.h /usr/include/bits/nan.h -../objs/gp2x/utilities.o: /usr/include/bits/mathdef.h -../objs/gp2x/utilities.o: /usr/include/bits/mathcalls.h -../objs/gp2x/wallpaperdialog.o: wallpaperdialog.h gmenu2x.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/dense_hash_map -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/sparsehash/sparseconfig.h -../objs/gp2x/wallpaperdialog.o: /usr/include/stdio.h /usr/include/features.h -../objs/gp2x/wallpaperdialog.o: /usr/include/sys/cdefs.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/wordsize.h -../objs/gp2x/wallpaperdialog.o: /usr/include/gnu/stubs.h -../objs/gp2x/wallpaperdialog.o: /usr/include/gnu/stubs-32.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/types.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/typesizes.h -../objs/gp2x/wallpaperdialog.o: /usr/include/libio.h /usr/include/_G_config.h -../objs/gp2x/wallpaperdialog.o: /usr/include/wchar.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/stdio_lim.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/sys_errlist.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/sparsehash/densehashtable.h -../objs/gp2x/wallpaperdialog.o: /usr/include/assert.h /usr/include/stdlib.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/waitflags.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/waitstatus.h -../objs/gp2x/wallpaperdialog.o: /usr/include/endian.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/endian.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/byteswap.h -../objs/gp2x/wallpaperdialog.o: /usr/include/xlocale.h -../objs/gp2x/wallpaperdialog.o: /usr/include/sys/types.h /usr/include/time.h -../objs/gp2x/wallpaperdialog.o: /usr/include/sys/select.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/select.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/sigset.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/time.h -../objs/gp2x/wallpaperdialog.o: /usr/include/sys/sysmacros.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/pthreadtypes.h -../objs/gp2x/wallpaperdialog.o: /usr/include/alloca.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/type_traits.h -../objs/gp2x/wallpaperdialog.o: surfacecollection.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/google/dense_hash_map -../objs/gp2x/wallpaperdialog.o: surface.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_main.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_stdinc.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_config.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_platform.h -../objs/gp2x/wallpaperdialog.o: /usr/include/string.h /usr/include/strings.h -../objs/gp2x/wallpaperdialog.o: /usr/include/inttypes.h /usr/include/stdint.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/wchar.h -../objs/gp2x/wallpaperdialog.o: /usr/include/ctype.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/iconv.h -../objs/gp2x/wallpaperdialog.o: /usr/include/errno.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/errno.h -../objs/gp2x/wallpaperdialog.o: /usr/include/linux/errno.h -../objs/gp2x/wallpaperdialog.o: /usr/include/asm/errno.h -../objs/gp2x/wallpaperdialog.o: /usr/include/asm-generic/errno.h -../objs/gp2x/wallpaperdialog.o: /usr/include/asm-generic/errno-base.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/begin_code.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/close_code.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_audio.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_error.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_endian.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mutex.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_thread.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_rwops.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cdrom.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_cpuinfo.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_events.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_active.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keyboard.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_keysym.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_mouse.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_video.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_joystick.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_quit.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_loadso.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_timer.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_version.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_image.h -../objs/gp2x/wallpaperdialog.o: utilities.h -../objs/gp2x/wallpaperdialog.o: /opt/open2x/gcc-4.1.1-glibc-2.3.6/include/SDL/SDL_gfxPrimitives.h -../objs/gp2x/wallpaperdialog.o: /usr/include/math.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/huge_val.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/huge_valf.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/huge_vall.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/inf.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/nan.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/mathdef.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/mathcalls.h iconbutton.h -../objs/gp2x/wallpaperdialog.o: button.h FastDelegate.h /usr/include/memory.h -../objs/gp2x/wallpaperdialog.o: translator.h touchscreen.h -../objs/gp2x/wallpaperdialog.o: /usr/include/fcntl.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/fcntl.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/uio.h -../objs/gp2x/wallpaperdialog.o: /usr/include/sys/stat.h -../objs/gp2x/wallpaperdialog.o: /usr/include/bits/stat.h inputmanager.h -../objs/gp2x/wallpaperdialog.o: filelister.h diff --git a/src/Makefile.linux b/src/Makefile.linux index 68521c0..3a84c4a 100644 --- a/src/Makefile.linux +++ b/src/Makefile.linux @@ -6,7 +6,7 @@ STRIP = strip CFLAGS = -I"/usr/include" -I"$(CHAINPREFIX)/include" `sdl-config --cflags` -DDEBUG -DTARGET_PANDORA -Wall -Wno-deprecated -Wno-unknown-pragmas -Wno-format -pg -O3 -DTIXML_USE_STL CXXFLAGS = $(CFLAGS) -LDFLAGS = -L"/usr/lib" -L"$(CHAINPREFIX)/lib" `sdl-config --libs` -lfreetype -lSDL_image -lSDL_ttf -lSDL_gfx -ljpeg -lpng12 -lz #-lpnd #-lSDL_gfx +LDFLAGS = -L"/usr/lib" -L"$(CHAINPREFIX)/lib" `sdl-config --libs` -lfreetype -lSDL_image -lSDL_gfx -ljpeg -lpng12 -lz #-lpnd #-lSDL_gfx TARGET = ../build/gmenu OBJDIR = ../objs/linux @@ -43,6 +43,58 @@ depend: makedepend -fMakefile.linux -p$(OBJDIR)/ -- $(CFLAGS) -- *.cpp # DO NOT DELETE +../objs/linux/asfont.o: asfont.h /usr/include/SDL/SDL.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_main.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_stdinc.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_config.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_platform.h +../objs/linux/asfont.o: /usr/include/sys/types.h /usr/include/features.h +../objs/linux/asfont.o: /usr/include/sys/cdefs.h /usr/include/bits/wordsize.h +../objs/linux/asfont.o: /usr/include/gnu/stubs.h /usr/include/gnu/stubs-32.h +../objs/linux/asfont.o: /usr/include/bits/types.h +../objs/linux/asfont.o: /usr/include/bits/typesizes.h /usr/include/time.h +../objs/linux/asfont.o: /usr/include/endian.h /usr/include/bits/endian.h +../objs/linux/asfont.o: /usr/include/sys/select.h /usr/include/bits/select.h +../objs/linux/asfont.o: /usr/include/bits/sigset.h /usr/include/bits/time.h +../objs/linux/asfont.o: /usr/include/sys/sysmacros.h +../objs/linux/asfont.o: /usr/include/bits/pthreadtypes.h /usr/include/stdio.h +../objs/linux/asfont.o: /usr/include/libio.h /usr/include/_G_config.h +../objs/linux/asfont.o: /usr/include/wchar.h /usr/include/bits/stdio_lim.h +../objs/linux/asfont.o: /usr/include/bits/sys_errlist.h /usr/include/stdlib.h +../objs/linux/asfont.o: /usr/include/bits/waitflags.h +../objs/linux/asfont.o: /usr/include/bits/waitstatus.h /usr/include/xlocale.h +../objs/linux/asfont.o: /usr/include/alloca.h /usr/include/string.h +../objs/linux/asfont.o: /usr/include/strings.h /usr/include/inttypes.h +../objs/linux/asfont.o: /usr/include/stdint.h /usr/include/bits/wchar.h +../objs/linux/asfont.o: /usr/include/ctype.h /usr/include/iconv.h +../objs/linux/asfont.o: /usr/include/SDL/begin_code.h +../objs/linux/asfont.o: /usr/include/SDL/close_code.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_audio.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_error.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_endian.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_mutex.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_thread.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_rwops.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_cdrom.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_cpuinfo.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_events.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_active.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_keyboard.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_keysym.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_mouse.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_video.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_joystick.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_quit.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_loadso.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_timer.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_version.h sfontplus.h surface.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/asfont.o: /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/asfont.o: /usr/include/math.h /usr/include/bits/huge_val.h +../objs/linux/asfont.o: /usr/include/bits/huge_valf.h +../objs/linux/asfont.o: /usr/include/bits/huge_vall.h /usr/include/bits/inf.h +../objs/linux/asfont.o: /usr/include/bits/nan.h /usr/include/bits/mathdef.h +../objs/linux/asfont.o: /usr/include/bits/mathcalls.h ../objs/linux/button.o: button.h /usr/include/SDL/SDL.h ../objs/linux/button.o: /usr/include/SDL/SDL_main.h ../objs/linux/button.o: /usr/include/SDL/SDL_stdinc.h @@ -54,7 +106,6 @@ depend: ../objs/linux/button.o: /usr/include/bits/types.h ../objs/linux/button.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/button.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/button.o: /usr/include/bits/byteswap.h ../objs/linux/button.o: /usr/include/sys/select.h /usr/include/bits/select.h ../objs/linux/button.o: /usr/include/bits/sigset.h /usr/include/bits/time.h ../objs/linux/button.o: /usr/include/sys/sysmacros.h @@ -96,8 +147,8 @@ depend: ../objs/linux/button.o: /usr/include/assert.h ../objs/linux/button.o: /usr/include/google/type_traits.h surfacecollection.h ../objs/linux/button.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/button.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/button.o: /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/button.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/button.o: utilities.h /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/button.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/button.o: /usr/include/bits/huge_valf.h ../objs/linux/button.o: /usr/include/bits/huge_vall.h /usr/include/bits/inf.h @@ -119,7 +170,6 @@ depend: ../objs/linux/dirdialog.o: /usr/include/bits/types.h ../objs/linux/dirdialog.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/dirdialog.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/dirdialog.o: /usr/include/bits/byteswap.h ../objs/linux/dirdialog.o: /usr/include/sys/select.h ../objs/linux/dirdialog.o: /usr/include/bits/select.h ../objs/linux/dirdialog.o: /usr/include/bits/sigset.h @@ -177,8 +227,8 @@ depend: ../objs/linux/dirdialog.o: /usr/include/google/type_traits.h ../objs/linux/dirdialog.o: surfacecollection.h ../objs/linux/dirdialog.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/dirdialog.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/dirdialog.o: iconbutton.h button.h FastDelegate.h +../objs/linux/dirdialog.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/dirdialog.o: utilities.h iconbutton.h button.h FastDelegate.h ../objs/linux/dirdialog.o: /usr/include/memory.h translator.h touchscreen.h ../objs/linux/dirdialog.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h ../objs/linux/dirdialog.o: /usr/include/bits/uio.h inputmanager.h @@ -196,7 +246,6 @@ depend: ../objs/linux/filedialog.o: /usr/include/bits/types.h ../objs/linux/filedialog.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/filedialog.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/filedialog.o: /usr/include/bits/byteswap.h ../objs/linux/filedialog.o: /usr/include/sys/select.h ../objs/linux/filedialog.o: /usr/include/bits/select.h ../objs/linux/filedialog.o: /usr/include/bits/sigset.h @@ -256,8 +305,8 @@ depend: ../objs/linux/filedialog.o: /usr/include/google/type_traits.h ../objs/linux/filedialog.o: surfacecollection.h ../objs/linux/filedialog.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/filedialog.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/filedialog.o: iconbutton.h button.h FastDelegate.h +../objs/linux/filedialog.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/filedialog.o: utilities.h iconbutton.h button.h FastDelegate.h ../objs/linux/filedialog.o: /usr/include/memory.h translator.h touchscreen.h ../objs/linux/filedialog.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h ../objs/linux/filedialog.o: /usr/include/bits/uio.h inputmanager.h @@ -270,7 +319,6 @@ depend: ../objs/linux/filelister.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/filelister.o: /usr/include/bits/stat.h /usr/include/sys/types.h ../objs/linux/filelister.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/filelister.o: /usr/include/bits/byteswap.h ../objs/linux/filelister.o: /usr/include/sys/select.h ../objs/linux/filelister.o: /usr/include/bits/select.h ../objs/linux/filelister.o: /usr/include/bits/sigset.h @@ -337,8 +385,7 @@ depend: ../objs/linux/gmenu2x.o: /usr/include/gnu/stubs.h /usr/include/gnu/stubs-32.h ../objs/linux/gmenu2x.o: /usr/include/bits/waitflags.h ../objs/linux/gmenu2x.o: /usr/include/bits/waitstatus.h /usr/include/endian.h -../objs/linux/gmenu2x.o: /usr/include/bits/endian.h -../objs/linux/gmenu2x.o: /usr/include/bits/byteswap.h /usr/include/xlocale.h +../objs/linux/gmenu2x.o: /usr/include/bits/endian.h /usr/include/xlocale.h ../objs/linux/gmenu2x.o: /usr/include/sys/types.h /usr/include/bits/types.h ../objs/linux/gmenu2x.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/gmenu2x.o: /usr/include/sys/select.h /usr/include/bits/select.h @@ -424,7 +471,7 @@ depend: ../objs/linux/gmenu2x.o: /usr/include/linux/ioctl.h ../objs/linux/gmenu2x.o: /usr/include/linux/patchkey.h linkapp.h link.h ../objs/linux/gmenu2x.o: button.h FastDelegate.h /usr/include/memory.h -../objs/linux/gmenu2x.o: linkaction.h menu.h sfontplus.h surface.h +../objs/linux/gmenu2x.o: linkaction.h menu.h asfont.h sfontplus.h surface.h ../objs/linux/gmenu2x.o: /usr/include/SDL/SDL_image.h filedialog.h ../objs/linux/gmenu2x.o: filelister.h gmenu2x.h ../objs/linux/gmenu2x.o: /usr/include/google/dense_hash_map @@ -455,7 +502,6 @@ depend: ../objs/linux/iconbutton.o: /usr/include/bits/types.h ../objs/linux/iconbutton.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/iconbutton.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/iconbutton.o: /usr/include/bits/byteswap.h ../objs/linux/iconbutton.o: /usr/include/sys/select.h ../objs/linux/iconbutton.o: /usr/include/bits/select.h ../objs/linux/iconbutton.o: /usr/include/bits/sigset.h @@ -503,8 +549,8 @@ depend: ../objs/linux/iconbutton.o: /usr/include/google/type_traits.h ../objs/linux/iconbutton.o: surfacecollection.h ../objs/linux/iconbutton.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/iconbutton.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/iconbutton.o: /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/iconbutton.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/iconbutton.o: utilities.h /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/iconbutton.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/iconbutton.o: /usr/include/bits/huge_valf.h ../objs/linux/iconbutton.o: /usr/include/bits/huge_vall.h @@ -529,7 +575,6 @@ depend: ../objs/linux/imagedialog.o: /usr/include/bits/typesizes.h ../objs/linux/imagedialog.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/imagedialog.o: /usr/include/bits/endian.h -../objs/linux/imagedialog.o: /usr/include/bits/byteswap.h ../objs/linux/imagedialog.o: /usr/include/sys/select.h ../objs/linux/imagedialog.o: /usr/include/bits/select.h ../objs/linux/imagedialog.o: /usr/include/bits/sigset.h @@ -589,10 +634,11 @@ depend: ../objs/linux/imagedialog.o: /usr/include/google/type_traits.h ../objs/linux/imagedialog.o: surfacecollection.h ../objs/linux/imagedialog.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/imagedialog.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/imagedialog.o: iconbutton.h button.h FastDelegate.h -../objs/linux/imagedialog.o: /usr/include/memory.h translator.h touchscreen.h -../objs/linux/imagedialog.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h +../objs/linux/imagedialog.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/imagedialog.o: sfontplus.h utilities.h iconbutton.h button.h +../objs/linux/imagedialog.o: FastDelegate.h /usr/include/memory.h +../objs/linux/imagedialog.o: translator.h touchscreen.h /usr/include/fcntl.h +../objs/linux/imagedialog.o: /usr/include/bits/fcntl.h ../objs/linux/imagedialog.o: /usr/include/bits/uio.h inputmanager.h ../objs/linux/inputdialog.o: /usr/include/SDL/SDL.h ../objs/linux/inputdialog.o: /usr/include/SDL/SDL_main.h @@ -608,7 +654,6 @@ depend: ../objs/linux/inputdialog.o: /usr/include/bits/typesizes.h ../objs/linux/inputdialog.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/inputdialog.o: /usr/include/bits/endian.h -../objs/linux/inputdialog.o: /usr/include/bits/byteswap.h ../objs/linux/inputdialog.o: /usr/include/sys/select.h ../objs/linux/inputdialog.o: /usr/include/bits/select.h ../objs/linux/inputdialog.o: /usr/include/bits/sigset.h @@ -662,10 +707,11 @@ depend: ../objs/linux/inputdialog.o: /usr/include/google/type_traits.h ../objs/linux/inputdialog.o: surfacecollection.h ../objs/linux/inputdialog.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/inputdialog.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/inputdialog.o: iconbutton.h button.h FastDelegate.h -../objs/linux/inputdialog.o: /usr/include/memory.h translator.h touchscreen.h -../objs/linux/inputdialog.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h +../objs/linux/inputdialog.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/inputdialog.o: sfontplus.h utilities.h iconbutton.h button.h +../objs/linux/inputdialog.o: FastDelegate.h /usr/include/memory.h +../objs/linux/inputdialog.o: translator.h touchscreen.h /usr/include/fcntl.h +../objs/linux/inputdialog.o: /usr/include/bits/fcntl.h ../objs/linux/inputdialog.o: /usr/include/bits/uio.h /usr/include/sys/stat.h ../objs/linux/inputdialog.o: /usr/include/bits/stat.h inputmanager.h ../objs/linux/inputmanager.o: inputmanager.h /usr/include/SDL/SDL.h @@ -683,7 +729,6 @@ depend: ../objs/linux/inputmanager.o: /usr/include/bits/typesizes.h ../objs/linux/inputmanager.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/inputmanager.o: /usr/include/bits/endian.h -../objs/linux/inputmanager.o: /usr/include/bits/byteswap.h ../objs/linux/inputmanager.o: /usr/include/sys/select.h ../objs/linux/inputmanager.o: /usr/include/bits/select.h ../objs/linux/inputmanager.o: /usr/include/bits/sigset.h @@ -742,10 +787,9 @@ depend: ../objs/linux/link.o: /usr/include/gnu/stubs.h /usr/include/gnu/stubs-32.h ../objs/linux/link.o: /usr/include/bits/types.h /usr/include/bits/typesizes.h ../objs/linux/link.o: /usr/include/time.h /usr/include/endian.h -../objs/linux/link.o: /usr/include/bits/endian.h /usr/include/bits/byteswap.h -../objs/linux/link.o: /usr/include/sys/select.h /usr/include/bits/select.h -../objs/linux/link.o: /usr/include/bits/sigset.h /usr/include/bits/time.h -../objs/linux/link.o: /usr/include/sys/sysmacros.h +../objs/linux/link.o: /usr/include/bits/endian.h /usr/include/sys/select.h +../objs/linux/link.o: /usr/include/bits/select.h /usr/include/bits/sigset.h +../objs/linux/link.o: /usr/include/bits/time.h /usr/include/sys/sysmacros.h ../objs/linux/link.o: /usr/include/bits/pthreadtypes.h /usr/include/stdio.h ../objs/linux/link.o: /usr/include/libio.h /usr/include/_G_config.h ../objs/linux/link.o: /usr/include/wchar.h /usr/include/bits/stdio_lim.h @@ -783,7 +827,8 @@ depend: ../objs/linux/link.o: /usr/include/google/sparsehash/densehashtable.h ../objs/linux/link.o: /usr/include/assert.h /usr/include/google/type_traits.h ../objs/linux/link.o: surfacecollection.h /usr/include/google/dense_hash_map -../objs/linux/link.o: surface.h /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/link.o: surface.h /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/link.o: sfontplus.h utilities.h ../objs/linux/link.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/link.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/link.o: /usr/include/bits/huge_valf.h @@ -808,7 +853,6 @@ depend: ../objs/linux/linkaction.o: /usr/include/bits/types.h ../objs/linux/linkaction.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/linkaction.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/linkaction.o: /usr/include/bits/byteswap.h ../objs/linux/linkaction.o: /usr/include/sys/select.h ../objs/linux/linkaction.o: /usr/include/bits/select.h ../objs/linux/linkaction.o: /usr/include/bits/sigset.h @@ -855,7 +899,6 @@ depend: ../objs/linux/linkapp.o: /usr/include/bits/types.h ../objs/linux/linkapp.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/linkapp.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/linkapp.o: /usr/include/bits/byteswap.h ../objs/linux/linkapp.o: /usr/include/sys/select.h /usr/include/bits/select.h ../objs/linux/linkapp.o: /usr/include/bits/sigset.h /usr/include/bits/time.h ../objs/linux/linkapp.o: /usr/include/sys/sysmacros.h @@ -907,8 +950,8 @@ depend: ../objs/linux/linkapp.o: /usr/include/google/type_traits.h ../objs/linux/linkapp.o: surfacecollection.h ../objs/linux/linkapp.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/linkapp.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/linkapp.o: /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/linkapp.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/linkapp.o: utilities.h /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/linkapp.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/linkapp.o: /usr/include/bits/huge_valf.h ../objs/linux/linkapp.o: /usr/include/bits/huge_vall.h @@ -936,9 +979,8 @@ depend: ../objs/linux/listview.o: /usr/include/bits/waitflags.h ../objs/linux/listview.o: /usr/include/bits/waitstatus.h ../objs/linux/listview.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/listview.o: /usr/include/bits/byteswap.h /usr/include/xlocale.h -../objs/linux/listview.o: /usr/include/sys/types.h /usr/include/time.h -../objs/linux/listview.o: /usr/include/sys/select.h +../objs/linux/listview.o: /usr/include/xlocale.h /usr/include/sys/types.h +../objs/linux/listview.o: /usr/include/time.h /usr/include/sys/select.h ../objs/linux/listview.o: /usr/include/bits/select.h ../objs/linux/listview.o: /usr/include/bits/sigset.h /usr/include/bits/time.h ../objs/linux/listview.o: /usr/include/sys/sysmacros.h @@ -975,8 +1017,8 @@ depend: ../objs/linux/listview.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/listview.o: /usr/include/SDL/SDL_timer.h ../objs/linux/listview.o: /usr/include/SDL/SDL_version.h -../objs/linux/listview.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/listview.o: /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/listview.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/listview.o: utilities.h /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/listview.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/listview.o: /usr/include/bits/huge_valf.h ../objs/linux/listview.o: /usr/include/bits/huge_vall.h @@ -1008,7 +1050,6 @@ depend: ../objs/linux/listviewitem.o: /usr/include/bits/waitstatus.h ../objs/linux/listviewitem.o: /usr/include/endian.h ../objs/linux/listviewitem.o: /usr/include/bits/endian.h -../objs/linux/listviewitem.o: /usr/include/bits/byteswap.h ../objs/linux/listviewitem.o: /usr/include/xlocale.h /usr/include/sys/types.h ../objs/linux/listviewitem.o: /usr/include/time.h /usr/include/sys/select.h ../objs/linux/listviewitem.o: /usr/include/bits/select.h @@ -1050,7 +1091,8 @@ depend: ../objs/linux/listviewitem.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/listviewitem.o: /usr/include/SDL/SDL_timer.h ../objs/linux/listviewitem.o: /usr/include/SDL/SDL_version.h -../objs/linux/listviewitem.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/listviewitem.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/listviewitem.o: sfontplus.h utilities.h ../objs/linux/listviewitem.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/listviewitem.o: /usr/include/math.h ../objs/linux/listviewitem.o: /usr/include/bits/huge_val.h @@ -1071,10 +1113,9 @@ depend: ../objs/linux/menu.o: /usr/include/bits/types.h /usr/include/bits/typesizes.h ../objs/linux/menu.o: /usr/include/time.h /usr/include/bits/stat.h ../objs/linux/menu.o: /usr/include/sys/types.h /usr/include/endian.h -../objs/linux/menu.o: /usr/include/bits/endian.h /usr/include/bits/byteswap.h -../objs/linux/menu.o: /usr/include/sys/select.h /usr/include/bits/select.h -../objs/linux/menu.o: /usr/include/bits/sigset.h /usr/include/bits/time.h -../objs/linux/menu.o: /usr/include/sys/sysmacros.h +../objs/linux/menu.o: /usr/include/bits/endian.h /usr/include/sys/select.h +../objs/linux/menu.o: /usr/include/bits/select.h /usr/include/bits/sigset.h +../objs/linux/menu.o: /usr/include/bits/time.h /usr/include/sys/sysmacros.h ../objs/linux/menu.o: /usr/include/bits/pthreadtypes.h /usr/include/dirent.h ../objs/linux/menu.o: /usr/include/bits/dirent.h ../objs/linux/menu.o: /usr/include/bits/posix1_lim.h @@ -1084,27 +1125,26 @@ depend: ../objs/linux/menu.o: /usr/include/bits/huge_valf.h ../objs/linux/menu.o: /usr/include/bits/huge_vall.h /usr/include/bits/inf.h ../objs/linux/menu.o: /usr/include/bits/nan.h /usr/include/bits/mathdef.h -../objs/linux/menu.o: /usr/include/bits/mathcalls.h gmenu2x.h -../objs/linux/menu.o: /usr/include/google/dense_hash_map -../objs/linux/menu.o: /usr/include/google/sparsehash/sparseconfig.h +../objs/linux/menu.o: /usr/include/bits/mathcalls.h tinyxml/tinyxml.h +../objs/linux/menu.o: /usr/include/ctype.h /usr/include/xlocale.h ../objs/linux/menu.o: /usr/include/stdio.h /usr/include/libio.h ../objs/linux/menu.o: /usr/include/_G_config.h /usr/include/wchar.h ../objs/linux/menu.o: /usr/include/bits/stdio_lim.h -../objs/linux/menu.o: /usr/include/bits/sys_errlist.h -../objs/linux/menu.o: /usr/include/google/sparsehash/densehashtable.h -../objs/linux/menu.o: /usr/include/assert.h /usr/include/stdlib.h +../objs/linux/menu.o: /usr/include/bits/sys_errlist.h /usr/include/stdlib.h ../objs/linux/menu.o: /usr/include/bits/waitflags.h -../objs/linux/menu.o: /usr/include/bits/waitstatus.h /usr/include/xlocale.h -../objs/linux/menu.o: /usr/include/alloca.h /usr/include/google/type_traits.h -../objs/linux/menu.o: surfacecollection.h /usr/include/google/dense_hash_map -../objs/linux/menu.o: surface.h /usr/include/SDL/SDL.h -../objs/linux/menu.o: /usr/include/SDL/SDL_main.h +../objs/linux/menu.o: /usr/include/bits/waitstatus.h /usr/include/alloca.h +../objs/linux/menu.o: /usr/include/string.h /usr/include/assert.h gmenu2x.h +../objs/linux/menu.o: /usr/include/google/dense_hash_map +../objs/linux/menu.o: /usr/include/google/sparsehash/sparseconfig.h +../objs/linux/menu.o: /usr/include/google/sparsehash/densehashtable.h +../objs/linux/menu.o: /usr/include/google/type_traits.h surfacecollection.h +../objs/linux/menu.o: /usr/include/google/dense_hash_map surface.h +../objs/linux/menu.o: /usr/include/SDL/SDL.h /usr/include/SDL/SDL_main.h ../objs/linux/menu.o: /usr/include/SDL/SDL_stdinc.h ../objs/linux/menu.o: /usr/include/SDL/SDL_config.h -../objs/linux/menu.o: /usr/include/SDL/SDL_platform.h /usr/include/string.h -../objs/linux/menu.o: /usr/include/strings.h /usr/include/inttypes.h -../objs/linux/menu.o: /usr/include/stdint.h /usr/include/bits/wchar.h -../objs/linux/menu.o: /usr/include/ctype.h /usr/include/iconv.h +../objs/linux/menu.o: /usr/include/SDL/SDL_platform.h /usr/include/strings.h +../objs/linux/menu.o: /usr/include/inttypes.h /usr/include/stdint.h +../objs/linux/menu.o: /usr/include/bits/wchar.h /usr/include/iconv.h ../objs/linux/menu.o: /usr/include/SDL/begin_code.h ../objs/linux/menu.o: /usr/include/SDL/close_code.h ../objs/linux/menu.o: /usr/include/SDL/SDL_audio.h @@ -1126,13 +1166,13 @@ depend: ../objs/linux/menu.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menu.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menu.o: /usr/include/SDL/SDL_version.h -../objs/linux/menu.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/menu.o: /usr/include/SDL/SDL_gfxPrimitives.h iconbutton.h -../objs/linux/menu.o: button.h FastDelegate.h /usr/include/memory.h -../objs/linux/menu.o: translator.h touchscreen.h /usr/include/fcntl.h -../objs/linux/menu.o: /usr/include/bits/fcntl.h /usr/include/bits/uio.h -../objs/linux/menu.o: inputmanager.h linkapp.h link.h menu.h linkaction.h -../objs/linux/menu.o: filelister.h pxml.h +../objs/linux/menu.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/menu.o: utilities.h /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/menu.o: iconbutton.h button.h FastDelegate.h +../objs/linux/menu.o: /usr/include/memory.h translator.h touchscreen.h +../objs/linux/menu.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h +../objs/linux/menu.o: /usr/include/bits/uio.h inputmanager.h linkapp.h link.h +../objs/linux/menu.o: menu.h linkaction.h filelister.h ../objs/linux/menusetting.o: menusetting.h gmenu2x.h ../objs/linux/menusetting.o: /usr/include/google/dense_hash_map ../objs/linux/menusetting.o: /usr/include/google/sparsehash/sparseconfig.h @@ -1152,7 +1192,6 @@ depend: ../objs/linux/menusetting.o: /usr/include/bits/waitflags.h ../objs/linux/menusetting.o: /usr/include/bits/waitstatus.h ../objs/linux/menusetting.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/menusetting.o: /usr/include/bits/byteswap.h ../objs/linux/menusetting.o: /usr/include/xlocale.h /usr/include/sys/types.h ../objs/linux/menusetting.o: /usr/include/time.h /usr/include/sys/select.h ../objs/linux/menusetting.o: /usr/include/bits/select.h @@ -1194,7 +1233,8 @@ depend: ../objs/linux/menusetting.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusetting.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusetting.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusetting.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusetting.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusetting.o: sfontplus.h utilities.h ../objs/linux/menusetting.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusetting.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/menusetting.o: /usr/include/bits/huge_valf.h @@ -1223,7 +1263,6 @@ depend: ../objs/linux/menusettingbool.o: /usr/include/bits/typesizes.h ../objs/linux/menusettingbool.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/menusettingbool.o: /usr/include/bits/endian.h -../objs/linux/menusettingbool.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingbool.o: /usr/include/sys/select.h ../objs/linux/menusettingbool.o: /usr/include/bits/select.h ../objs/linux/menusettingbool.o: /usr/include/bits/sigset.h @@ -1274,7 +1313,8 @@ depend: ../objs/linux/menusettingbool.o: /usr/include/google/type_traits.h ../objs/linux/menusettingbool.o: surfacecollection.h ../objs/linux/menusettingbool.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/menusettingbool.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingbool.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingbool.o: sfontplus.h utilities.h ../objs/linux/menusettingbool.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingbool.o: /usr/include/math.h ../objs/linux/menusettingbool.o: /usr/include/bits/huge_val.h @@ -1309,7 +1349,6 @@ depend: ../objs/linux/menusettingdir.o: /usr/include/bits/waitstatus.h ../objs/linux/menusettingdir.o: /usr/include/endian.h ../objs/linux/menusettingdir.o: /usr/include/bits/endian.h -../objs/linux/menusettingdir.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingdir.o: /usr/include/xlocale.h ../objs/linux/menusettingdir.o: /usr/include/sys/types.h /usr/include/time.h ../objs/linux/menusettingdir.o: /usr/include/sys/select.h @@ -1352,7 +1391,8 @@ depend: ../objs/linux/menusettingdir.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusettingdir.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusettingdir.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusettingdir.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingdir.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingdir.o: sfontplus.h utilities.h ../objs/linux/menusettingdir.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingdir.o: /usr/include/math.h ../objs/linux/menusettingdir.o: /usr/include/bits/huge_val.h @@ -1391,7 +1431,6 @@ depend: ../objs/linux/menusettingfile.o: /usr/include/bits/waitstatus.h ../objs/linux/menusettingfile.o: /usr/include/endian.h ../objs/linux/menusettingfile.o: /usr/include/bits/endian.h -../objs/linux/menusettingfile.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingfile.o: /usr/include/xlocale.h ../objs/linux/menusettingfile.o: /usr/include/sys/types.h /usr/include/time.h ../objs/linux/menusettingfile.o: /usr/include/sys/select.h @@ -1435,7 +1474,8 @@ depend: ../objs/linux/menusettingfile.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusettingfile.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusettingfile.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusettingfile.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingfile.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingfile.o: sfontplus.h utilities.h ../objs/linux/menusettingfile.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingfile.o: /usr/include/math.h ../objs/linux/menusettingfile.o: /usr/include/bits/huge_val.h @@ -1475,7 +1515,6 @@ depend: ../objs/linux/menusettingimage.o: /usr/include/bits/waitstatus.h ../objs/linux/menusettingimage.o: /usr/include/endian.h ../objs/linux/menusettingimage.o: /usr/include/bits/endian.h -../objs/linux/menusettingimage.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingimage.o: /usr/include/xlocale.h ../objs/linux/menusettingimage.o: /usr/include/sys/types.h ../objs/linux/menusettingimage.o: /usr/include/time.h @@ -1521,7 +1560,8 @@ depend: ../objs/linux/menusettingimage.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusettingimage.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusettingimage.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusettingimage.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingimage.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingimage.o: sfontplus.h utilities.h ../objs/linux/menusettingimage.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingimage.o: /usr/include/math.h ../objs/linux/menusettingimage.o: /usr/include/bits/huge_val.h @@ -1556,7 +1596,6 @@ depend: ../objs/linux/menusettingint.o: /usr/include/bits/typesizes.h ../objs/linux/menusettingint.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/menusettingint.o: /usr/include/bits/endian.h -../objs/linux/menusettingint.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingint.o: /usr/include/sys/select.h ../objs/linux/menusettingint.o: /usr/include/bits/select.h ../objs/linux/menusettingint.o: /usr/include/bits/sigset.h @@ -1604,7 +1643,8 @@ depend: ../objs/linux/menusettingint.o: /usr/include/google/type_traits.h ../objs/linux/menusettingint.o: surfacecollection.h ../objs/linux/menusettingint.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/menusettingint.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingint.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingint.o: sfontplus.h utilities.h ../objs/linux/menusettingint.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingint.o: /usr/include/math.h ../objs/linux/menusettingint.o: /usr/include/bits/huge_val.h @@ -1642,7 +1682,6 @@ depend: ../objs/linux/menusettingmultistring.o: /usr/include/bits/waitstatus.h ../objs/linux/menusettingmultistring.o: /usr/include/endian.h ../objs/linux/menusettingmultistring.o: /usr/include/bits/endian.h -../objs/linux/menusettingmultistring.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingmultistring.o: /usr/include/xlocale.h ../objs/linux/menusettingmultistring.o: /usr/include/sys/types.h ../objs/linux/menusettingmultistring.o: /usr/include/time.h @@ -1689,8 +1728,8 @@ depend: ../objs/linux/menusettingmultistring.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusettingmultistring.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusettingmultistring.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusettingmultistring.o: /usr/include/SDL/SDL_image.h -../objs/linux/menusettingmultistring.o: utilities.h +../objs/linux/menusettingmultistring.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingmultistring.o: sfontplus.h utilities.h ../objs/linux/menusettingmultistring.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingmultistring.o: /usr/include/math.h ../objs/linux/menusettingmultistring.o: /usr/include/bits/huge_val.h @@ -1729,7 +1768,6 @@ depend: ../objs/linux/menusettingrgba.o: /usr/include/bits/waitstatus.h ../objs/linux/menusettingrgba.o: /usr/include/endian.h ../objs/linux/menusettingrgba.o: /usr/include/bits/endian.h -../objs/linux/menusettingrgba.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingrgba.o: /usr/include/xlocale.h ../objs/linux/menusettingrgba.o: /usr/include/sys/types.h /usr/include/time.h ../objs/linux/menusettingrgba.o: /usr/include/sys/select.h @@ -1773,7 +1811,8 @@ depend: ../objs/linux/menusettingrgba.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusettingrgba.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusettingrgba.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusettingrgba.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingrgba.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingrgba.o: sfontplus.h utilities.h ../objs/linux/menusettingrgba.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingrgba.o: /usr/include/math.h ../objs/linux/menusettingrgba.o: /usr/include/bits/huge_val.h @@ -1814,7 +1853,6 @@ depend: ../objs/linux/menusettingstring.o: /usr/include/bits/waitstatus.h ../objs/linux/menusettingstring.o: /usr/include/endian.h ../objs/linux/menusettingstring.o: /usr/include/bits/endian.h -../objs/linux/menusettingstring.o: /usr/include/bits/byteswap.h ../objs/linux/menusettingstring.o: /usr/include/xlocale.h ../objs/linux/menusettingstring.o: /usr/include/sys/types.h ../objs/linux/menusettingstring.o: /usr/include/time.h @@ -1860,7 +1898,8 @@ depend: ../objs/linux/menusettingstring.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/menusettingstring.o: /usr/include/SDL/SDL_timer.h ../objs/linux/menusettingstring.o: /usr/include/SDL/SDL_version.h -../objs/linux/menusettingstring.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/menusettingstring.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/menusettingstring.o: sfontplus.h utilities.h ../objs/linux/menusettingstring.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/menusettingstring.o: /usr/include/math.h ../objs/linux/menusettingstring.o: /usr/include/bits/huge_val.h @@ -1891,7 +1930,6 @@ depend: ../objs/linux/messagebox.o: /usr/include/bits/types.h ../objs/linux/messagebox.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/messagebox.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/messagebox.o: /usr/include/bits/byteswap.h ../objs/linux/messagebox.o: /usr/include/sys/select.h ../objs/linux/messagebox.o: /usr/include/bits/select.h ../objs/linux/messagebox.o: /usr/include/bits/sigset.h @@ -1945,29 +1983,12 @@ depend: ../objs/linux/messagebox.o: /usr/include/google/type_traits.h ../objs/linux/messagebox.o: surfacecollection.h ../objs/linux/messagebox.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/messagebox.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/messagebox.o: iconbutton.h button.h FastDelegate.h +../objs/linux/messagebox.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/messagebox.o: utilities.h iconbutton.h button.h FastDelegate.h ../objs/linux/messagebox.o: /usr/include/memory.h translator.h touchscreen.h ../objs/linux/messagebox.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h ../objs/linux/messagebox.o: /usr/include/bits/uio.h /usr/include/sys/stat.h ../objs/linux/messagebox.o: /usr/include/bits/stat.h inputmanager.h -../objs/linux/pxml.o: pxml.h tinyxml/tinyxml.h /usr/include/ctype.h -../objs/linux/pxml.o: /usr/include/features.h /usr/include/sys/cdefs.h -../objs/linux/pxml.o: /usr/include/bits/wordsize.h /usr/include/gnu/stubs.h -../objs/linux/pxml.o: /usr/include/gnu/stubs-32.h /usr/include/bits/types.h -../objs/linux/pxml.o: /usr/include/bits/typesizes.h /usr/include/endian.h -../objs/linux/pxml.o: /usr/include/bits/endian.h /usr/include/bits/byteswap.h -../objs/linux/pxml.o: /usr/include/xlocale.h /usr/include/stdio.h -../objs/linux/pxml.o: /usr/include/libio.h /usr/include/_G_config.h -../objs/linux/pxml.o: /usr/include/wchar.h /usr/include/bits/stdio_lim.h -../objs/linux/pxml.o: /usr/include/bits/sys_errlist.h /usr/include/stdlib.h -../objs/linux/pxml.o: /usr/include/bits/waitflags.h -../objs/linux/pxml.o: /usr/include/bits/waitstatus.h /usr/include/sys/types.h -../objs/linux/pxml.o: /usr/include/time.h /usr/include/sys/select.h -../objs/linux/pxml.o: /usr/include/bits/select.h /usr/include/bits/sigset.h -../objs/linux/pxml.o: /usr/include/bits/time.h /usr/include/sys/sysmacros.h -../objs/linux/pxml.o: /usr/include/bits/pthreadtypes.h /usr/include/alloca.h -../objs/linux/pxml.o: /usr/include/string.h /usr/include/assert.h ../objs/linux/selector.o: /usr/include/SDL/SDL.h /usr/include/SDL/SDL_main.h ../objs/linux/selector.o: /usr/include/SDL/SDL_stdinc.h ../objs/linux/selector.o: /usr/include/SDL/SDL_config.h @@ -1980,7 +2001,6 @@ depend: ../objs/linux/selector.o: /usr/include/bits/types.h ../objs/linux/selector.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/selector.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/selector.o: /usr/include/bits/byteswap.h ../objs/linux/selector.o: /usr/include/sys/select.h ../objs/linux/selector.o: /usr/include/bits/select.h ../objs/linux/selector.o: /usr/include/bits/sigset.h /usr/include/bits/time.h @@ -2038,8 +2058,8 @@ depend: ../objs/linux/selector.o: /usr/include/google/type_traits.h ../objs/linux/selector.o: surfacecollection.h ../objs/linux/selector.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/selector.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/selector.o: iconbutton.h translator.h touchscreen.h +../objs/linux/selector.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/selector.o: utilities.h iconbutton.h translator.h touchscreen.h ../objs/linux/selector.o: /usr/include/fcntl.h /usr/include/bits/fcntl.h ../objs/linux/selector.o: /usr/include/bits/uio.h inputmanager.h filelister.h ../objs/linux/selectordetector.o: selectordetector.h utilities.h @@ -2058,7 +2078,6 @@ depend: ../objs/linux/selectordetector.o: /usr/include/bits/typesizes.h ../objs/linux/selectordetector.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/selectordetector.o: /usr/include/bits/endian.h -../objs/linux/selectordetector.o: /usr/include/bits/byteswap.h ../objs/linux/selectordetector.o: /usr/include/sys/select.h ../objs/linux/selectordetector.o: /usr/include/bits/select.h ../objs/linux/selectordetector.o: /usr/include/bits/sigset.h @@ -2125,7 +2144,6 @@ depend: ../objs/linux/settingsdialog.o: /usr/include/bits/typesizes.h ../objs/linux/settingsdialog.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/settingsdialog.o: /usr/include/bits/endian.h -../objs/linux/settingsdialog.o: /usr/include/bits/byteswap.h ../objs/linux/settingsdialog.o: /usr/include/sys/select.h ../objs/linux/settingsdialog.o: /usr/include/bits/select.h ../objs/linux/settingsdialog.o: /usr/include/bits/sigset.h @@ -2182,10 +2200,11 @@ depend: ../objs/linux/settingsdialog.o: /usr/include/google/type_traits.h ../objs/linux/settingsdialog.o: surfacecollection.h ../objs/linux/settingsdialog.o: /usr/include/google/dense_hash_map surface.h -../objs/linux/settingsdialog.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/settingsdialog.o: iconbutton.h button.h FastDelegate.h -../objs/linux/settingsdialog.o: /usr/include/memory.h translator.h -../objs/linux/settingsdialog.o: touchscreen.h /usr/include/fcntl.h +../objs/linux/settingsdialog.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/settingsdialog.o: sfontplus.h utilities.h iconbutton.h button.h +../objs/linux/settingsdialog.o: FastDelegate.h /usr/include/memory.h +../objs/linux/settingsdialog.o: translator.h touchscreen.h +../objs/linux/settingsdialog.o: /usr/include/fcntl.h ../objs/linux/settingsdialog.o: /usr/include/bits/fcntl.h ../objs/linux/settingsdialog.o: /usr/include/bits/uio.h ../objs/linux/settingsdialog.o: /usr/include/sys/stat.h @@ -2204,7 +2223,6 @@ depend: ../objs/linux/sfontplus.o: /usr/include/bits/types.h ../objs/linux/sfontplus.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/sfontplus.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/sfontplus.o: /usr/include/bits/byteswap.h ../objs/linux/sfontplus.o: /usr/include/sys/select.h ../objs/linux/sfontplus.o: /usr/include/bits/select.h ../objs/linux/sfontplus.o: /usr/include/bits/sigset.h @@ -2242,9 +2260,8 @@ depend: ../objs/linux/sfontplus.o: /usr/include/SDL/SDL_quit.h ../objs/linux/sfontplus.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/sfontplus.o: /usr/include/SDL/SDL_timer.h -../objs/linux/sfontplus.o: /usr/include/SDL/SDL_version.h surface.h +../objs/linux/sfontplus.o: /usr/include/SDL/SDL_version.h ../objs/linux/sfontplus.o: /usr/include/SDL/SDL_image.h -../objs/linux/sfontplus.o: /usr/include/SDL/SDL_ttf.h ../objs/linux/surface.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/surface.o: /usr/include/math.h /usr/include/features.h ../objs/linux/surface.o: /usr/include/sys/cdefs.h @@ -2263,7 +2280,6 @@ depend: ../objs/linux/surface.o: /usr/include/sys/types.h /usr/include/bits/types.h ../objs/linux/surface.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/surface.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/surface.o: /usr/include/bits/byteswap.h ../objs/linux/surface.o: /usr/include/sys/select.h /usr/include/bits/select.h ../objs/linux/surface.o: /usr/include/bits/sigset.h /usr/include/bits/time.h ../objs/linux/surface.o: /usr/include/sys/sysmacros.h @@ -2299,7 +2315,8 @@ depend: ../objs/linux/surface.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/surface.o: /usr/include/SDL/SDL_timer.h ../objs/linux/surface.o: /usr/include/SDL/SDL_version.h surface.h -../objs/linux/surface.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/surface.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/surface.o: utilities.h ../objs/linux/surfacecollection.o: surfacecollection.h ../objs/linux/surfacecollection.o: /usr/include/google/dense_hash_map ../objs/linux/surfacecollection.o: surface.h /usr/include/SDL/SDL.h @@ -2317,7 +2334,6 @@ depend: ../objs/linux/surfacecollection.o: /usr/include/bits/typesizes.h ../objs/linux/surfacecollection.o: /usr/include/time.h /usr/include/endian.h ../objs/linux/surfacecollection.o: /usr/include/bits/endian.h -../objs/linux/surfacecollection.o: /usr/include/bits/byteswap.h ../objs/linux/surfacecollection.o: /usr/include/sys/select.h ../objs/linux/surfacecollection.o: /usr/include/bits/select.h ../objs/linux/surfacecollection.o: /usr/include/bits/sigset.h @@ -2361,7 +2377,8 @@ depend: ../objs/linux/surfacecollection.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/surfacecollection.o: /usr/include/SDL/SDL_timer.h ../objs/linux/surfacecollection.o: /usr/include/SDL/SDL_version.h -../objs/linux/surfacecollection.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/surfacecollection.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/surfacecollection.o: sfontplus.h utilities.h ../objs/linux/surfacecollection.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/surfacecollection.o: /usr/include/math.h ../objs/linux/surfacecollection.o: /usr/include/bits/huge_val.h @@ -2390,7 +2407,6 @@ depend: ../objs/linux/textdialog.o: /usr/include/bits/waitflags.h ../objs/linux/textdialog.o: /usr/include/bits/waitstatus.h ../objs/linux/textdialog.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/textdialog.o: /usr/include/bits/byteswap.h ../objs/linux/textdialog.o: /usr/include/xlocale.h /usr/include/sys/types.h ../objs/linux/textdialog.o: /usr/include/time.h /usr/include/sys/select.h ../objs/linux/textdialog.o: /usr/include/bits/select.h @@ -2432,8 +2448,8 @@ depend: ../objs/linux/textdialog.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/textdialog.o: /usr/include/SDL/SDL_timer.h ../objs/linux/textdialog.o: /usr/include/SDL/SDL_version.h -../objs/linux/textdialog.o: /usr/include/SDL/SDL_image.h utilities.h -../objs/linux/textdialog.o: /usr/include/SDL/SDL_gfxPrimitives.h +../objs/linux/textdialog.o: /usr/include/SDL/SDL_image.h asfont.h sfontplus.h +../objs/linux/textdialog.o: utilities.h /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/textdialog.o: /usr/include/math.h /usr/include/bits/huge_val.h ../objs/linux/textdialog.o: /usr/include/bits/huge_valf.h ../objs/linux/textdialog.o: /usr/include/bits/huge_vall.h @@ -2467,7 +2483,6 @@ depend: ../objs/linux/textmanualdialog.o: /usr/include/bits/waitstatus.h ../objs/linux/textmanualdialog.o: /usr/include/endian.h ../objs/linux/textmanualdialog.o: /usr/include/bits/endian.h -../objs/linux/textmanualdialog.o: /usr/include/bits/byteswap.h ../objs/linux/textmanualdialog.o: /usr/include/xlocale.h ../objs/linux/textmanualdialog.o: /usr/include/sys/types.h ../objs/linux/textmanualdialog.o: /usr/include/time.h @@ -2513,7 +2528,8 @@ depend: ../objs/linux/textmanualdialog.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/textmanualdialog.o: /usr/include/SDL/SDL_timer.h ../objs/linux/textmanualdialog.o: /usr/include/SDL/SDL_version.h -../objs/linux/textmanualdialog.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/textmanualdialog.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/textmanualdialog.o: sfontplus.h utilities.h ../objs/linux/textmanualdialog.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/textmanualdialog.o: /usr/include/math.h ../objs/linux/textmanualdialog.o: /usr/include/bits/huge_val.h @@ -2548,7 +2564,6 @@ depend: ../objs/linux/touchscreen.o: /usr/include/SDL/SDL_platform.h ../objs/linux/touchscreen.o: /usr/include/sys/types.h /usr/include/time.h ../objs/linux/touchscreen.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/touchscreen.o: /usr/include/bits/byteswap.h ../objs/linux/touchscreen.o: /usr/include/sys/select.h ../objs/linux/touchscreen.o: /usr/include/bits/select.h ../objs/linux/touchscreen.o: /usr/include/bits/sigset.h @@ -2604,7 +2619,6 @@ depend: ../objs/linux/translator.o: /usr/include/bits/types.h ../objs/linux/translator.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/translator.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/translator.o: /usr/include/bits/byteswap.h ../objs/linux/translator.o: /usr/include/sys/select.h ../objs/linux/translator.o: /usr/include/bits/select.h ../objs/linux/translator.o: /usr/include/bits/sigset.h @@ -2660,7 +2674,6 @@ depend: ../objs/linux/utilities.o: /usr/include/bits/typesizes.h /usr/include/time.h ../objs/linux/utilities.o: /usr/include/bits/stat.h /usr/include/sys/types.h ../objs/linux/utilities.o: /usr/include/endian.h /usr/include/bits/endian.h -../objs/linux/utilities.o: /usr/include/bits/byteswap.h ../objs/linux/utilities.o: /usr/include/sys/select.h ../objs/linux/utilities.o: /usr/include/bits/select.h ../objs/linux/utilities.o: /usr/include/bits/sigset.h @@ -2735,7 +2748,6 @@ depend: ../objs/linux/wallpaperdialog.o: /usr/include/bits/waitstatus.h ../objs/linux/wallpaperdialog.o: /usr/include/endian.h ../objs/linux/wallpaperdialog.o: /usr/include/bits/endian.h -../objs/linux/wallpaperdialog.o: /usr/include/bits/byteswap.h ../objs/linux/wallpaperdialog.o: /usr/include/xlocale.h ../objs/linux/wallpaperdialog.o: /usr/include/sys/types.h /usr/include/time.h ../objs/linux/wallpaperdialog.o: /usr/include/sys/select.h @@ -2779,7 +2791,8 @@ depend: ../objs/linux/wallpaperdialog.o: /usr/include/SDL/SDL_loadso.h ../objs/linux/wallpaperdialog.o: /usr/include/SDL/SDL_timer.h ../objs/linux/wallpaperdialog.o: /usr/include/SDL/SDL_version.h -../objs/linux/wallpaperdialog.o: /usr/include/SDL/SDL_image.h utilities.h +../objs/linux/wallpaperdialog.o: /usr/include/SDL/SDL_image.h asfont.h +../objs/linux/wallpaperdialog.o: sfontplus.h utilities.h ../objs/linux/wallpaperdialog.o: /usr/include/SDL/SDL_gfxPrimitives.h ../objs/linux/wallpaperdialog.o: /usr/include/math.h ../objs/linux/wallpaperdialog.o: /usr/include/bits/huge_val.h diff --git a/src/asfont.cpp b/src/asfont.cpp new file mode 100644 index 0000000..e6cfdbb --- /dev/null +++ b/src/asfont.cpp @@ -0,0 +1,124 @@ +#include "asfont.h" +#include "surface.h" +#include "utilities.h" + +#include + +using namespace std; + +ASFont::ASFont(SDL_Surface* font) { + this->font.initFont(font); + halfHeight = getHeight()/2; + halfLineHeight = getLineHeight()/2; +} + +ASFont::ASFont(Surface* font) { + this->font.initFont(font->raw); + halfHeight = getHeight()/2; + halfLineHeight = getLineHeight()/2; +} + +ASFont::ASFont(string font) { + this->font.initFont(font); + halfHeight = getHeight()/2; + halfLineHeight = getLineHeight()/2; +} + +ASFont::~ASFont() { + font.freeFont(); +} + +bool ASFont::utf8Code(unsigned char c) { + return font.utf8Code(c); +} + +void ASFont::write(SDL_Surface* surface, const char* text, int x, int y) { + font.write(surface, text, x, y); +} + +void ASFont::write(SDL_Surface* surface, const std::string& text, int x, int y, const unsigned short halign, const unsigned short valign) { + switch (halign) { + case SFontHAlignCenter: + x -= getTextWidth(text)/2; + break; + case SFontHAlignRight: + x -= getTextWidth(text); + break; + } + + switch (valign) { + case SFontVAlignMiddle: + y -= getHalfHeight(); + break; + case SFontVAlignBottom: + y -= getHeight(); + break; + } + + font.write(surface, text, x, y); +} +void ASFont::write(SDL_Surface* surface, vector *text, int x, int y, const unsigned short halign, const unsigned short valign) { + switch (valign) { + case SFontVAlignMiddle: + y -= getHalfHeight()*text->size(); + break; + case SFontVAlignBottom: + y -= getHeight()*text->size(); + break; + } + + for (uint i=0; isize(); i++) { + int ix = x; + switch (halign) { + case SFontHAlignCenter: + ix -= getTextWidth(text->at(i))/2; + break; + case SFontHAlignRight: + ix -= getTextWidth(text->at(i)); + break; + } + + font.write(surface, text->at(i), x, y+getHeight()*i); + } +} + +void ASFont::write(Surface* surface, const std::string& text, int x, int y, const unsigned short halign, const unsigned short valign) { + if (text.find("\n",0)!=string::npos) { + vector textArr; + split(textArr,text,"\n"); + write(surface->raw, &textArr, x, y, halign, valign); + } else + write(surface->raw, text, x, y, halign, valign); +} + +int ASFont::getHeight() { + return font.getHeight(); +} +int ASFont::getHalfHeight() { + return halfHeight; +} + +int ASFont::getLineHeight() { + return font.getLineHeight(); +} +int ASFont::getHalfLineHeight() { + return halfLineHeight; +} + +int ASFont::getTextWidth(const char* text) { + return font.getTextWidth(text); +} +int ASFont::getTextWidth(const std::string& text) { + if (text.find("\n",0)!=string::npos) { + vector textArr; + split(textArr,text,"\n"); + return getTextWidth(&textArr); + } else + return getTextWidth(text.c_str()); +} +int ASFont::getTextWidth(vector *text) { + int w = 0; + for (uint i=0; isize(); i++) + w = max( getTextWidth(text->at(i).c_str()), w ); + return w; +} diff --git a/src/asfont.h b/src/asfont.h new file mode 100644 index 0000000..b28efcb --- /dev/null +++ b/src/asfont.h @@ -0,0 +1,49 @@ +//Advanced SFont by Massimiliano Torromeo (cpp wrapper around SFont) + +#ifndef ASFONT_H +#define ASFONT_H + +#include +#include +#include +#include "sfontplus.h" + +using std::string; +using std::vector; + +const unsigned short SFontHAlignLeft = 0; +const unsigned short SFontHAlignRight = 1; +const unsigned short SFontHAlignCenter = 2; +const unsigned short SFontVAlignTop = 0; +const unsigned short SFontVAlignBottom = 1; +const unsigned short SFontVAlignMiddle = 2; + +class Surface; + +class ASFont { +public: + ASFont(SDL_Surface* font); + ASFont(Surface* font); + ASFont(string font); + ~ASFont(); + + bool utf8Code(unsigned char c); + + int getHeight(); + int getHalfHeight(); + int getLineHeight(); + int getHalfLineHeight(); + int getTextWidth(const char* text); + int getTextWidth(const string& text); + int getTextWidth(vector *text); + void write(SDL_Surface* surface, const char* text, int x, int y); + void write(SDL_Surface* surface, const std::string& text, int x, int y, const unsigned short halign = 0, const unsigned short valign = 0); + void write(SDL_Surface* surface, vector *text, int x, int y, const unsigned short halign = 0, const unsigned short valign = 0); + void write(Surface* surface, const std::string& text, int x, int y, const unsigned short halign = 0, const unsigned short valign = 0); + +private: + SFontPlus font; + int halfHeight, halfLineHeight; +}; + +#endif /* ASFONT_H */ diff --git a/src/cpu.cpp b/src/cpu.cpp new file mode 100644 index 0000000..94168f7 --- /dev/null +++ b/src/cpu.cpp @@ -0,0 +1,98 @@ +#include +#include +#include +#include +#include +#include "jz4740.h" +#include "cpu.h" + +inline int sdram_convert(unsigned int pllin,unsigned int *sdram_freq) +{ + register unsigned int ns, tmp; + + ns = 1000000000 / pllin; + /* Set refresh registers */ + tmp = SDRAM_TREF/ns; + tmp = tmp/64 + 1; + if (tmp > 0xff) tmp = 0xff; + *sdram_freq = tmp; + + return 0; + +} + +void pll_init(unsigned int clock) +{ + register unsigned int cfcr, plcr1; + unsigned int sdramclock = 0; + int n2FR[33] = { + 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, + 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, + 9 + }; + //int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */ + int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */ + int nf, pllout2; + + cfcr = CPM_CPCCR_CLKOEN | + (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | + (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | + (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | + (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | + (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); + + pllout2 = (cfcr & CPM_CPCCR_PCS) ? clock : (clock / 2); + + /* Init UHC clock */ +// REG_CPM_UHCCDR = pllout2 / 48000000 - 1; + jz_cpmregl[0x6C>>2] = pllout2 / 48000000 - 1; + + nf = clock * 2 / CFG_EXTAL; + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ + (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ + CPM_CPPCR_PLLEN; /* enable PLL */ + + /* init PLL */ +// REG_CPM_CPCCR = cfcr; +// REG_CPM_CPPCR = plcr1; + jz_cpmregl[0] = cfcr; + jz_cpmregl[0x10>>2] = plcr1; + + sdram_convert(clock,&sdramclock); + if(sdramclock > 0) + { +// REG_EMC_RTCOR = sdramclock; +// REG_EMC_RTCNT = sdramclock; + jz_emcregs[0x8C>>1] = sdramclock; + jz_emcregs[0x88>>1] = sdramclock; + + }else + { + printf("sdram init fail!\n"); + while(1); + } + +} + + +void jz_cpuspeed(unsigned clockspeed) +{ + if (clockspeed >= 200 && clockspeed <= 430) + { + jz_dev = open("/dev/mem", O_RDWR); + if(jz_dev) + { + jz_cpmregl=(unsigned long *)mmap(0, 0x80, PROT_READ|PROT_WRITE, MAP_SHARED, jz_dev, 0x10000000); + jz_emcregl=(unsigned long *)mmap(0, 0x90, PROT_READ|PROT_WRITE, MAP_SHARED, jz_dev, 0x13010000); + jz_emcregs=(unsigned short *)jz_emcregl; + pll_init(clockspeed*1000000); + munmap((void *)jz_cpmregl, 0x80); + munmap((void *)jz_emcregl, 0x90); + close(jz_dev); + } + else + printf("failed opening /dev/mem \n"); + } +} diff --git a/src/cpu.h b/src/cpu.h new file mode 100644 index 0000000..7a05c7e --- /dev/null +++ b/src/cpu.h @@ -0,0 +1,24 @@ +#ifndef CPU_H +#define CPU_H + +/* Define this to the CPU frequency */ +#define CPU_FREQ 336000000 /* CPU clock: 336 MHz */ +#define CFG_EXTAL 12000000 /* EXT clock: 12 Mhz */ + +// SDRAM Timings, unit: ns +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */ +//#define SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */ + +static unsigned long jz_dev; +static volatile unsigned long *jz_cpmregl, *jz_emcregl; +volatile unsigned short *jz_emcregs; + +void jz_cpuspeed(unsigned clockspeed); +void pll_init(unsigned int clock); +inline int sdram_convert(unsigned int pllin,unsigned int *sdram_freq); + +#endif diff --git a/src/dirdialog.cpp b/src/dirdialog.cpp index 4a2e93d..5732412 100644 --- a/src/dirdialog.cpp +++ b/src/dirdialog.cpp @@ -38,7 +38,7 @@ DirDialog::DirDialog(GMenu2X *gmenu2x, string text, string dir) { this->text = text; selRow = 0; if (dir.empty()) - path = "/mnt"; + path = "/boot/local"; else path = dir; @@ -46,7 +46,7 @@ DirDialog::DirDialog(GMenu2X *gmenu2x, string text, string dir) { ButtonAction actionUp = MakeDelegate(this, &DirDialog::up); ButtonAction actionEnter = MakeDelegate(this, &DirDialog::enter); ButtonAction actionConfirm = MakeDelegate(this, &DirDialog::confirm); - + btnUp = new IconButton(gmenu2x, "skin:imgs/buttons/x.png", gmenu2x->tr["Up one folder"]); btnUp->setAction(actionUp); @@ -60,9 +60,9 @@ DirDialog::DirDialog(GMenu2X *gmenu2x, string text, string dir) { bool DirDialog::exec() { bool ts_pressed = false; uint i, firstElement = 0, iY, action; - + if (!fileExists(path)) - path = "/mnt"; + path = "/boot/local"; fl = new FileLister(path,true,false); fl->browse(); @@ -70,7 +70,7 @@ bool DirDialog::exec() { selected = 0; close = false; result = true; - + uint rowHeight = gmenu2x->font->getHeight()+1; // gp2x=15+1 / pandora=19+1 uint numRows = (gmenu2x->resY-gmenu2x->skinConfInt["topBarHeight"]-20)/rowHeight; SDL_Rect clipRect = {0, gmenu2x->skinConfInt["topBarHeight"]+1, gmenu2x->resX-9, gmenu2x->resY-gmenu2x->skinConfInt["topBarHeight"]-25}; @@ -78,7 +78,7 @@ bool DirDialog::exec() { while (!close) { action = DirDialog::ACT_NONE; if (gmenu2x->f200) gmenu2x->ts.poll(); - + gmenu2x->bg->blit(gmenu2x->s,0,0); gmenu2x->drawTitleIcon("icons/explorer.png",true); gmenu2x->writeTitle("Directory Browser"); @@ -173,7 +173,7 @@ bool DirDialog::exec() { } break; } } - + delete(fl); return result; @@ -181,7 +181,7 @@ bool DirDialog::exec() { void DirDialog::up() { string::size_type p = path.rfind("/"); - if (p==string::npos || path.substr(0,4)!="/mnt" || p<4) { + if (p==string::npos || path.substr(0,11)!="/boot/local" || p<4) { close = true; result = false; } else { diff --git a/src/filedialog.cpp b/src/filedialog.cpp index 4e87b39..c0bdacf 100644 --- a/src/filedialog.cpp +++ b/src/filedialog.cpp @@ -35,7 +35,7 @@ FileDialog::FileDialog(GMenu2X *gmenu2x, string text, string filter, string file this->text = text; this->filter = filter; this->file = ""; - setPath("/mnt"); + setPath("/boot/local"); title = "File Browser"; if (!file.empty()) { string::size_type pos = file.rfind("/"); @@ -50,7 +50,7 @@ FileDialog::FileDialog(GMenu2X *gmenu2x, string text, string filter, string file bool FileDialog::exec() { bool close = false, result = true, ts_pressed = false; if (!fileExists(path())) - setPath("/mnt"); + setPath("/boot/local"); fl.setFilter(filter); fl.browse(); @@ -60,7 +60,7 @@ bool FileDialog::exec() { uint numRows = (gmenu2x->resY-gmenu2x->skinConfInt["topBarHeight"]-20)/rowHeight; SDL_Rect clipRect = {0, gmenu2x->skinConfInt["topBarHeight"]+1, gmenu2x->resX-9, gmenu2x->resY-gmenu2x->skinConfInt["topBarHeight"]-25}; SDL_Rect touchRect = {2, gmenu2x->skinConfInt["topBarHeight"]+4, gmenu2x->resX-12, clipRect.h}; - + selected = 0; while (!close) { action = FD_NO_ACTION; @@ -155,7 +155,7 @@ bool FileDialog::exec() { } break; case FD_ACTION_GOUP: { string::size_type p = path().rfind("/"); - if (p==string::npos || path().substr(0,4)!="/mnt" || p<4) + if (p==string::npos || path().substr(0,11)!="/boot/local" || p<4) return false; else setPath( path().substr(0,p) ); diff --git a/src/filelister.cpp b/src/filelister.cpp index bbdc7d5..1543e21 100644 --- a/src/filelister.cpp +++ b/src/filelister.cpp @@ -86,8 +86,8 @@ void FileLister::browse() { if (S_ISDIR(st.st_mode)) { if (!showDirectories) continue; -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) - if (!(path=="/mnt/" && (file!="sd" && file!="ext" && file!="nand"))) +#ifdef TARGET_GP2X +// if (!(path=="/boot/local/" && (file!="sd" && file!="ext" && file!="nand"))) #endif directories.push_back(file); } else { diff --git a/src/filelister.h b/src/filelister.h index e948f78..2f61ea8 100644 --- a/src/filelister.h +++ b/src/filelister.h @@ -33,7 +33,7 @@ class FileLister { bool showDirectories, showFiles; public: - FileLister(string startPath = "/mnt/sd", bool showDirectories = true, bool showFiles = true); + FileLister(string startPath = "/boot/local", bool showDirectories = true, bool showFiles = true); void browse(); vector directories, files, exclude; diff --git a/src/gmenu2x.cpp b/src/gmenu2x.cpp index 1ed5823..57ee737 100644 --- a/src/gmenu2x.cpp +++ b/src/gmenu2x.cpp @@ -19,7 +19,6 @@ ***************************************************************************/ #include -#include #include #include #include @@ -47,6 +46,7 @@ #include "linkapp.h" #include "linkaction.h" #include "menu.h" +#include "asfont.h" #include "sfontplus.h" #include "surface.h" #include "filedialog.h" @@ -91,59 +91,37 @@ int main(int argc, char *argv[]) { void GMenu2X::gp2x_init() { #ifdef TARGET_GP2X - gp2x_mem = open("/dev/mem", O_RDWR); +/* gp2x_mem = open("/dev/mem", O_RDWR); gp2x_memregs=(unsigned short *)mmap(0, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_mem, 0xc0000000); MEM_REG=&gp2x_memregs[0]; - - batteryHandle = open(f200 ? "/dev/mmsp2adc" : "/dev/batt", O_RDONLY); if (f200) { //if wm97xx fails to open, set f200 to false to prevent any further access to the touchscreen f200 = ts.init(); - } -#endif -#ifdef TARGET_WIZ - /* open /dev/mem to access registers */ - wiz_mem = open("/dev/mem", O_RDWR); - if (wiz_mem < 0) { - printf("Could not open /dev/mem!\n"); - } - /* get access to the registers */ - else { - wiz_memregs = (volatile uint32_t*)mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, wiz_mem, 0xC0000000); - if(wiz_memregs == (volatile uint32_t*)0xFFFFFFFF) { - printf("Could not mmap hardware registers!\n"); - close(wiz_mem); - } - } - /* get access to battery device */ - batteryHandle = open("/dev/pollux_batt", O_RDONLY); - printf( "System Init Done!\n" ); + }*/ + batteryHandle = fopen("/proc/jz/battery", "r"); + backlightHandle = fopen("/proc/jz/lcd_backlight","w+"); #endif } void GMenu2X::gp2x_deinit() { #ifdef TARGET_GP2X - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { gp2x_memregs[0x28DA>>1]=0x4AB; gp2x_memregs[0x290C>>1]=640; close(gp2x_mem); } - if (f200) ts.deinit(); -#endif -#ifdef TARGET_WIZ - wiz_memregs = NULL; - close(wiz_mem); -#endif -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) - if (batteryHandle!=0) close(batteryHandle); + + if (f200) ts.deinit();*/ #endif + if (batteryHandle) fclose(batteryHandle); + if (backlightHandle) fclose(backlightHandle); } void GMenu2X::gp2x_tvout_on(bool pal) { #ifdef TARGET_GP2X - if (gp2x_mem!=0) { - /*Ioctl_Dummy_t *msg; - int TVHandle = ioctl(SDL_videofd, FBMMSP2CTRL, msg);*/ +/* if (gp2x_mem!=0) { +// Ioctl_Dummy_t *msg; +// int TVHandle = ioctl(SDL_videofd, FBMMSP2CTRL, msg); if (cx25874!=0) gp2x_tvout_off(); //if tv-out is enabled without cx25874 open, stop //if (gp2x_memregs[0x2800>>1]&0x100) return; @@ -152,17 +130,17 @@ void GMenu2X::gp2x_tvout_on(bool pal) { gp2x_memregs[0x2906>>1]=512; gp2x_memregs[0x28E4>>1]=gp2x_memregs[0x290C>>1]; gp2x_memregs[0x28E8>>1]=239; - } + }*/ #endif } void GMenu2X::gp2x_tvout_off() { #ifdef TARGET_GP2X - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { close(cx25874); cx25874 = 0; gp2x_memregs[0x2906>>1]=1024; - } + }*/ #endif } @@ -231,27 +209,23 @@ GMenu2X::GMenu2X(int argc, char *argv[]) { path = ""; getExePath(); -#ifdef TARGET_WIZ - wiz_mem = 0; -#elif TARGET_GP2X +#ifdef TARGET_GP2X gp2x_mem = 0; cx25874 = 0; -#endif -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) batteryHandle = 0; + backlightHandle = 0; + gp2x_init(); -#endif -#ifdef TARGET_GP2X //Fix tv-out - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { if (gp2x_memregs[0x2800>>1]&0x100) { gp2x_memregs[0x2906>>1]=512; //gp2x_memregs[0x290C>>1]=640; gp2x_memregs[0x28E4>>1]=gp2x_memregs[0x290C>>1]; } gp2x_memregs[0x28E8>>1]=239; - } + }*/ #endif //Screen @@ -261,7 +235,7 @@ GMenu2X::GMenu2X(int argc, char *argv[]) { } s = new Surface(); -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) +#ifdef TARGET_GP2X { //I use a tmp variable to hide the cursor as soon as possible (and create the double buffer surface only after that) //I'm forced to use SW surfaces since with HW there are issuse with changing the clock frequency @@ -296,12 +270,10 @@ GMenu2X::GMenu2X(int argc, char *argv[]) { input.init(path+"input.conf"); setInputSpeed(); initServices(); - - setGamma(confInt["gamma"]); + setBacklight(confInt["backlight"]); setVolume(confInt["globalVolume"]); applyDefaultTimings(); setClock(confInt["menuClock"]); - //recover last session readTmp(); if (lastSelectorElement>-1 && menu->selLinkApp()!=NULL && (!menu->selLinkApp()->getSelectorDir().empty() || !lastSelectorDir.empty())) @@ -330,14 +302,14 @@ void GMenu2X::quit() { s->free(); SDL_Quit(); #ifdef TARGET_GP2X - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { //Fix tv-out if (gp2x_memregs[0x2800>>1]&0x100) { gp2x_memregs[0x2906>>1]=512; gp2x_memregs[0x28E4>>1]=gp2x_memregs[0x290C>>1]; } gp2x_deinit(); - } + }*/ #endif } @@ -400,18 +372,13 @@ void GMenu2X::initFont() { font = NULL; } - bool ttf = false; - string fontFile = sc.getSkinFilePath("font.png"); - if (fontFile.empty()) { - fontFile = sc.getSkinFilePath("font.ttf"); - ttf = true; - } + string fontFile = sc.getSkinFilePath("imgs/font.png"); if (fontFile.empty()) { - cout << "Font not found!" << endl; + cout << "Font png not found!" << endl; quit(); exit(-1); } - font = new SFontPlus(fontFile, ttf, rgbatosdl(skinConfColors["fontColor"]), rgbatosdl(skinConfColors["fontOutlineColor"])); + font = new ASFont(fontFile); } void GMenu2X::initMenu() { @@ -431,11 +398,11 @@ void GMenu2X::initMenu() { menu->addActionLink(i,tr["Skin"],MakeDelegate(this,&GMenu2X::skinMenu),tr["Configure skin"],"skin:icons/skin.png"); menu->addActionLink(i,tr["Wallpaper"],MakeDelegate(this,&GMenu2X::changeWallpaper),tr["Change GMenu2X wallpaper"],"skin:icons/wallpaper.png"); #ifdef TARGET_GP2X - menu->addActionLink(i,"TV",MakeDelegate(this,&GMenu2X::toggleTvOut),tr["Activate/deactivate tv-out"],"skin:icons/tv.png"); +/* menu->addActionLink(i,"TV",MakeDelegate(this,&GMenu2X::toggleTvOut),tr["Activate/deactivate tv-out"],"skin:icons/tv.png"); menu->addActionLink(i,"USB Sd",MakeDelegate(this,&GMenu2X::activateSdUsb),tr["Activate Usb on SD"],"skin:icons/usb.png"); if (fwType=="gph" && !f200) menu->addActionLink(i,"USB Nand",MakeDelegate(this,&GMenu2X::activateNandUsb),tr["Activate Usb on Nand"],"skin:icons/usb.png"); - //menu->addActionLink(i,"USB Root",MakeDelegate(this,&GMenu2X::activateRootUsb),tr["Activate Usb on the root of the Gp2x Filesystem"],"skin:icons/usb.png"); + //menu->addActionLink(i,"USB Root",MakeDelegate(this,&GMenu2X::activateRootUsb),tr["Activate Usb on the root of the Gp2x Filesystem"],"skin:icons/usb.png");*/ #endif if (fileExists(path+"log.txt")) menu->addActionLink(i,tr["Log Viewer"],MakeDelegate(this,&GMenu2X::viewLog),tr["Displays last launched program's output"],"skin:icons/ebook.png"); @@ -449,7 +416,7 @@ void GMenu2X::initMenu() { menu->loadIcons(); //DEBUG - //menu->addLink( "/mnt/sd/development/gmenu2x/", "sample.pxml", "applications" ); + //menu->addLink( "/boot/local/", "sample.pxml", "applications" ); } void GMenu2X::about() { @@ -458,8 +425,6 @@ void GMenu2X::about() { Website: http://gmenu2x.sourceforge.net\n\ E-Mail & PayPal account: massimiliano.torromeo@gmail.com\n\ \n\ -Wiz version by Pickle\n\ -\n\ Thanks goes to...\n\ \n\ Contributors\n\ @@ -552,21 +517,15 @@ void GMenu2X::readConfig() { inf.close(); } } - if (!confStr["lang"].empty()) tr.setLang(confStr["lang"]); if (!confStr["wallpaper"].empty() && !fileExists(confStr["wallpaper"])) confStr["wallpaper"] = ""; if (confStr["skin"].empty() || !fileExists("skins/"+confStr["skin"])) confStr["skin"] = "Default"; evalIntConf( &confInt["outputLogs"], 0, 0,1 ); -#ifdef TARGET_GP2X - evalIntConf( &confInt["maxClock"], 300, 200,300 ); -#endif -#ifdef TARGET_WIZ - evalIntConf( &confInt["maxClock"], 550, 200,900 ); -#endif - evalIntConf( &confInt["menuClock"], f200 ? 136 : 100, 50,300 ); + evalIntConf( &confInt["maxClock"], 430, 200,430 ); + evalIntConf( &confInt["menuClock"], 200, 200,430 ); evalIntConf( &confInt["globalVolume"], 67, 0,100 ); - evalIntConf( &confInt["gamma"], 1, 1,100 ); + evalIntConf( &confInt["backlight"], 100, 5,100 ); evalIntConf( &confInt["videoBpp"], 16, 8,32 ); if (confStr["tvoutEncoding"] != "PAL") confStr["tvoutEncoding"] = "NTSC"; @@ -658,12 +617,7 @@ void GMenu2X::writeSkinConfig() { ConfRGBAHash::iterator endC = skinConfColors.end(); for(ConfRGBAHash::iterator curr = skinConfColors.begin(); curr != endC; curr++) - inf << curr->first << "=#" - << hex << setw(2) << setfill('0') << right << curr->second.r - << hex << setw(2) << setfill('0') << right << curr->second.g - << hex << setw(2) << setfill('0') << right << curr->second.b - << hex << setw(2) << setfill('0') << right << curr->second.a << endl; - + inf << curr->first << "=#" << hex << curr->second.r << hex << curr->second.g << hex << curr->second.b << hex << curr->second.a << endl; inf.close(); sync(); @@ -746,32 +700,66 @@ void GMenu2X::writeTmp(int selelem, string selectordir) { if (selectordir!="") inf << "selectordir=" << selectordir << endl; inf.close(); + sync(); } } void GMenu2X::initServices() { #ifdef TARGET_GP2X - if (usbnet) { +/* if (usbnet) { string services = "scripts/services.sh "+ip+" "+(inet?"on":"off")+" "+(samba?"on":"off")+" "+(web?"on":"off")+" &"; system(services.c_str()); - } + }*/ #endif } void GMenu2X::ledOn() { #ifdef TARGET_GP2X - if (gp2x_mem!=0 && !f200) gp2x_memregs[0x106E >> 1] ^= 16; +// if (gp2x_mem!=0 && !f200) gp2x_memregs[0x106E >> 1] ^= 16; //SDL_SYS_JoystickGp2xSys(joy.joystick, BATT_LED_ON); #endif } void GMenu2X::ledOff() { #ifdef TARGET_GP2X - if (gp2x_mem!=0 && !f200) gp2x_memregs[0x106E >> 1] ^= 16; +// if (gp2x_mem!=0 && !f200) gp2x_memregs[0x106E >> 1] ^= 16; //SDL_SYS_JoystickGp2xSys(joy.joystick, BATT_LED_OFF); #endif } +void GMenu2X::setBacklight(int val) +{ + if ((val >= 0) && (val <=100)) + { + if (backlightHandle) + { + stringstream valsstr; + string valstr = ""; + if (val < 10) + valsstr << "00"; + else if (val < 100) + valsstr << "0" ; + valsstr << val; + valsstr >> valstr; + fprintf(backlightHandle,"%s",valstr.c_str()); + rewind(backlightHandle); + } + } +} + +int GMenu2X::getBackLight() +{ + int val = 100; + if (backlightHandle) + { + char valcstring[4]; + fscanf(backlightHandle,"%s",&valcstring); + rewind(backlightHandle); + val = atoi(valcstring); + } + return val; +} + int GMenu2X::main() { uint linksPerPage = linkColumns*linkRows; int linkSpacingX = (resX-10 - linkColumns*skinConfInt["linkWidth"])/linkColumns; @@ -786,14 +774,14 @@ int GMenu2X::main() { stringstream ss; uint sectionsCoordX = 24; SDL_Rect re = {0,0,0,0}; - + bool helpDisplayed = false; #ifdef DEBUG //framerate long tickFPS = SDL_GetTicks(); int drawn_frames = 0; string fps = ""; #endif - + IconButton btnContextMenu(this,"skin:imgs/menu.png"); btnContextMenu.setPosition(resX-38, bottomBarIconY); btnContextMenu.setAction(MakeDelegate(this, &GMenu2X::contextMenu)); @@ -803,7 +791,7 @@ int GMenu2X::main() { //Background sc["bgmain"]->blit(s,0,0); - + //Sections sectionsCoordX = halfX - (constrain((uint)menu->sections.size(), 0 , linkColumns) * skinConfInt["linkWidth"]) / 2; if (menu->firstDispSection()>0) @@ -823,7 +811,7 @@ int GMenu2X::main() { if (sc.exists(sectionIcon)) sc[sectionIcon]->blit(s,x-16,sectionLinkPadding,32,32); else - sc.skinRes("icons/section.png")->blit(s,x,sectionLinkPadding); + sc.skinRes("icons/section.png")->blit(s,x-16,sectionLinkPadding); s->write( font, menu->sections[i], x, skinConfInt["topBarHeight"]-sectionLinkPadding, SFontHAlignCenter, SFontVAlignBottom ); } @@ -878,9 +866,13 @@ int GMenu2X::main() { } } sc.skinRes(batteryIcon)->blit( s, resX-19, bottomBarIconY ); - + //s->write( font, tr[batstr.c_str()], 20, 170 ); //On Screen Help - if (input[ACTION_A]) { + + if(input[ACTION_A] ) + helpDisplayed = ! helpDisplayed; + + if (helpDisplayed) { s->box(10,50,300,143, skinConfColors["messageBoxBg"]); s->rectangle( 12,52,296,helpBoxHeight, skinConfColors["messageBoxBorder"] ); s->write( font, tr["CONTROLS"], 20, 60 ); @@ -892,6 +884,7 @@ int GMenu2X::main() { s->write( font, tr["SELECT: Show contextual menu"], 20, 155 ); s->write( font, tr["START: Show options menu"], 20, 170 ); if (fwType=="open2x") s->write( font, tr["X: Toggle speaker mode"], 20, 185 ); + } #ifdef DEBUG @@ -907,23 +900,6 @@ int GMenu2X::main() { s->write( font, fps+" FPS", resX-1,1 ,SFontHAlignRight ); #endif - - -/* - if (!TTF_WasInit()) TTF_Init(); - TTF_Font *font = TTF_OpenFont("/usr/share/fonts/webcore-vista/CALIBRII.TTF", 12); - if (font != NULL) { - cout << "TTF init" << endl; - SDL_Surface *tmpSurface = TTF_RenderUTF8_Blended(font, "Hello world", (SDL_Color){0,0,0,255}); - SDL_BlitSurface(tmpSurface, NULL, s->raw, NULL); - SDL_FreeSurface(tmpSurface); - TTF_CloseFont(font); - sleep(10); - } -*/ - - - s->flip(); //touchscreen @@ -988,16 +964,11 @@ int GMenu2X::main() { if ( input.isActive(ACTION_VOLUP) && input.isActive(ACTION_VOLDOWN) ) menu->selLinkApp()->setVolume(-1); } else { // CLOCK -#if defined(TARGET_WIZ) - int inc = 10; -#else - int inc = 1; -#endif if ( input[ACTION_VOLDOWN] && !input.isActive(ACTION_VOLUP) ) - menu->selLinkApp()->setClock( constrain(menu->selLinkApp()->clock()-inc,50,confInt["maxClock"]) ); + menu->selLinkApp()->setClock( constrain(menu->selLinkApp()->clock()-1,200,confInt["maxClock"]) ); if ( input[ACTION_VOLUP] && !input.isActive(ACTION_VOLDOWN) ) - menu->selLinkApp()->setClock( constrain(menu->selLinkApp()->clock()+inc,50,confInt["maxClock"]) ); - if ( input.isActive(ACTION_VOLUP) && input.isActive(ACTION_VOLDOWN) ) menu->selLinkApp()->setClock(200); + menu->selLinkApp()->setClock( constrain(menu->selLinkApp()->clock()+1,200,confInt["maxClock"]) ); + if ( input.isActive(ACTION_VOLUP) && input.isActive(ACTION_VOLDOWN) ) menu->selLinkApp()->setClock(336); } } if ( input.isActive(ACTION_A) ) { @@ -1021,7 +992,7 @@ int GMenu2X::main() { } void GMenu2X::explorer() { - FileDialog fd(this,tr["Select an application"],".gpu,.gpe,.sh"); + FileDialog fd(this,tr["Select an application"],".gpu,.dge,.sh"); if (fd.exec()) { if (confInt["saveSelection"] && (confInt["section"]!=menu->selSectionIndex() || confInt["link"]!=menu->selLinkIndex())) writeConfig(); @@ -1047,8 +1018,8 @@ void GMenu2X::options() { int curMenuClock = confInt["menuClock"]; int curGlobalVolume = confInt["globalVolume"]; //G - int prevgamma = confInt["gamma"]; - bool showRootFolder = fileExists("/mnt/root"); + int prevbacklight = confInt["backlight"]; + bool showRootFolder = fileExists("/boot/local"); FileLister fl_tr("translations"); fl_tr.browse(); @@ -1062,32 +1033,26 @@ void GMenu2X::options() { SettingsDialog sd(this,tr["Settings"]); sd.addSetting(new MenuSettingMultiString(this,tr["Language"],tr["Set the language used by GMenu2X"],&lang,&fl_tr.files)); sd.addSetting(new MenuSettingBool(this,tr["Save last selection"],tr["Save the last selected link and section on exit"],&confInt["saveSelection"])); -#ifdef TARGET_GP2X - sd.addSetting(new MenuSettingInt(this,tr["Clock for GMenu2X"],tr["Set the cpu working frequency when running GMenu2X"],&confInt["menuClock"],50,325)); - sd.addSetting(new MenuSettingInt(this,tr["Maximum overclock"],tr["Set the maximum overclock for launching links"],&confInt["maxClock"],50,325)); -#endif -#ifdef TARGET_WIZ - sd.addSetting(new MenuSettingInt(this,tr["Clock for GMenu2X"],tr["Set the cpu working frequency when running GMenu2X"],&confInt["menuClock"],50,900,10)); - sd.addSetting(new MenuSettingInt(this,tr["Maximum overclock"],tr["Set the maximum overclock for launching links"],&confInt["maxClock"],50,900,10)); -#endif + sd.addSetting(new MenuSettingInt(this,tr["Clock for GMenu2X"],tr["Set the cpu working frequency when running GMenu2X"],&confInt["menuClock"],200,430)); + sd.addSetting(new MenuSettingInt(this,tr["Maximum overclock"],tr["Set the maximum overclock for launching links"],&confInt["maxClock"],200,430)); sd.addSetting(new MenuSettingInt(this,tr["Global Volume"],tr["Set the default volume for the gp2x soundcard"],&confInt["globalVolume"],0,100)); sd.addSetting(new MenuSettingBool(this,tr["Output logs"],tr["Logs the output of the links. Use the Log Viewer to read them."],&confInt["outputLogs"])); //G - sd.addSetting(new MenuSettingInt(this,tr["Gamma"],tr["Set gp2x gamma value (default: 10)"],&confInt["gamma"],1,100)); - sd.addSetting(new MenuSettingMultiString(this,tr["Tv-Out encoding"],tr["Encoding of the tv-out signal"],&confStr["tvoutEncoding"],&encodings)); + sd.addSetting(new MenuSettingInt(this,tr["Lcd Backlight"],tr["Set dingoo's Lcd Backlight value (default: 100)"],&confInt["backlight"],5,100)); +// sd.addSetting(new MenuSettingMultiString(this,tr["Tv-Out encoding"],tr["Encoding of the tv-out signal"],&confStr["tvoutEncoding"],&encodings)); sd.addSetting(new MenuSettingBool(this,tr["Show root"],tr["Show root folder in the file selection dialogs"],&showRootFolder)); if (sd.exec() && sd.edited()) { //G - if (prevgamma != confInt["gamma"]) setGamma(confInt["gamma"]); + if (prevbacklight != confInt["backlight"]) setBacklight(confInt["backlight"]); if (curMenuClock!=confInt["menuClock"]) setClock(confInt["menuClock"]); if (curGlobalVolume!=confInt["globalVolume"]) setVolume(confInt["globalVolume"]); if (lang == "English") lang = ""; if (lang != tr.lang()) tr.setLang(lang); - if (fileExists("/mnt/root") && !showRootFolder) - unlink("/mnt/root"); - else if (!fileExists("/mnt/root") && showRootFolder) - symlink("/","/mnt/root"); + if (fileExists("/boot/local") && !showRootFolder) + unlink("/boot/local"); + else if (!fileExists("/boot/local") && showRootFolder) + symlink("/","/boot/local"); writeConfig(); } } @@ -1102,7 +1067,7 @@ void GMenu2X::settingsOpen2x() { sd.addSetting(new MenuSettingBool(this,tr["USB host on boot"],tr["Allow USB host to be started at boot time"],&o2x_usb_host_on_boot)); sd.addSetting(new MenuSettingBool(this,tr["USB HID on boot"],tr["Allow USB HID to be started at boot time"],&o2x_usb_hid_on_boot)); sd.addSetting(new MenuSettingBool(this,tr["USB storage on boot"],tr["Allow USB storage to be started at boot time"],&o2x_usb_storage_on_boot)); - //sd.addSetting(new MenuSettingInt(this,tr["Speaker Mode on boot"],tr["Set Speaker mode. 0 = Mute, 1 = Phones, 2 = Speaker"],&volumeMode,0,2,1)); + //sd.addSetting(new MenuSettingInt(this,tr["Speaker Mode on boot"],tr["Set Speaker mode. 0 = Mute, 1 = Phones, 2 = Speaker"],&volumeMode,0,2)); sd.addSetting(new MenuSettingInt(this,tr["Speaker Scaler"],tr["Set the Speaker Mode scaling 0-150\% (default is 100\%)"],&volumeScalerNormal,0,150)); sd.addSetting(new MenuSettingInt(this,tr["Headphones Scaler"],tr["Set the Headphones Mode scaling 0-100\% (default is 65\%)"],&volumeScalerPhones,0,100)); @@ -1131,8 +1096,6 @@ void GMenu2X::skinMenu() { sd.addSetting(new MenuSettingRGBA(this,tr["Message Box Color"],tr["Background color of the message box"],&skinConfColors["messageBoxBg"])); sd.addSetting(new MenuSettingRGBA(this,tr["Message Box Border Color"],tr["Border color of the message box"],&skinConfColors["messageBoxBorder"])); sd.addSetting(new MenuSettingRGBA(this,tr["Message Box Selection Color"],tr["Color of the selection of the message box"],&skinConfColors["messageBoxSelection"])); - sd.addSetting(new MenuSettingRGBA(this,tr["Font Color"],tr["Color of the font"],&skinConfColors["fontColor"])); - sd.addSetting(new MenuSettingRGBA(this,tr["Font Outline Color"],tr["Color of the font's outline"],&skinConfColors["fontOutlineColor"])); if (sd.exec() && sd.edited()) { if (curSkin != confStr["skin"]) { @@ -1146,10 +1109,10 @@ void GMenu2X::skinMenu() { void GMenu2X::toggleTvOut() { #ifdef TARGET_GP2X - if (cx25874!=0) +/* if (cx25874!=0) gp2x_tvout_off(); else - gp2x_tvout_on(confStr["tvoutEncoding"] == "PAL"); + gp2x_tvout_on(confStr["tvoutEncoding"] == "PAL");*/ #endif } @@ -1172,8 +1135,6 @@ void GMenu2X::setSkin(string skin, bool setWallpaper) { skinConfColors["messageBoxBg"] = (RGBAColor){255,255,255,255}; skinConfColors["messageBoxBorder"] = (RGBAColor){80,80,80,255}; skinConfColors["messageBoxSelection"] = (RGBAColor){160,160,160,255}; - skinConfColors["fontColor"] = (RGBAColor){255,255,255,255}; - skinConfColors["fontOutlineColor"] = (RGBAColor){0,0,0,130}; //load skin settings string skinconfname = "skins/"+skin+"/skin.conf"; @@ -1429,6 +1390,7 @@ void GMenu2X::editLink() { int linkVolume = menu->selLinkApp()->volume(); //G int linkGamma = menu->selLinkApp()->gamma(); + int linkBacklight = menu->selLinkApp()->backlight(); string diagTitle = tr.translate("Edit link: $1",linkTitle.c_str(),NULL); string diagIcon = menu->selLinkApp()->getIconPath(); @@ -1439,14 +1401,10 @@ void GMenu2X::editLink() { sd.addSetting(new MenuSettingMultiString(this,tr["Section"],tr["The section this link belongs to"],&newSection,&menu->sections)); sd.addSetting(new MenuSettingImage(this,tr["Icon"],tr.translate("Select an icon for the link: $1",linkTitle.c_str(),NULL),&linkIcon,".png,.bmp,.jpg,.jpeg")); sd.addSetting(new MenuSettingFile(this,tr["Manual"],tr["Select a graphic/textual manual or a readme"],&linkManual,".man.png,.txt")); -#ifdef TARGET_GP2X - sd.addSetting(new MenuSettingInt(this,tr["Clock (default: 200)"],tr["Cpu clock frequency to set when launching this link"],&linkClock,50,confInt["maxClock"])); -#endif -#ifdef TARGET_WIZ - sd.addSetting(new MenuSettingInt(this,tr["Clock (default: 550)"],tr["Cpu clock frequency to set when launching this link"],&linkClock,50,confInt["maxClock"],10)); -#endif - sd.addSetting(new MenuSettingBool(this,tr["Tweak RAM Timings"],tr["This usually speeds up the application at the cost of stability"],&linkUseRamTimings)); + sd.addSetting(new MenuSettingInt(this,tr["Clock (default: 336)"],tr["Cpu clock frequency to set when launching this link"],&linkClock,200,confInt["maxClock"])); +// sd.addSetting(new MenuSettingBool(this,tr["Tweak RAM Timings"],tr["This usually speeds up the application at the cost of stability"],&linkUseRamTimings)); sd.addSetting(new MenuSettingInt(this,tr["Volume (default: -1)"],tr["Volume to set for this link"],&linkVolume,-1,100)); + sd.addSetting(new MenuSettingInt(this,tr["Backlight (default: 100)"],tr["LCD backlight value to set when launching this link"],&linkBacklight,5,100)); sd.addSetting(new MenuSettingString(this,tr["Parameters"],tr["Parameters to pass to the application"],&linkParams, diagTitle,diagIcon)); sd.addSetting(new MenuSettingDir(this,tr["Selector Directory"],tr["Directory to scan for the selector"],&linkSelDir)); sd.addSetting(new MenuSettingBool(this,tr["Selector Browser"],tr["Allow the selector to change directory"],&linkSelBrowser)); @@ -1454,7 +1412,6 @@ void GMenu2X::editLink() { sd.addSetting(new MenuSettingDir(this,tr["Selector Screenshots"],tr["Directory of the screenshots for the selector"],&linkSelScreens)); sd.addSetting(new MenuSettingFile(this,tr["Selector Aliases"],tr["File containing a list of aliases for the selector"],&linkSelAliases)); //G - sd.addSetting(new MenuSettingInt(this,tr["Gamma (default: 0)"],tr["Gamma value to set when launching this link"],&linkGamma,0,100)); sd.addSetting(new MenuSettingBool(this,tr["Wrapper"],tr["Explicitly relaunch GMenu2X after this link's execution ends"],&menu->selLinkApp()->wrapper)); sd.addSetting(new MenuSettingBool(this,tr["Don't Leave"],tr["Don't quit GMenu2X when launching this link"],&menu->selLinkApp()->dontleave)); @@ -1475,7 +1432,7 @@ void GMenu2X::editLink() { menu->selLinkApp()->setClock(linkClock); menu->selLinkApp()->setVolume(linkVolume); //G - menu->selLinkApp()->setGamma(linkGamma); + menu->selLinkApp()->setBacklight(linkBacklight); #ifdef DEBUG cout << "New Section: " << newSection << endl; @@ -1591,9 +1548,9 @@ void GMenu2X::scanner() { #ifdef _TARGET_PANDORA //char *configpath = pnd_conf_query_searchpath(); #else - if (confInt["menuClock"]<200) { - setClock(200); - scanbg.write(font,tr["Raising cpu clock to 200Mhz"],5,lineY); + if (confInt["menuClock"]<430) { + setClock(336); + scanbg.write(font,tr["Raising cpu clock to 336Mhz"],5,lineY); scanbg.blit(s,0,0); s->flip(); lineY += 26; @@ -1605,17 +1562,17 @@ void GMenu2X::scanner() { lineY += 26; vector files; - scanPath("/mnt/sd",&files); + scanPath("/boot/local/",&files); //Onyl gph firmware has nand - if (fwType=="gph" && !f200) { +/* if (fwType=="gph" && !f200) { scanbg.write(font,tr["Scanning NAND filesystem..."],5,lineY); scanbg.blit(s,0,0); s->flip(); lineY += 26; - scanPath("/mnt/nand",&files); + scanPath("/boot/local/nand",&files); } - +*/ stringstream ss; ss << files.size(); string str = ""; @@ -1650,7 +1607,7 @@ void GMenu2X::scanner() { s->flip(); lineY += 26; - if (confInt["menuClock"]<200) { + if (confInt["menuClock"]<430) { setClock(confInt["menuClock"]); scanbg.write(font,tr["Decreasing cpu clock"],5,lineY); scanbg.blit(s,0,0); @@ -1688,8 +1645,8 @@ void GMenu2X::scanPath(string path, vector *files) { scanPath(filepath, files); if (statRet != -1) { ext = filepath.substr(filepath.length()-4,4); -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) - if (ext==".gpu" || ext==".gpe") +#ifdef TARGET_GP2X + if (ext==".gpu" || ext==".dge") #else if (ext==".pxml") #endif @@ -1701,8 +1658,8 @@ void GMenu2X::scanPath(string path, vector *files) { } unsigned short GMenu2X::getBatteryLevel() { -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) - if (batteryHandle<=0) return 0; +#ifdef TARGET_GP2X +/* if (batteryHandle<=0) return 0; if (f200) { MMSP2ADC val; @@ -1733,7 +1690,18 @@ unsigned short GMenu2X::getBatteryLevel() { if (battval>700) return 3; if (battval>690) return 2; if (battval>680) return 1; - } + }*/ + if (!batteryHandle) return 0; + int battval = 0; + char battvalcstr[5]; + fscanf(batteryHandle,"%s",&battvalcstr); + rewind(batteryHandle); + battval = atoi(battvalcstr); + if (battval>4000) return 5; + if (battval>3800) return 4; + if (battval>3600) return 3; + if (battval>3400) return 2; + if (battval>3200) return 1; return 0; #else return 6; //AC Power @@ -1759,29 +1727,31 @@ void GMenu2X::setInputSpeed() { void GMenu2X::applyRamTimings() { #ifdef TARGET_GP2X // 6 4 1 1 1 2 2 - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { int tRC = 5, tRAS = 3, tWR = 0, tMRD = 0, tRFC = 0, tRP = 1, tRCD = 1; gp2x_memregs[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF); gp2x_memregs[0x3804>>1] = ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF); - } + }*/ #endif } void GMenu2X::applyDefaultTimings() { #ifdef TARGET_GP2X // 8 16 3 8 8 8 8 - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { int tRC = 7, tRAS = 15, tWR = 2, tMRD = 7, tRFC = 7, tRP = 7, tRCD = 7; gp2x_memregs[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF); gp2x_memregs[0x3804>>1] = ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF); - } + }*/ #endif } + + void GMenu2X::setClock(unsigned mhz) { - mhz = constrain(mhz,50,confInt["maxClock"]); + mhz = constrain(mhz,200,confInt["maxClock"]); #ifdef TARGET_GP2X - if (gp2x_mem!=0) { +/* if (gp2x_mem!=0) { unsigned v; unsigned mdiv,pdiv=3,scale=0; mhz*=1000000; @@ -1791,26 +1761,14 @@ void GMenu2X::setClock(unsigned mhz) { scale&=3; v=mdiv | pdiv | scale; MEM_REG[0x910>>1]=v; - } -#endif -#ifdef TARGET_WIZ - unsigned long v; - unsigned mdiv, pdiv=9, sdiv=0; - if (wiz_mem!=0) { - printf( "Setting clockspeed to %d\n", mhz ); - mdiv= (mhz * pdiv) / SYS_CLK_FREQ; - mdiv &= 0x3FF; - v= pdiv<<18 | mdiv<<8 | sdiv; - - PLLSETREG0 = v; - PWRMODE |= 0x8000; - } + }*/ + jz_cpuspeed(mhz); #endif } void GMenu2X::setGamma(int gamma) { #ifdef TARGET_GP2X - float fgamma = (float)constrain(gamma,1,100)/10; +/* float fgamma = (float)constrain(gamma,1,100)/10; fgamma = 1 / fgamma; MEM_REG[0x2880>>1]&=~(1<<12); MEM_REG[0x295C>>1]=0; @@ -1820,32 +1778,39 @@ void GMenu2X::setGamma(int gamma) { unsigned short s = (g<<8) | g; MEM_REG[0x295E>>1]= s; MEM_REG[0x295E>>1]= g; - } + }*/ #endif } int GMenu2X::getVolume() { - int vol = -1; - unsigned long soundDev = open("/dev/mixer", O_RDONLY); - if (soundDev) { - ioctl(soundDev, SOUND_MIXER_READ_PCM, &vol); - close(soundDev); - if (vol != -1) { - //just return one channel , not both channels, they're hopefully the same anyways - return vol & 0xFF; + unsigned long mixer; + int basevolume = -1; + mixer = open("/dev/mixer", O_RDONLY); + if(mixer) + { + if (ioctl(mixer, SOUND_MIXER_READ_VOLUME, &basevolume) == -1) { + fprintf(stderr, "Failed opening mixer for read - VOLUME\n"); } + close(mixer); + if(basevolume != -1) + return (basevolume>>8) & basevolume ; } - return vol; + return basevolume; } void GMenu2X::setVolume(int vol) { - vol = constrain(vol,0,100); - unsigned long soundDev = open("/dev/mixer", O_RDWR); - if (soundDev) { - vol = (vol << 8) | vol; - ioctl(soundDev, SOUND_MIXER_WRITE_PCM, &vol); - close(soundDev); + unsigned long mixer; + int newvolume = vol; + int oss_volume = newvolume | (newvolume << 8); // set volume for both channels + mixer = open("/dev/mixer", O_WRONLY); + if(mixer) + { + if (ioctl(mixer, SOUND_MIXER_WRITE_VOLUME, &oss_volume) == -1) { + fprintf(stderr, "Failed opening mixer for write - VOLUME\n"); + } + close(mixer); } + } void GMenu2X::setVolumeScaler(int scale) { @@ -1885,7 +1850,7 @@ string GMenu2X::getDiskFree() { string df = ""; struct statvfs b; - int ret = statvfs("/mnt/sd", &b); + int ret = statvfs("/boot/local/gmenu2x", &b); if (ret==0) { /*unsigned long free = b.f_bfree*b.f_frsize/1048576; unsigned long total = b.f_blocks*b.f_frsize/1048576; diff --git a/src/gmenu2x.h b/src/gmenu2x.h index 72e3550..83c8fee 100644 --- a/src/gmenu2x.h +++ b/src/gmenu2x.h @@ -45,6 +45,8 @@ const int BATTERY_READS = 10; const int LOOP_DELAY=30000; +extern void jz_cpuspeed(unsigned clockspeed); + using std::string; using fastdelegate::FastDelegate0; using google::dense_hash_map; @@ -82,10 +84,10 @@ class GMenu2X { @return A number representing battery charge. 0 means fully discharged. 5 means fully charged. 6 represents a gp2x using AC power. */ unsigned short getBatteryLevel(); - int batteryHandle; + FILE* batteryHandle, *backlightHandle; void browsePath(string path, vector* directories, vector* files); /*! - Starts the scanning of the nand and sd filesystems, searching for gpe and gpu files and creating the links in 2 dedicated sections. + Starts the scanning of the nand and sd filesystems, searching for dge and gpu files and creating the links in 2 dedicated sections. */ void scanner(); /*! @@ -120,13 +122,6 @@ class GMenu2X { unsigned short *gp2x_memregs; volatile unsigned short *MEM_REG; int cx25874; //tv-out -#endif -#ifdef TARGET_WIZ - #define PLLSETREG0 (wiz_memregs[0xF004>>2]) - #define PWRMODE (wiz_memregs[0xF07C>>2]) - #define SYS_CLK_FREQ 27 - int wiz_mem; - volatile uint32_t *wiz_memregs; #endif void gp2x_tvout_on(bool pal); void gp2x_tvout_off(); @@ -182,7 +177,7 @@ class GMenu2X { SurfaceCollection sc; Translator tr; Surface *s, *bg; - SFontPlus *font; + ASFont *font; //Status functions int main(); @@ -209,6 +204,9 @@ class GMenu2X { void setVolumeScaler(int scaler); int getVolumeScaler(); + void setBacklight(int val); + int getBackLight(); + void setInputSpeed(); void writeConfig(); diff --git a/src/imagedialog.cpp b/src/imagedialog.cpp index cfe73de..22ce577 100644 --- a/src/imagedialog.cpp +++ b/src/imagedialog.cpp @@ -36,7 +36,7 @@ ImageDialog::ImageDialog(GMenu2X *gmenu2x, string text, string filter, string fi this->text = text; this->filter = filter; this->file = ""; - setPath("/mnt"); + setPath("/boot/local"); title = "Image Browser"; if (!file.empty()) { file = strreplace(file,"skin:",gmenu2x->getExePath()+"skins/"+gmenu2x->confStr["skin"]+"/"); diff --git a/src/jz4740.h b/src/jz4740.h new file mode 100644 index 0000000..1ca84d3 --- /dev/null +++ b/src/jz4740.h @@ -0,0 +1,5212 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2008 by Maurus Cuelenaere + * Copyright (C) 2006-2007 by Ingenic Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/* + * linux/include/asm-mips/mach-jz4740/jz4740.h + * + * JZ4740 common definition. + * + * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. + * + * Author: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Include file for Ingenic Semiconductor's JZ4740 CPU. + */ +#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#ifndef __ASSEMBLY__ + +#define REG8(addr) (*(volatile unsigned char *)(addr)) +#define REG16(addr) (*(volatile unsigned short *)(addr)) +#define REG32(addr) (*(volatile unsigned int *)(addr)) + +#endif /* !ASSEMBLY */ + +/************************************************************************* + * Boot ROM Specification + */ + +/* NOR Boot config */ +#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ + +/* NAND Boot config */ +#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ + + +/************************************************************************* + * Register Definitions + */ +#define CPM_BASE 0xB0000000 +#define INTC_BASE 0xB0001000 +#define TCU_BASE 0xB0002000 +#define WDT_BASE 0xB0002000 +#define RTC_BASE 0xB0003000 +#define GPIO_BASE 0xB0010000 +#define AIC_BASE 0xB0020000 +#define ICDC_BASE 0xB0020000 +#define MSC_BASE 0xB0021000 +#define UART0_BASE 0xB0030000 +#define I2C_BASE 0xB0042000 +#define SSI_BASE 0xB0043000 +#define SADC_BASE 0xB0070000 +#define EMC_BASE 0xB3010000 +#define DMAC_BASE 0xB3020000 +#define UHC_BASE 0xB3030000 +#define UDC_BASE 0xB3040000 +#define LCD_BASE 0xB3050000 +#define SLCD_BASE 0xB3050000 +#define CIM_BASE 0xB3060000 +#define ETH_BASE 0xB3100000 + + +/************************************************************************* + * INTC (Interrupt Controller) + *************************************************************************/ +#define INTC_ISR (INTC_BASE + 0x00) +#define INTC_IMR (INTC_BASE + 0x04) +#define INTC_IMSR (INTC_BASE + 0x08) +#define INTC_IMCR (INTC_BASE + 0x0c) +#define INTC_IPR (INTC_BASE + 0x10) + +#define REG_INTC_ISR REG32(INTC_ISR) +#define REG_INTC_IMR REG32(INTC_IMR) +#define REG_INTC_IMSR REG32(INTC_IMSR) +#define REG_INTC_IMCR REG32(INTC_IMCR) +#define REG_INTC_IPR REG32(INTC_IPR) + +// 1st-level interrupts +#define IRQ_I2C 1 +#define IRQ_EMC 2 +#define IRQ_UHC 3 +#define IRQ_UART0 9 +#define IRQ_SADC 12 +#define IRQ_MSC 14 +#define IRQ_RTC 15 +#define IRQ_SSI 16 +#define IRQ_CIM 17 +#define IRQ_AIC 18 +#define IRQ_ETH 19 +#define IRQ_DMAC 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_UDC 24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_IPU 29 +#define IRQ_LCD 30 + +// 2nd-level interrupts +#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ +#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ + + +/************************************************************************* + * RTC + *************************************************************************/ +#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ +#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ +#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ +#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ + +#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ +#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ +#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ +#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ +#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ +#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ + +#define REG_RTC_RCR REG32(RTC_RCR) +#define REG_RTC_RSR REG32(RTC_RSR) +#define REG_RTC_RSAR REG32(RTC_RSAR) +#define REG_RTC_RGR REG32(RTC_RGR) +#define REG_RTC_HCR REG32(RTC_HCR) +#define REG_RTC_HWFCR REG32(RTC_HWFCR) +#define REG_RTC_HRCR REG32(RTC_HRCR) +#define REG_RTC_HWCR REG32(RTC_HWCR) +#define REG_RTC_HWRSR REG32(RTC_HWRSR) +#define REG_RTC_HSPR REG32(RTC_HSPR) + +/* RTC Control Register */ +#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ +#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ +#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ +#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ +#define RTC_RCR_AF_BIT 4 /* Alarm Flag */ +#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ +#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ +#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ + +/* RTC Regulator Register */ +#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ +#define RTC_RGR_ADJC_BIT 16 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) +#define RTC_RGR_NC1HZ_BIT 0 +#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) + +/* Hibernate Control Register */ +#define RTC_HCR_PD (1 << 0) /* Power Down */ + +/* Hibernate Wakeup Filter Counter Register */ +#define RTC_HWFCR_BIT 5 +#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) + +/* Hibernate Reset Counter Register */ +#define RTC_HRCR_BIT 5 +#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) + +/* Hibernate Wakeup Control Register */ +#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ + +/* Hibernate Wakeup Status Register */ +#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ +#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ +#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ +#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ + + +/************************************************************************* + * CPM (Clock reset and Power control Management) + *************************************************************************/ +#define CPM_CPCCR (CPM_BASE+0x00) +#define CPM_CPPCR (CPM_BASE+0x10) +#define CPM_I2SCDR (CPM_BASE+0x60) +#define CPM_LPCDR (CPM_BASE+0x64) +#define CPM_MSCCDR (CPM_BASE+0x68) +#define CPM_UHCCDR (CPM_BASE+0x6C) + +#define CPM_LCR (CPM_BASE+0x04) +#define CPM_CLKGR (CPM_BASE+0x20) +#define CPM_SCR (CPM_BASE+0x24) + +#define CPM_HCR (CPM_BASE+0x30) +#define CPM_HWFCR (CPM_BASE+0x34) +#define CPM_HRCR (CPM_BASE+0x38) +#define CPM_HWCR (CPM_BASE+0x3c) +#define CPM_HWSR (CPM_BASE+0x40) +#define CPM_HSPR (CPM_BASE+0x44) + +#define CPM_RSR (CPM_BASE+0x08) + + +#define REG_CPM_CPCCR REG32(CPM_CPCCR) +#define REG_CPM_CPPCR REG32(CPM_CPPCR) +#define REG_CPM_I2SCDR REG32(CPM_I2SCDR) +#define REG_CPM_LPCDR REG32(CPM_LPCDR) +#define REG_CPM_MSCCDR REG32(CPM_MSCCDR) +#define REG_CPM_UHCCDR REG32(CPM_UHCCDR) + +#define REG_CPM_LCR REG32(CPM_LCR) +#define REG_CPM_CLKGR REG32(CPM_CLKGR) +#define REG_CPM_SCR REG32(CPM_SCR) +#define REG_CPM_HCR REG32(CPM_HCR) +#define REG_CPM_HWFCR REG32(CPM_HWFCR) +#define REG_CPM_HRCR REG32(CPM_HRCR) +#define REG_CPM_HWCR REG32(CPM_HWCR) +#define REG_CPM_HWSR REG32(CPM_HWSR) +#define REG_CPM_HSPR REG32(CPM_HSPR) + +#define REG_CPM_RSR REG32(CPM_RSR) + + +/* Clock Control Register */ +#define CPM_CPCCR_I2CS (1 << 31) +#define CPM_CPCCR_CLKOEN (1 << 30) +#define CPM_CPCCR_UCS (1 << 29) +#define CPM_CPCCR_UDIV_BIT 23 +#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) +#define CPM_CPCCR_CE (1 << 22) +#define CPM_CPCCR_PCS (1 << 21) +#define CPM_CPCCR_LDIV_BIT 16 +#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) +#define CPM_CPCCR_MDIV_BIT 12 +#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) +#define CPM_CPCCR_PDIV_BIT 8 +#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) +#define CPM_CPCCR_HDIV_BIT 4 +#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) +#define CPM_CPCCR_CDIV_BIT 0 +#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) + +/* I2S Clock Divider Register */ +#define CPM_I2SCDR_I2SDIV_BIT 0 +#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) + +/* LCD Pixel Clock Divider Register */ +#define CPM_LPCDR_PIXDIV_BIT 0 +#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) + +/* MSC Clock Divider Register */ +#define CPM_MSCCDR_MSCDIV_BIT 0 +#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) + +/* PLL Control Register */ +#define CPM_CPPCR_PLLM_BIT 23 +#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) +#define CPM_CPPCR_PLLN_BIT 18 +#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) +#define CPM_CPPCR_PLLOD_BIT 16 +#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) +#define CPM_CPPCR_PLLS (1 << 10) +#define CPM_CPPCR_PLLBP (1 << 9) +#define CPM_CPPCR_PLLEN (1 << 8) +#define CPM_CPPCR_PLLST_BIT 0 +#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) + +/* Low Power Control Register */ +#define CPM_LCR_DOZE_DUTY_BIT 3 +#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) +#define CPM_LCR_DOZE_ON (1 << 2) +#define CPM_LCR_LPM_BIT 0 +#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) + #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) + #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) + +/* Clock Gate Register */ +#define CPM_CLKGR_UART1 (1 << 15) +#define CPM_CLKGR_UHC (1 << 14) +#define CPM_CLKGR_IPU (1 << 13) +#define CPM_CLKGR_DMAC (1 << 12) +#define CPM_CLKGR_UDC (1 << 11) +#define CPM_CLKGR_LCD (1 << 10) +#define CPM_CLKGR_CIM (1 << 9) +#define CPM_CLKGR_SADC (1 << 8) +#define CPM_CLKGR_MSC (1 << 7) +#define CPM_CLKGR_AIC1 (1 << 6) +#define CPM_CLKGR_AIC2 (1 << 5) +#define CPM_CLKGR_SSI (1 << 4) +#define CPM_CLKGR_I2C (1 << 3) +#define CPM_CLKGR_RTC (1 << 2) +#define CPM_CLKGR_TCU (1 << 1) +#define CPM_CLKGR_UART0 (1 << 0) + +/* Sleep Control Register */ +#define CPM_SCR_O1ST_BIT 8 +#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) +#define CPM_SCR_USBHOST_SUSPEND (1 << 7) +#define CPM_SCR_USBPHY_ENABLE (1 << 6) +#define CPM_SCR_OSC_ENABLE (1 << 4) + +/* Hibernate Control Register */ +#define CPM_HCR_PD (1 << 0) + +/* Wakeup Filter Counter Register in Hibernate Mode */ +#define CPM_HWFCR_TIME_BIT 0 +#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) + +/* Reset Counter Register in Hibernate Mode */ +#define CPM_HRCR_TIME_BIT 0 +#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) + +/* Wakeup Control Register in Hibernate Mode */ +#define CPM_HWCR_WLE_LOW (0 << 2) +#define CPM_HWCR_WLE_HIGH (1 << 2) +#define CPM_HWCR_PIN_WAKEUP (1 << 1) +#define CPM_HWCR_RTC_WAKEUP (1 << 0) + +/* Wakeup Status Register in Hibernate Mode */ +#define CPM_HWSR_WSR_PIN (1 << 1) +#define CPM_HWSR_WSR_RTC (1 << 0) + +/* Reset Status Register */ +#define CPM_RSR_HR (1 << 2) +#define CPM_RSR_WR (1 << 1) +#define CPM_RSR_PR (1 << 0) + + +/************************************************************************* + * TCU (Timer Counter Unit) + *************************************************************************/ +#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ +#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ +#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ +#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ +#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ +#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ +#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ +#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ +#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ +#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ +#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ +#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ +#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ +#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ +#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ +#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ +#define TCU_TDFR1 (TCU_BASE + 0x50) +#define TCU_TDHR1 (TCU_BASE + 0x54) +#define TCU_TCNT1 (TCU_BASE + 0x58) +#define TCU_TCSR1 (TCU_BASE + 0x5C) +#define TCU_TDFR2 (TCU_BASE + 0x60) +#define TCU_TDHR2 (TCU_BASE + 0x64) +#define TCU_TCNT2 (TCU_BASE + 0x68) +#define TCU_TCSR2 (TCU_BASE + 0x6C) +#define TCU_TDFR3 (TCU_BASE + 0x70) +#define TCU_TDHR3 (TCU_BASE + 0x74) +#define TCU_TCNT3 (TCU_BASE + 0x78) +#define TCU_TCSR3 (TCU_BASE + 0x7C) +#define TCU_TDFR4 (TCU_BASE + 0x80) +#define TCU_TDHR4 (TCU_BASE + 0x84) +#define TCU_TCNT4 (TCU_BASE + 0x88) +#define TCU_TCSR4 (TCU_BASE + 0x8C) +#define TCU_TDFR5 (TCU_BASE + 0x90) +#define TCU_TDHR5 (TCU_BASE + 0x94) +#define TCU_TCNT5 (TCU_BASE + 0x98) +#define TCU_TCSR5 (TCU_BASE + 0x9C) + +#define REG_TCU_TSR REG32(TCU_TSR) +#define REG_TCU_TSSR REG32(TCU_TSSR) +#define REG_TCU_TSCR REG32(TCU_TSCR) +#define REG_TCU_TER REG8(TCU_TER) +#define REG_TCU_TESR REG8(TCU_TESR) +#define REG_TCU_TECR REG8(TCU_TECR) +#define REG_TCU_TFR REG32(TCU_TFR) +#define REG_TCU_TFSR REG32(TCU_TFSR) +#define REG_TCU_TFCR REG32(TCU_TFCR) +#define REG_TCU_TMR REG32(TCU_TMR) +#define REG_TCU_TMSR REG32(TCU_TMSR) +#define REG_TCU_TMCR REG32(TCU_TMCR) +#define REG_TCU_TDFR0 REG16(TCU_TDFR0) +#define REG_TCU_TDHR0 REG16(TCU_TDHR0) +#define REG_TCU_TCNT0 REG16(TCU_TCNT0) +#define REG_TCU_TCSR0 REG16(TCU_TCSR0) +#define REG_TCU_TDFR1 REG16(TCU_TDFR1) +#define REG_TCU_TDHR1 REG16(TCU_TDHR1) +#define REG_TCU_TCNT1 REG16(TCU_TCNT1) +#define REG_TCU_TCSR1 REG16(TCU_TCSR1) +#define REG_TCU_TDFR2 REG16(TCU_TDFR2) +#define REG_TCU_TDHR2 REG16(TCU_TDHR2) +#define REG_TCU_TCNT2 REG16(TCU_TCNT2) +#define REG_TCU_TCSR2 REG16(TCU_TCSR2) +#define REG_TCU_TDFR3 REG16(TCU_TDFR3) +#define REG_TCU_TDHR3 REG16(TCU_TDHR3) +#define REG_TCU_TCNT3 REG16(TCU_TCNT3) +#define REG_TCU_TCSR3 REG16(TCU_TCSR3) +#define REG_TCU_TDFR4 REG16(TCU_TDFR4) +#define REG_TCU_TDHR4 REG16(TCU_TDHR4) +#define REG_TCU_TCNT4 REG16(TCU_TCNT4) +#define REG_TCU_TCSR4 REG16(TCU_TCSR4) + +// n = 0,1,2,3,4,5,6,7 +#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ +#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ +#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ +#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ + +#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) +#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) +#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) +#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) + +// Register definitions +#define TCU_TCSR_PWM_SD (1 << 9) +#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) +#define TCU_TCSR_PWM_EN (1 << 7) +#define TCU_TCSR_PRESCALE_BIT 3 +#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) + #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) + #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) + #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) + #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) + #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) + #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_EXT_EN (1 << 2) +#define TCU_TCSR_RTC_EN (1 << 1) +#define TCU_TCSR_PCK_EN (1 << 0) + +#define TCU_TER_TCEN5 (1 << 5) +#define TCU_TER_TCEN4 (1 << 4) +#define TCU_TER_TCEN3 (1 << 3) +#define TCU_TER_TCEN2 (1 << 2) +#define TCU_TER_TCEN1 (1 << 1) +#define TCU_TER_TCEN0 (1 << 0) + +#define TCU_TESR_TCST5 (1 << 5) +#define TCU_TESR_TCST4 (1 << 4) +#define TCU_TESR_TCST3 (1 << 3) +#define TCU_TESR_TCST2 (1 << 2) +#define TCU_TESR_TCST1 (1 << 1) +#define TCU_TESR_TCST0 (1 << 0) + +#define TCU_TECR_TCCL5 (1 << 5) +#define TCU_TECR_TCCL4 (1 << 4) +#define TCU_TECR_TCCL3 (1 << 3) +#define TCU_TECR_TCCL2 (1 << 2) +#define TCU_TECR_TCCL1 (1 << 1) +#define TCU_TECR_TCCL0 (1 << 0) + +#define TCU_TFR_HFLAG5 (1 << 21) +#define TCU_TFR_HFLAG4 (1 << 20) +#define TCU_TFR_HFLAG3 (1 << 19) +#define TCU_TFR_HFLAG2 (1 << 18) +#define TCU_TFR_HFLAG1 (1 << 17) +#define TCU_TFR_HFLAG0 (1 << 16) +#define TCU_TFR_FFLAG5 (1 << 5) +#define TCU_TFR_FFLAG4 (1 << 4) +#define TCU_TFR_FFLAG3 (1 << 3) +#define TCU_TFR_FFLAG2 (1 << 2) +#define TCU_TFR_FFLAG1 (1 << 1) +#define TCU_TFR_FFLAG0 (1 << 0) + +#define TCU_TFSR_HFLAG5 (1 << 21) +#define TCU_TFSR_HFLAG4 (1 << 20) +#define TCU_TFSR_HFLAG3 (1 << 19) +#define TCU_TFSR_HFLAG2 (1 << 18) +#define TCU_TFSR_HFLAG1 (1 << 17) +#define TCU_TFSR_HFLAG0 (1 << 16) +#define TCU_TFSR_FFLAG5 (1 << 5) +#define TCU_TFSR_FFLAG4 (1 << 4) +#define TCU_TFSR_FFLAG3 (1 << 3) +#define TCU_TFSR_FFLAG2 (1 << 2) +#define TCU_TFSR_FFLAG1 (1 << 1) +#define TCU_TFSR_FFLAG0 (1 << 0) + +#define TCU_TFCR_HFLAG5 (1 << 21) +#define TCU_TFCR_HFLAG4 (1 << 20) +#define TCU_TFCR_HFLAG3 (1 << 19) +#define TCU_TFCR_HFLAG2 (1 << 18) +#define TCU_TFCR_HFLAG1 (1 << 17) +#define TCU_TFCR_HFLAG0 (1 << 16) +#define TCU_TFCR_FFLAG5 (1 << 5) +#define TCU_TFCR_FFLAG4 (1 << 4) +#define TCU_TFCR_FFLAG3 (1 << 3) +#define TCU_TFCR_FFLAG2 (1 << 2) +#define TCU_TFCR_FFLAG1 (1 << 1) +#define TCU_TFCR_FFLAG0 (1 << 0) + +#define TCU_TMR_HMASK5 (1 << 21) +#define TCU_TMR_HMASK4 (1 << 20) +#define TCU_TMR_HMASK3 (1 << 19) +#define TCU_TMR_HMASK2 (1 << 18) +#define TCU_TMR_HMASK1 (1 << 17) +#define TCU_TMR_HMASK0 (1 << 16) +#define TCU_TMR_FMASK5 (1 << 5) +#define TCU_TMR_FMASK4 (1 << 4) +#define TCU_TMR_FMASK3 (1 << 3) +#define TCU_TMR_FMASK2 (1 << 2) +#define TCU_TMR_FMASK1 (1 << 1) +#define TCU_TMR_FMASK0 (1 << 0) + +#define TCU_TMSR_HMST5 (1 << 21) +#define TCU_TMSR_HMST4 (1 << 20) +#define TCU_TMSR_HMST3 (1 << 19) +#define TCU_TMSR_HMST2 (1 << 18) +#define TCU_TMSR_HMST1 (1 << 17) +#define TCU_TMSR_HMST0 (1 << 16) +#define TCU_TMSR_FMST5 (1 << 5) +#define TCU_TMSR_FMST4 (1 << 4) +#define TCU_TMSR_FMST3 (1 << 3) +#define TCU_TMSR_FMST2 (1 << 2) +#define TCU_TMSR_FMST1 (1 << 1) +#define TCU_TMSR_FMST0 (1 << 0) + +#define TCU_TMCR_HMCL5 (1 << 21) +#define TCU_TMCR_HMCL4 (1 << 20) +#define TCU_TMCR_HMCL3 (1 << 19) +#define TCU_TMCR_HMCL2 (1 << 18) +#define TCU_TMCR_HMCL1 (1 << 17) +#define TCU_TMCR_HMCL0 (1 << 16) +#define TCU_TMCR_FMCL5 (1 << 5) +#define TCU_TMCR_FMCL4 (1 << 4) +#define TCU_TMCR_FMCL3 (1 << 3) +#define TCU_TMCR_FMCL2 (1 << 2) +#define TCU_TMCR_FMCL1 (1 << 1) +#define TCU_TMCR_FMCL0 (1 << 0) + +#define TCU_TSR_WDTS (1 << 16) +#define TCU_TSR_STOP5 (1 << 5) +#define TCU_TSR_STOP4 (1 << 4) +#define TCU_TSR_STOP3 (1 << 3) +#define TCU_TSR_STOP2 (1 << 2) +#define TCU_TSR_STOP1 (1 << 1) +#define TCU_TSR_STOP0 (1 << 0) + +#define TCU_TSSR_WDTSS (1 << 16) +#define TCU_TSSR_STPS5 (1 << 5) +#define TCU_TSSR_STPS4 (1 << 4) +#define TCU_TSSR_STPS3 (1 << 3) +#define TCU_TSSR_STPS2 (1 << 2) +#define TCU_TSSR_STPS1 (1 << 1) +#define TCU_TSSR_STPS0 (1 << 0) + +#define TCU_TSSR_WDTSC (1 << 16) +#define TCU_TSSR_STPC5 (1 << 5) +#define TCU_TSSR_STPC4 (1 << 4) +#define TCU_TSSR_STPC3 (1 << 3) +#define TCU_TSSR_STPC2 (1 << 2) +#define TCU_TSSR_STPC1 (1 << 1) +#define TCU_TSSR_STPC0 (1 << 0) + + +/************************************************************************* + * WDT (WatchDog Timer) + *************************************************************************/ +#define WDT_TDR (WDT_BASE + 0x00) +#define WDT_TCER (WDT_BASE + 0x04) +#define WDT_TCNT (WDT_BASE + 0x08) +#define WDT_TCSR (WDT_BASE + 0x0C) + +#define REG_WDT_TDR REG16(WDT_TDR) +#define REG_WDT_TCER REG8(WDT_TCER) +#define REG_WDT_TCNT REG16(WDT_TCNT) +#define REG_WDT_TCSR REG16(WDT_TCSR) + +// Register definition +#define WDT_TCSR_PRESCALE_BIT 3 +#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_EXT_EN (1 << 2) +#define WDT_TCSR_RTC_EN (1 << 1) +#define WDT_TCSR_PCK_EN (1 << 0) + +#define WDT_TCER_TCEN (1 << 0) + + +/************************************************************************* + * DMAC (DMA Controller) + *************************************************************************/ + +#define MAX_DMA_NUM 6 /* max 6 channels */ + +#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ +#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ +#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ +#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ +#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ +#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ +#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ +#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ +#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ +#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ +#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ + +// channel 0 +#define DMAC_DSAR0 DMAC_DSAR(0) +#define DMAC_DTAR0 DMAC_DTAR(0) +#define DMAC_DTCR0 DMAC_DTCR(0) +#define DMAC_DRSR0 DMAC_DRSR(0) +#define DMAC_DCCSR0 DMAC_DCCSR(0) +#define DMAC_DCMD0 DMAC_DCMD(0) +#define DMAC_DDA0 DMAC_DDA(0) + +// channel 1 +#define DMAC_DSAR1 DMAC_DSAR(1) +#define DMAC_DTAR1 DMAC_DTAR(1) +#define DMAC_DTCR1 DMAC_DTCR(1) +#define DMAC_DRSR1 DMAC_DRSR(1) +#define DMAC_DCCSR1 DMAC_DCCSR(1) +#define DMAC_DCMD1 DMAC_DCMD(1) +#define DMAC_DDA1 DMAC_DDA(1) + +// channel 2 +#define DMAC_DSAR2 DMAC_DSAR(2) +#define DMAC_DTAR2 DMAC_DTAR(2) +#define DMAC_DTCR2 DMAC_DTCR(2) +#define DMAC_DRSR2 DMAC_DRSR(2) +#define DMAC_DCCSR2 DMAC_DCCSR(2) +#define DMAC_DCMD2 DMAC_DCMD(2) +#define DMAC_DDA2 DMAC_DDA(2) + +// channel 3 +#define DMAC_DSAR3 DMAC_DSAR(3) +#define DMAC_DTAR3 DMAC_DTAR(3) +#define DMAC_DTCR3 DMAC_DTCR(3) +#define DMAC_DRSR3 DMAC_DRSR(3) +#define DMAC_DCCSR3 DMAC_DCCSR(3) +#define DMAC_DCMD3 DMAC_DCMD(3) +#define DMAC_DDA3 DMAC_DDA(3) + +// channel 4 +#define DMAC_DSAR4 DMAC_DSAR(4) +#define DMAC_DTAR4 DMAC_DTAR(4) +#define DMAC_DTCR4 DMAC_DTCR(4) +#define DMAC_DRSR4 DMAC_DRSR(4) +#define DMAC_DCCSR4 DMAC_DCCSR(4) +#define DMAC_DCMD4 DMAC_DCMD(4) +#define DMAC_DDA4 DMAC_DDA(4) + +// channel 5 +#define DMAC_DSAR5 DMAC_DSAR(5) +#define DMAC_DTAR5 DMAC_DTAR(5) +#define DMAC_DTCR5 DMAC_DTCR(5) +#define DMAC_DRSR5 DMAC_DRSR(5) +#define DMAC_DCCSR5 DMAC_DCCSR(5) +#define DMAC_DCMD5 DMAC_DCMD(5) +#define DMAC_DDA5 DMAC_DDA(5) + +#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) +#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) +#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) +#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) +#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) +#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) +#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) +#define REG_DMAC_DMACR REG32(DMAC_DMACR) +#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) +#define REG_DMAC_DMADBR REG32(DMAC_DMADBR) +#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) + +// DMA request source register +#define DMAC_DRSR_RS_BIT 0 +#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) + +// DMA channel control/status register +#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ +#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ +#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) +#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ +#define DMAC_DCCSR_AR (1 << 4) /* address error */ +#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ +#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ +#define DMAC_DCCSR_CT (1 << 1) /* count terminated */ +#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ + +// DMA channel command register +#define DMAC_DCMD_SAI (1 << 23) /* source address increment */ +#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ +#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ +#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) + #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) +#define DMAC_DCMD_SWDH_BIT 14 /* source port width */ +#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) + #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) + #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) + #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) +#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ +#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) + #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) + #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) + #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) +#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ +#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) + #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) + #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) + #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) + #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) + #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) +#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ +#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ +#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ +#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ +#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ +#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ + +// DMA descriptor address register +#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ +#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) +#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ +#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) + +// DMA control register +#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ +#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ +#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ +#define DMAC_DMACR_AR (1 << 2) /* address error flag */ +#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ + +// DMA doorbell register +#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ +#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ +#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ +#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ +#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ +#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ + +// DMA doorbell set register +#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ +#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ +#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ +#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ +#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ +#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ + +// DMA interrupt pending register +#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ +#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ +#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ +#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ +#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ +#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ + + +/************************************************************************* + * GPIO (General-Purpose I/O Ports) + *************************************************************************/ +#define MAX_GPIO_NUM 128 + +//n = 0,1,2,3 +#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ +#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ +#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ +#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ +#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ +#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ +#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ +#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ +#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ +#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ +#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ +#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ +#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ +#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ +#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ +#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ +#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ +#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ +#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ +#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ +#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ +#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ +#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ +#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */ + +#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ +#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ +#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) +#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) +#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ +#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) +#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) +#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ +#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) +#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) +#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ +#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) +#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) +#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ +#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) +#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) +#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ +#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) +#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) +#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ +#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) +#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) +#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ +#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ + + +/************************************************************************* + * UART + *************************************************************************/ + +#define IRDA_BASE UART0_BASE +#define UART_BASE UART0_BASE +#define UART_OFF 0x1000 + +/* Register Offset */ +#define OFF_RDR (0x00) /* R 8b H'xx */ +#define OFF_TDR (0x00) /* W 8b H'xx */ +#define OFF_DLLR (0x00) /* RW 8b H'00 */ +#define OFF_DLHR (0x04) /* RW 8b H'00 */ +#define OFF_IER (0x04) /* RW 8b H'00 */ +#define OFF_ISR (0x08) /* R 8b H'01 */ +#define OFF_FCR (0x08) /* W 8b H'00 */ +#define OFF_LCR (0x0C) /* RW 8b H'00 */ +#define OFF_MCR (0x10) /* RW 8b H'00 */ +#define OFF_LSR (0x14) /* R 8b H'00 */ +#define OFF_MSR (0x18) /* R 8b H'00 */ +#define OFF_SPR (0x1C) /* RW 8b H'00 */ +#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ +#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ +#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ + +/* Register Address */ +#define UART0_RDR (UART0_BASE + OFF_RDR) +#define UART0_TDR (UART0_BASE + OFF_TDR) +#define UART0_DLLR (UART0_BASE + OFF_DLLR) +#define UART0_DLHR (UART0_BASE + OFF_DLHR) +#define UART0_IER (UART0_BASE + OFF_IER) +#define UART0_ISR (UART0_BASE + OFF_ISR) +#define UART0_FCR (UART0_BASE + OFF_FCR) +#define UART0_LCR (UART0_BASE + OFF_LCR) +#define UART0_MCR (UART0_BASE + OFF_MCR) +#define UART0_LSR (UART0_BASE + OFF_LSR) +#define UART0_MSR (UART0_BASE + OFF_MSR) +#define UART0_SPR (UART0_BASE + OFF_SPR) +#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) +#define UART0_UMR (UART0_BASE + OFF_UMR) +#define UART0_UACR (UART0_BASE + OFF_UACR) + +/* + * Define macros for UART_IER + * UART Interrupt Enable Register + */ +#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ +#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ +#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ +#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ +#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ + +/* + * Define macros for UART_ISR + * UART Interrupt Status Register + */ +#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ +#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ +#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ +#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ +#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ +#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ +#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ +#define UART_ISR_FFMS_NO_FIFO (0 << 6) +#define UART_ISR_FFMS_FIFO_MODE (3 << 6) + +/* + * Define macros for UART_FCR + * UART FIFO Control Register + */ +#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ +#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ +#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ +#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ +#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ +#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ +#define UART_FCR_RTRG_1 (0 << 6) +#define UART_FCR_RTRG_4 (1 << 6) +#define UART_FCR_RTRG_8 (2 << 6) +#define UART_FCR_RTRG_15 (3 << 6) + +/* + * Define macros for UART_LCR + * UART Line Control Register + */ +#define UART_LCR_WLEN (3 << 0) /* word length */ +#define UART_LCR_WLEN_5 (0 << 0) +#define UART_LCR_WLEN_6 (1 << 0) +#define UART_LCR_WLEN_7 (2 << 0) +#define UART_LCR_WLEN_8 (3 << 0) +#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ +#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ +#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ + +#define UART_LCR_PE (1 << 3) /* 0: parity disable */ +#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ +#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ +#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ +#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ + +/* + * Define macros for UART_LSR + * UART Line Status Register + */ +#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ +#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ +#define UART_LSR_PER (1 << 2) /* 0: no parity error */ +#define UART_LSR_FER (1 << 3) /* 0; no framing error */ +#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ +#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ +#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ +#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ + +/* + * Define macros for UART_MCR + * UART Modem Control Register + */ +#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ +#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ +#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ +#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ +#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ +#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ + +/* + * Define macros for UART_MSR + * UART Modem Status Register + */ +#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ +#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ +#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ +#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ +#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ +#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ +#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ +#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ + +/* + * Define macros for SIRCR + * Slow IrDA Control Register + */ +#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ +#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ +#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length + 1: 0 pulse width is 1.6us for 115.2Kbps */ +#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ +#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ + + +/************************************************************************* + * AIC (AC97/I2S Controller) + *************************************************************************/ +#define AIC_FR (AIC_BASE + 0x000) +#define AIC_CR (AIC_BASE + 0x004) +#define AIC_ACCR1 (AIC_BASE + 0x008) +#define AIC_ACCR2 (AIC_BASE + 0x00C) +#define AIC_I2SCR (AIC_BASE + 0x010) +#define AIC_SR (AIC_BASE + 0x014) +#define AIC_ACSR (AIC_BASE + 0x018) +#define AIC_I2SSR (AIC_BASE + 0x01C) +#define AIC_ACCAR (AIC_BASE + 0x020) +#define AIC_ACCDR (AIC_BASE + 0x024) +#define AIC_ACSAR (AIC_BASE + 0x028) +#define AIC_ACSDR (AIC_BASE + 0x02C) +#define AIC_I2SDIV (AIC_BASE + 0x030) +#define AIC_DR (AIC_BASE + 0x034) + +#define REG_AIC_FR REG32(AIC_FR) +#define REG_AIC_CR REG32(AIC_CR) +#define REG_AIC_ACCR1 REG32(AIC_ACCR1) +#define REG_AIC_ACCR2 REG32(AIC_ACCR2) +#define REG_AIC_I2SCR REG32(AIC_I2SCR) +#define REG_AIC_SR REG32(AIC_SR) +#define REG_AIC_ACSR REG32(AIC_ACSR) +#define REG_AIC_I2SSR REG32(AIC_I2SSR) +#define REG_AIC_ACCAR REG32(AIC_ACCAR) +#define REG_AIC_ACCDR REG32(AIC_ACCDR) +#define REG_AIC_ACSAR REG32(AIC_ACSAR) +#define REG_AIC_ACSDR REG32(AIC_ACSDR) +#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) +#define REG_AIC_DR REG32(AIC_DR) + +/* AIC Controller Configuration Register (AIC_FR) */ + +#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ +#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) +#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ +#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) +#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ +#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ +#define AIC_FR_RST (1 << 3) /* AIC registers reset */ +#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ +#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ +#define AIC_FR_ENB (1 << 0) /* AIC enable bit */ + +/* AIC Controller Common Control Register (AIC_CR) */ + +#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ +#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) + #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) + #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) + #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) + #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) + #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) +#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ +#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) + #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) + #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) + #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) + #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) + #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) +#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ +#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ +#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ +#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ +#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ +#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ +#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ +#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ +#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ +#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ +#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ +#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ +#define AIC_CR_EREC (1 << 0) /* Enable Record Function */ + +/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ + +#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ +#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) + #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ + #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ + #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ + #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ + #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ + #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ + #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ + #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ + #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ + #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ +#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ +#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) + #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ + #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ + #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ + #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ + #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ + #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ + #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ + #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ + #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ + #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ + +/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ + +#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ +#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ +#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ +#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ +#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) + #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ + #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ + #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ + #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ +#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ +#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) + #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ + #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ + #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ + #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ +#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ +#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ +#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ +#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ + +/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ + +#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ +#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ +#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) + #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ + #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ + #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ + #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ + #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ +#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ + +/* AIC Controller FIFO Status Register (AIC_SR) */ + +#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ +#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) +#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ +#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) +#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ +#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ +#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ +#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ + +/* AIC Controller AC-link Status Register (AIC_ACSR) */ + +#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ +#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ +#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ +#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ +#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ +#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ + +/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ + +#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ + +/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ + +#define AIC_ACCAR_CAR_BIT 0 +#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) + +/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ + +#define AIC_ACCDR_CDR_BIT 0 +#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) + +/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ + +#define AIC_ACSAR_SAR_BIT 0 +#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) + +/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ + +#define AIC_ACSDR_SDR_BIT 0 +#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) + +/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ + +#define AIC_I2SDIV_DIV_BIT 0 +#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) + #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ + #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ + #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ + #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ + #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ + #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ + + +/************************************************************************* + * ICDC (Internal CODEC) + *************************************************************************/ +#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ +#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ +#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ +#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ +#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ +#define ICDC_CDCCR1 (ICDC_BASE + 0x0080) +#define ICDC_CDCCR2 (ICDC_BASE + 0x0084) + +#define REG_ICDC_CR REG32(ICDC_CR) +#define REG_ICDC_APWAIT REG32(ICDC_APWAIT) +#define REG_ICDC_APPRE REG32(ICDC_APPRE) +#define REG_ICDC_APHPEN REG32(ICDC_APHPEN) +#define REG_ICDC_APSR REG32(ICDC_APSR) +#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) +#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) + +/* ICDC Control Register */ +#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ +#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) +#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ +#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) + #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) +#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ +#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) + #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) + #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) + #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) + #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) +#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ +#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) + #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) + #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) + #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) + #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) +#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ +#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ +#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ +#define ICDC_CR_EADC (1 << 10) /* Enable ADC */ +#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ +#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ +#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ +#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ +#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ +#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ +#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ +#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ + +/* Anti-Pop WAIT Stage Timing Control Register */ +#define ICDC_APWAIT_WAITSN_BIT 0 +#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) + +/* Anti-Pop HPEN-PRE Stage Timing Control Register */ +#define ICDC_APPRE_PRESN_BIT 0 +#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) + +/* Anti-Pop HPEN Stage Timing Control Register */ +#define ICDC_APHPEN_HPENSN_BIT 0 +#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) + +/* Anti-Pop Status Register */ +#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ +#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) +#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ +#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ + #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ +#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ + #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ + #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ + #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ + #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ +#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ +#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) + +#define ICDC_CDCCR1_ELININ (1 << 29) +#define ICDC_CDCCR1_EMIC (1 << 28) +#define ICDC_CDCCR1_SW1ON (1 << 27) +#define ICDC_CDCCR1_EADC (1 << 26) +#define ICDC_CDCCR1_SW2ON (1 << 25) +#define ICDC_CDCCR1_EDAC (1 << 24) +#define ICDC_CDCCR1_PDVR (1 << 20) +#define ICDC_CDCCR1_PDVRA (1 << 19) +#define ICDC_CDCCR1_VRPLD (1 << 18) +#define ICDC_CDCCR1_VRCGL (1 << 17) +#define ICDC_CDCCR1_VRCGH (1 << 16) +#define ICDC_CDCCR1_HPMUTE (1 << 14) +#define ICDC_CDCCR1_HPOV0 (1 << 13) +#define ICDC_CDCCR1_HPCG (1 << 12) +#define ICDC_CDCCR1_HPPLDM (1 << 11) +#define ICDC_CDCCR1_HPPLDR (1 << 10) +#define ICDC_CDCCR1_PDHPM (1 << 9) +#define ICDC_CDCCR1_PDHP (1 << 8) +#define ICDC_CDCCR1_SUSPD (1 << 1) +#define ICDC_CDCCR1_RST (1 << 0) + +#define ICDC_CDCCR2_AINVOL(n) ((n & 0x1F) << 16) +#define ICDC_CDCCR2_SMPR(n) ((n & 0xF) << 8) +#define ICDC_CDCCR2_MICBG(n) ((n & 0x3) << 4) +#define ICDC_CDCCR2_HPVOL(n) ((n & 0x3) << 0) + +#define ICDC_CDCCR2_SMPR_8 (0) +#define ICDC_CDCCR2_SMPR_11 (1) +#define ICDC_CDCCR2_SMPR_12 (2) +#define ICDC_CDCCR2_SMPR_16 (3) +#define ICDC_CDCCR2_SMPR_22 (4) +#define ICDC_CDCCR2_SMPR_24 (5) +#define ICDC_CDCCR2_SMPR_32 (6) +#define ICDC_CDCCR2_SMPR_44 (7) +#define ICDC_CDCCR2_SMPR_48 (8) + +#define ICDC_CDCCR2_HPVOL_0 (0) +#define ICDC_CDCCR2_HPVOL_2 (1) +#define ICDC_CDCCR2_HPVOL_4 (2) +#define ICDC_CDCCR2_HPVOL_6 (3) + + +/************************************************************************* + * I2C + *************************************************************************/ +#define I2C_DR (I2C_BASE + 0x000) +#define I2C_CR (I2C_BASE + 0x004) +#define I2C_SR (I2C_BASE + 0x008) +#define I2C_GR (I2C_BASE + 0x00C) + +#define REG_I2C_DR REG8(I2C_DR) +#define REG_I2C_CR REG8(I2C_CR) +#define REG_I2C_SR REG8(I2C_SR) +#define REG_I2C_GR REG16(I2C_GR) + +/* I2C Control Register (I2C_CR) */ + +#define I2C_CR_IEN (1 << 4) +#define I2C_CR_STA (1 << 3) +#define I2C_CR_STO (1 << 2) +#define I2C_CR_AC (1 << 1) +#define I2C_CR_I2CE (1 << 0) + +/* I2C Status Register (I2C_SR) */ + +#define I2C_SR_STX (1 << 4) +#define I2C_SR_BUSY (1 << 3) +#define I2C_SR_TEND (1 << 2) +#define I2C_SR_DRF (1 << 1) +#define I2C_SR_ACKF (1 << 0) + + +/************************************************************************* + * SSI + *************************************************************************/ +#define SSI_DR (SSI_BASE + 0x000) +#define SSI_CR0 (SSI_BASE + 0x004) +#define SSI_CR1 (SSI_BASE + 0x008) +#define SSI_SR (SSI_BASE + 0x00C) +#define SSI_ITR (SSI_BASE + 0x010) +#define SSI_ICR (SSI_BASE + 0x014) +#define SSI_GR (SSI_BASE + 0x018) + +#define REG_SSI_DR REG32(SSI_DR) +#define REG_SSI_CR0 REG16(SSI_CR0) +#define REG_SSI_CR1 REG32(SSI_CR1) +#define REG_SSI_SR REG32(SSI_SR) +#define REG_SSI_ITR REG16(SSI_ITR) +#define REG_SSI_ICR REG8(SSI_ICR) +#define REG_SSI_GR REG16(SSI_GR) + +/* SSI Data Register (SSI_DR) */ + +#define SSI_DR_GPC_BIT 0 +#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) + +/* SSI Control Register 0 (SSI_CR0) */ + +#define SSI_CR0_SSIE (1 << 15) +#define SSI_CR0_TIE (1 << 14) +#define SSI_CR0_RIE (1 << 13) +#define SSI_CR0_TEIE (1 << 12) +#define SSI_CR0_REIE (1 << 11) +#define SSI_CR0_LOOP (1 << 10) +#define SSI_CR0_RFINE (1 << 9) +#define SSI_CR0_RFINC (1 << 8) +#define SSI_CR0_FSEL (1 << 6) +#define SSI_CR0_TFLUSH (1 << 2) +#define SSI_CR0_RFLUSH (1 << 1) +#define SSI_CR0_DISREV (1 << 0) + +/* SSI Control Register 1 (SSI_CR1) */ + +#define SSI_CR1_FRMHL_BIT 30 +#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) + #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ + #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ + #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ + #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ +#define SSI_CR1_TFVCK_BIT 28 +#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) +#define SSI_CR1_TCKFI_BIT 26 +#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) +#define SSI_CR1_LFST (1 << 25) +#define SSI_CR1_ITFRM (1 << 24) +#define SSI_CR1_UNFIN (1 << 23) +#define SSI_CR1_MULTS (1 << 22) +#define SSI_CR1_FMAT_BIT 20 +#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) + #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ + #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ + #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ + #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ +#define SSI_CR1_TTRG_BIT 16 +#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) +#define SSI_CR1_MCOM_BIT 12 +#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) + #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ + #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ + #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ + #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ + #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ + #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ + #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ + #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ + #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ + #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ + #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ + #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ + #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ + #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ + #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ + #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ +#define SSI_CR1_RTRG_BIT 8 +#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) +#define SSI_CR1_FLEN_BIT 4 +#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) +#define SSI_CR1_PHA (1 << 1) +#define SSI_CR1_POL (1 << 0) + +/* SSI Status Register (SSI_SR) */ + +#define SSI_SR_TFIFONUM_BIT 16 +#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) +#define SSI_SR_RFIFONUM_BIT 8 +#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) +#define SSI_SR_END (1 << 7) +#define SSI_SR_BUSY (1 << 6) +#define SSI_SR_TFF (1 << 5) +#define SSI_SR_RFE (1 << 4) +#define SSI_SR_TFHE (1 << 3) +#define SSI_SR_RFHF (1 << 2) +#define SSI_SR_UNDR (1 << 1) +#define SSI_SR_OVER (1 << 0) + +/* SSI Interval Time Control Register (SSI_ITR) */ + +#define SSI_ITR_CNTCLK (1 << 15) +#define SSI_ITR_IVLTM_BIT 0 +#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) + + +/************************************************************************* + * MSC + *************************************************************************/ +#define MSC_STRPCL (MSC_BASE + 0x000) +#define MSC_STAT (MSC_BASE + 0x004) +#define MSC_CLKRT (MSC_BASE + 0x008) +#define MSC_CMDAT (MSC_BASE + 0x00C) +#define MSC_RESTO (MSC_BASE + 0x010) +#define MSC_RDTO (MSC_BASE + 0x014) +#define MSC_BLKLEN (MSC_BASE + 0x018) +#define MSC_NOB (MSC_BASE + 0x01C) +#define MSC_SNOB (MSC_BASE + 0x020) +#define MSC_IMASK (MSC_BASE + 0x024) +#define MSC_IREG (MSC_BASE + 0x028) +#define MSC_CMD (MSC_BASE + 0x02C) +#define MSC_ARG (MSC_BASE + 0x030) +#define MSC_RES (MSC_BASE + 0x034) +#define MSC_RXFIFO (MSC_BASE + 0x038) +#define MSC_TXFIFO (MSC_BASE + 0x03C) + +#define REG_MSC_STRPCL REG16(MSC_STRPCL) +#define REG_MSC_STAT REG32(MSC_STAT) +#define REG_MSC_CLKRT REG16(MSC_CLKRT) +#define REG_MSC_CMDAT REG32(MSC_CMDAT) +#define REG_MSC_RESTO REG16(MSC_RESTO) +#define REG_MSC_RDTO REG16(MSC_RDTO) +#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) +#define REG_MSC_NOB REG16(MSC_NOB) +#define REG_MSC_SNOB REG16(MSC_SNOB) +#define REG_MSC_IMASK REG16(MSC_IMASK) +#define REG_MSC_IREG REG16(MSC_IREG) +#define REG_MSC_CMD REG8(MSC_CMD) +#define REG_MSC_ARG REG32(MSC_ARG) +#define REG_MSC_RES REG16(MSC_RES) +#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) +#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) + +/* MSC Clock and Control Register (MSC_STRPCL) */ + +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) +#define MSC_STRPCL_START_READWAIT (1 << 5) +#define MSC_STRPCL_STOP_READWAIT (1 << 4) +#define MSC_STRPCL_RESET (1 << 3) +#define MSC_STRPCL_START_OP (1 << 2) +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) + #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ + #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ + +/* MSC Status Register (MSC_STAT) */ + +#define MSC_STAT_IS_RESETTING (1 << 15) +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) +#define MSC_STAT_PRG_DONE (1 << 13) +#define MSC_STAT_DATA_TRAN_DONE (1 << 12) +#define MSC_STAT_END_CMD_RES (1 << 11) +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) +#define MSC_STAT_IS_READWAIT (1 << 9) +#define MSC_STAT_CLK_EN (1 << 8) +#define MSC_STAT_DATA_FIFO_FULL (1 << 7) +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) +#define MSC_STAT_CRC_RES_ERR (1 << 5) +#define MSC_STAT_CRC_READ_ERROR (1 << 4) +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) + #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ + #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ + #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ +#define MSC_STAT_TIME_OUT_RES (1 << 1) +#define MSC_STAT_TIME_OUT_READ (1 << 0) + +/* MSC Bus Clock Control Register (MSC_CLKRT) */ + +#define MSC_CLKRT_CLK_RATE_BIT 0 +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) + #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ + +/* MSC Command Sequence Control Register (MSC_CMDAT) */ + +#define MSC_CMDAT_IO_ABORT (1 << 11) +#define MSC_CMDAT_BUS_WIDTH_BIT 9 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) + #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ + #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ + #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) + #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) +#define MSC_CMDAT_DMA_EN (1 << 8) +#define MSC_CMDAT_INIT (1 << 7) +#define MSC_CMDAT_BUSY (1 << 6) +#define MSC_CMDAT_STREAM_BLOCK (1 << 5) +#define MSC_CMDAT_WRITE (1 << 4) +#define MSC_CMDAT_READ (0 << 4) +#define MSC_CMDAT_DATA_EN (1 << 3) +#define MSC_CMDAT_RESPONSE_BIT 0 +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) + #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ + #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ + #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ + #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ + #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ + #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ + #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ + +#define CMDAT_DMA_EN (1 << 8) +#define CMDAT_INIT (1 << 7) +#define CMDAT_BUSY (1 << 6) +#define CMDAT_STREAM (1 << 5) +#define CMDAT_WRITE (1 << 4) +#define CMDAT_DATA_EN (1 << 3) + +/* MSC Interrupts Mask Register (MSC_IMASK) */ + +#define MSC_IMASK_SDIO (1 << 7) +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) +#define MSC_IMASK_END_CMD_RES (1 << 2) +#define MSC_IMASK_PRG_DONE (1 << 1) +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) + + +/* MSC Interrupts Status Register (MSC_IREG) */ + +#define MSC_IREG_SDIO (1 << 7) +#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) +#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) +#define MSC_IREG_END_CMD_RES (1 << 2) +#define MSC_IREG_PRG_DONE (1 << 1) +#define MSC_IREG_DATA_TRAN_DONE (1 << 0) + + +/************************************************************************* + * EMC (External Memory Controller) + *************************************************************************/ +#define EMC_BCR (EMC_BASE + 0x0) /* BCR */ + +#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ +#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ +#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ +#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ +#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ +#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ +#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ +#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ +#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ +#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ + +#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ +#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ +#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ +#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ +#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ +#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ +#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ +#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ +#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ +#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ +#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ +#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ + +#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ +#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ +#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ +#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ +#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ +#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ + +#define REG_EMC_BCR REG32(EMC_BCR) + +#define REG_EMC_SMCR0 REG32(EMC_SMCR0) +#define REG_EMC_SMCR1 REG32(EMC_SMCR1) +#define REG_EMC_SMCR2 REG32(EMC_SMCR2) +#define REG_EMC_SMCR3 REG32(EMC_SMCR3) +#define REG_EMC_SMCR4 REG32(EMC_SMCR4) +#define REG_EMC_SACR0 REG32(EMC_SACR0) +#define REG_EMC_SACR1 REG32(EMC_SACR1) +#define REG_EMC_SACR2 REG32(EMC_SACR2) +#define REG_EMC_SACR3 REG32(EMC_SACR3) +#define REG_EMC_SACR4 REG32(EMC_SACR4) + +#define REG_EMC_NFCSR REG32(EMC_NFCSR) +#define REG_EMC_NFECR REG32(EMC_NFECR) +#define REG_EMC_NFECC REG32(EMC_NFECC) +#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) +#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) +#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) +#define REG_EMC_NFINTS REG32(EMC_NFINTS) +#define REG_EMC_NFINTE REG32(EMC_NFINTE) +#define REG_EMC_NFERR0 REG32(EMC_NFERR0) +#define REG_EMC_NFERR1 REG32(EMC_NFERR1) +#define REG_EMC_NFERR2 REG32(EMC_NFERR2) +#define REG_EMC_NFERR3 REG32(EMC_NFERR3) + +#define REG_EMC_DMCR REG32(EMC_DMCR) +#define REG_EMC_RTCSR REG16(EMC_RTCSR) +#define REG_EMC_RTCNT REG16(EMC_RTCNT) +#define REG_EMC_RTCOR REG16(EMC_RTCOR) +#define REG_EMC_DMAR0 REG32(EMC_DMAR0) + +/* Static Memory Control Register */ +#define EMC_SMCR_STRV_BIT 24 +#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) +#define EMC_SMCR_TAW_BIT 20 +#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) +#define EMC_SMCR_TBP_BIT 16 +#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) +#define EMC_SMCR_TAH_BIT 12 +#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) +#define EMC_SMCR_TAS_BIT 8 +#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) +#define EMC_SMCR_BW_BIT 6 +#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) /* Bus Width? */ + #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) + #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) + #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) +#define EMC_SMCR_BCM (1 << 3) +#define EMC_SMCR_BL_BIT 1 +#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) /* Bus Latency? */ + #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_SMT (1 << 0) + +/* Static Memory Bank Addr Config Reg */ +#define EMC_SACR_BASE_BIT 8 +#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) +#define EMC_SACR_MASK_BIT 0 +#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) + +/* NAND Flash Control/Status Register */ +#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ +#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ +#define EMC_NFCSR_NFCE3 (1 << 5) +#define EMC_NFCSR_NFE3 (1 << 4) +#define EMC_NFCSR_NFCE2 (1 << 3) +#define EMC_NFCSR_NFE2 (1 << 2) +#define EMC_NFCSR_NFCE1 (1 << 1) +#define EMC_NFCSR_NFE1 (1 << 0) +#define EMC_NFCSR_NFE(n) (1 << (((n)-1)*2)) +#define EMC_NFCSR_NFCE(n) (1 << (((n)*2)-1)) + +/* NAND Flash ECC Control Register */ +#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ +#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ +#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ +#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ +#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ +#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ +#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ + +/* NAND Flash ECC Data Register */ +#define EMC_NFECC_ECC2_BIT 16 +#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) +#define EMC_NFECC_ECC1_BIT 8 +#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) +#define EMC_NFECC_ECC0_BIT 0 +#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) + +/* NAND Flash Interrupt Status Register */ +#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ +#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) +#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ +#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ +#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ +#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ +#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ + +/* NAND Flash Interrupt Enable Register */ +#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ +#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ +#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ +#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ +#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ + +/* NAND Flash RS Error Report Register */ +#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ +#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) +#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ +#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) + + +/* DRAM Control Register */ +#define EMC_DMCR_BW_BIT 31 +#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) +#define EMC_DMCR_CA_BIT 26 +#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_RMODE (1 << 25) +#define EMC_DMCR_RFSH (1 << 24) +#define EMC_DMCR_MRSET (1 << 23) +#define EMC_DMCR_RA_BIT 20 +#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) + #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) + #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) + #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) +#define EMC_DMCR_BA_BIT 19 +#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) +#define EMC_DMCR_PDM (1 << 18) +#define EMC_DMCR_EPIN (1 << 17) +#define EMC_DMCR_TRAS_BIT 13 +#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) +#define EMC_DMCR_RCD_BIT 11 +#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) +#define EMC_DMCR_TPC_BIT 8 +#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) +#define EMC_DMCR_TRWL_BIT 5 +#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) +#define EMC_DMCR_TRC_BIT 2 +#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) +#define EMC_DMCR_TCL_BIT 0 +#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) + +/* Refresh Time Control/Status Register */ +#define EMC_RTCSR_CMF (1 << 7) +#define EMC_RTCSR_CKS_BIT 0 +#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) + +/* SDRAM Bank Address Configuration Register */ +#define EMC_DMAR_BASE_BIT 8 +#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) +#define EMC_DMAR_MASK_BIT 0 +#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) + +/* Mode Register of SDRAM bank 0 */ +#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ +#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ +#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) + #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) +#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ +#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) + #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) + #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) + #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) +#define EMC_SDMR_BT_BIT 3 /* Burst Type */ +#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) + #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ + #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ +#define EMC_SDMR_BL_BIT 0 /* Burst Length */ +#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) + +#define EMC_SDMR_CAS2_16BIT \ + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) +#define EMC_SDMR_CAS2_32BIT \ + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) +#define EMC_SDMR_CAS3_16BIT \ + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) +#define EMC_SDMR_CAS3_32BIT \ + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) + + +/************************************************************************* + * CIM + *************************************************************************/ +#define CIM_CFG (CIM_BASE + 0x0000) +#define CIM_CTRL (CIM_BASE + 0x0004) +#define CIM_STATE (CIM_BASE + 0x0008) +#define CIM_IID (CIM_BASE + 0x000C) +#define CIM_RXFIFO (CIM_BASE + 0x0010) +#define CIM_DA (CIM_BASE + 0x0020) +#define CIM_FA (CIM_BASE + 0x0024) +#define CIM_FID (CIM_BASE + 0x0028) +#define CIM_CMD (CIM_BASE + 0x002C) + +#define REG_CIM_CFG REG32(CIM_CFG) +#define REG_CIM_CTRL REG32(CIM_CTRL) +#define REG_CIM_STATE REG32(CIM_STATE) +#define REG_CIM_IID REG32(CIM_IID) +#define REG_CIM_RXFIFO REG32(CIM_RXFIFO) +#define REG_CIM_DA REG32(CIM_DA) +#define REG_CIM_FA REG32(CIM_FA) +#define REG_CIM_FID REG32(CIM_FID) +#define REG_CIM_CMD REG32(CIM_CMD) + +/* CIM Configuration Register (CIM_CFG) */ + +#define CIM_CFG_INV_DAT (1 << 15) +#define CIM_CFG_VSP (1 << 14) +#define CIM_CFG_HSP (1 << 13) +#define CIM_CFG_PCP (1 << 12) +#define CIM_CFG_DUMMY_ZERO (1 << 9) +#define CIM_CFG_EXT_VSYNC (1 << 8) +#define CIM_CFG_PACK_BIT 4 +#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) +#define CIM_CFG_DSM_BIT 0 +#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) + #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ + #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ + #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ + #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ + +/* CIM Control Register (CIM_CTRL) */ + +#define CIM_CTRL_MCLKDIV_BIT 24 +#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) +#define CIM_CTRL_FRC_BIT 16 +#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) + #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ + #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ + #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ + #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ + #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ + #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ + #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ + #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ + #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ + #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ + #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ + #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ + #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ + #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ + #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ + #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ +#define CIM_CTRL_VDDM (1 << 13) +#define CIM_CTRL_DMA_SOFM (1 << 12) +#define CIM_CTRL_DMA_EOFM (1 << 11) +#define CIM_CTRL_DMA_STOPM (1 << 10) +#define CIM_CTRL_RXF_TRIGM (1 << 9) +#define CIM_CTRL_RXF_OFM (1 << 8) +#define CIM_CTRL_RXF_TRIG_BIT 4 +#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) + #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ + #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ + #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ + #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ + #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ + #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ + #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ + #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ +#define CIM_CTRL_DMA_EN (1 << 2) +#define CIM_CTRL_RXF_RST (1 << 1) +#define CIM_CTRL_ENA (1 << 0) + +/* CIM State Register (CIM_STATE) */ + +#define CIM_STATE_DMA_SOF (1 << 6) +#define CIM_STATE_DMA_EOF (1 << 5) +#define CIM_STATE_DMA_STOP (1 << 4) +#define CIM_STATE_RXF_OF (1 << 3) +#define CIM_STATE_RXF_TRIG (1 << 2) +#define CIM_STATE_RXF_EMPTY (1 << 1) +#define CIM_STATE_VDD (1 << 0) + +/* CIM DMA Command Register (CIM_CMD) */ + +#define CIM_CMD_SOFINT (1 << 31) +#define CIM_CMD_EOFINT (1 << 30) +#define CIM_CMD_STOP (1 << 28) +#define CIM_CMD_LEN_BIT 0 +#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) + + +/************************************************************************* + * SADC (Smart A/D Controller) + *************************************************************************/ + +#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ +#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ +#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ +#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ +#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ +#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ +#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ +#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ +#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ + +#define REG_SADC_ENA REG8(SADC_ENA) +#define REG_SADC_CFG REG32(SADC_CFG) +#define REG_SADC_CTRL REG8(SADC_CTRL) +#define REG_SADC_STATE REG8(SADC_STATE) +#define REG_SADC_SAMETIME REG16(SADC_SAMETIME) +#define REG_SADC_WAITTIME REG16(SADC_WAITTIME) +#define REG_SADC_TSDAT REG32(SADC_TSDAT) +#define REG_SADC_BATDAT REG16(SADC_BATDAT) +#define REG_SADC_SADDAT REG16(SADC_SADDAT) + +/* ADC Enable Register */ +#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ +#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ +#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ +#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ + +/* ADC Configure Register */ +#define SADC_CFG_CLKOUT_NUM_BIT 16 +#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) +#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ +#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ +#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) + #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) + #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) + #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) +#define SADC_CFG_SNUM_BIT 10 /* Sample Number */ +#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) + #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) +#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ +#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) +#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ +#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ +#define SADC_CFG_CMD_BIT 0 /* ADC Command */ +#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) + #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ + #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ + #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ + #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ + #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ + #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ + #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ + #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ + #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ + #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ + #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ + #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ + #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ + +/* ADC Control Register */ +#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ +#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ +#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ +#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ +#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ + +/* ADC Status Register */ +#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ +#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ +#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ +#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ +#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ +#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ +#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ +#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ + +/* ADC Touch Screen Data Register */ +#define SADC_TSDAT_DATA0_BIT 0 +#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) +#define SADC_TSDAT_TYPE0 (1 << 15) +#define SADC_TSDAT_DATA1_BIT 16 +#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) +#define SADC_TSDAT_TYPE1 (1 << 31) + + +/************************************************************************* + * SLCD (Smart LCD Controller) + *************************************************************************/ + +#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ +#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ +#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ +#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ +#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ + +#define REG_SLCD_CFG REG32(SLCD_CFG) +#define REG_SLCD_CTRL REG8(SLCD_CTRL) +#define REG_SLCD_STATE REG8(SLCD_STATE) +#define REG_SLCD_DATA REG32(SLCD_DATA) +#define REG_SLCD_FIFO REG32(SLCD_FIFO) + +/* SLCD Configure Register */ +#define SLCD_CFG_BURST_BIT 14 +#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) + #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) + #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) +#define SLCD_CFG_DWIDTH_BIT 10 +#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) + #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) + #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) + #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) + #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) + #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) + #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT) +#define SLCD_CFG_CWIDTH_BIT 8 +#define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) + #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) + #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) + #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) +#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) +#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) +#define SLCD_CFG_RS_CMD_LOW (0 << 3) +#define SLCD_CFG_RS_CMD_HIGH (1 << 3) +#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) +#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) +#define SLCD_CFG_TYPE_PARALLEL (0 << 0) +#define SLCD_CFG_TYPE_SERIAL (1 << 0) + +/* SLCD Control Register */ +#define SLCD_CTRL_DMA_EN (1 << 0) + +/* SLCD Status Register */ +#define SLCD_STATE_BUSY (1 << 0) + +/* SLCD Data Register */ +#define SLCD_DATA_RS_DATA (0 << 31) +#define SLCD_DATA_RS_COMMAND (1 << 31) + +/* SLCD FIFO Register */ +#define SLCD_FIFO_RS_DATA (0 << 31) +#define SLCD_FIFO_RS_COMMAND (1 << 31) + + +/************************************************************************* + * LCD (LCD Controller) + *************************************************************************/ +#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ +#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ +#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ +#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ +#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ +#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ +#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ +#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ +#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ +#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ +#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ +#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ +#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ +#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ +#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ +#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ +#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ +#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ +#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ +#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ +#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ + +#define REG_LCD_CFG REG32(LCD_CFG) +#define REG_LCD_VSYNC REG32(LCD_VSYNC) +#define REG_LCD_HSYNC REG32(LCD_HSYNC) +#define REG_LCD_VAT REG32(LCD_VAT) +#define REG_LCD_DAH REG32(LCD_DAH) +#define REG_LCD_DAV REG32(LCD_DAV) +#define REG_LCD_PS REG32(LCD_PS) +#define REG_LCD_CLS REG32(LCD_CLS) +#define REG_LCD_SPL REG32(LCD_SPL) +#define REG_LCD_REV REG32(LCD_REV) +#define REG_LCD_CTRL REG32(LCD_CTRL) +#define REG_LCD_STATE REG32(LCD_STATE) +#define REG_LCD_IID REG32(LCD_IID) +#define REG_LCD_DA0 REG32(LCD_DA0) +#define REG_LCD_SA0 REG32(LCD_SA0) +#define REG_LCD_FID0 REG32(LCD_FID0) +#define REG_LCD_CMD0 REG32(LCD_CMD0) +#define REG_LCD_DA1 REG32(LCD_DA1) +#define REG_LCD_SA1 REG32(LCD_SA1) +#define REG_LCD_FID1 REG32(LCD_FID1) +#define REG_LCD_CMD1 REG32(LCD_CMD1) + +/* LCD Configure Register */ +#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ +#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) + #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) + #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) +#define LCD_CFG_PSM (1 << 23) /* PS signal mode */ +#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ +#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ +#define LCD_CFG_REVM (1 << 20) /* REV signal mode */ +#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ +#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ +#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ +#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ +#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ +#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ +#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ +#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ +#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ +#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ +#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ +#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ +#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ +#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) +#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ + #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ + #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ + #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ +#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ +#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ + #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) + /* JZ47XX defines */ + #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) + + + +/* Vertical Synchronize Register */ +#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ +#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) +#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ +#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) + +/* Horizontal Synchronize Register */ +#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ +#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) +#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ +#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) + +/* Virtual Area Setting Register */ +#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ +#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) +#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ +#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) + +/* Display Area Horizontal Start/End Point Register */ +#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ +#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) +#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ +#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) + +/* Display Area Vertical Start/End Point Register */ +#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ +#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) +#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ +#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) + +/* PS Signal Setting */ +#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ +#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) +#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ +#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) + +/* CLS Signal Setting */ +#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ +#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) +#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ +#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) + +/* SPL Signal Setting */ +#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ +#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) +#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ +#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) + +/* REV Signal Setting */ +#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ +#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) + +/* LCD Control Register */ +#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ +#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ +#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ +#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ +#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ +#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ +#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) +#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ +#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ +#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ +#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ +#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ +#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ +#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ +#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ +#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ +#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ +#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ +#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ + #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ + +/* LCD Status Register */ +#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ +#define LCD_STATE_EOF (1 << 5) /* EOF Flag */ +#define LCD_STATE_SOF (1 << 4) /* SOF Flag */ +#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ +#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ +#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ +#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ + +/* DMA Command Register */ +#define LCD_CMD_SOFINT (1 << 31) +#define LCD_CMD_EOFINT (1 << 30) +#define LCD_CMD_PAL (1 << 28) +#define LCD_CMD_LEN_BIT 0 +#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) + + +/************************************************************************* + * USB Device + *************************************************************************/ +#define USB_BASE UDC_BASE + +#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ +#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ +#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ +#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ +#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ +#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ +#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ +#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ +#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ +#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ +#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ + +#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ +#define USB_REG_COUNT0 (USB_BASE + 0x18) /* bytes in EP0 FIFO 16-bit */ +#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ +#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ +#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ +#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ +#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ +#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ +#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ + +#define USB_FIFO_EP0 (USB_BASE + 0x20) +#define USB_FIFO_EP1 (USB_BASE + 0x24) +#define USB_FIFO_EP2 (USB_BASE + 0x28) + +#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ +#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ + +#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts 8-bit */ +#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control 32-bit */ +#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr 32-bit */ +#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count 32-bit */ +#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control 32-bit */ +#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr 32-bit */ +#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count 32-bit */ + +#define REG_USB_REG_FADDR REG8(USB_REG_FADDR) +#define REG_USB_REG_POWER REG8(USB_REG_POWER) +#define REG_USB_REG_INTRIN REG16(USB_REG_INTRIN) +#define REG_USB_REG_INTROUT REG16(USB_REG_INTROUT) +#define REG_USB_REG_INTRINE REG16(USB_REG_INTRINE) +#define REG_USB_REG_INTROUTE REG16(USB_REG_INTROUTE) +#define REG_USB_REG_INTRUSB REG8(USB_REG_INTRUSB) +#define REG_USB_REG_INTRUSBE REG8(USB_REG_INTRUSBE) +#define REG_USB_REG_FRAME REG16(USB_REG_FRAME) +#define REG_USB_REG_INDEX REG8(USB_REG_INDEX) +#define REG_USB_REG_TESTMODE REG8(USB_REG_TESTMODE) + +#define REG_USB_REG_CSR0 REG8(USB_REG_CSR0) +#define REG_USB_REG_COUNT0 REG16(USB_REG_COUNT0) +#define REG_USB_REG_INMAXP REG16(USB_REG_INMAXP) +#define REG_USB_REG_INCSR REG16(USB_REG_INCSR) +#define REG_USB_REG_INCSRH REG8(USB_REG_INCSRH) +#define REG_USB_REG_OUTMAXP REG16(USB_REG_OUTMAXP) +#define REG_USB_REG_OUTCSR REG16(USB_REG_OUTCSR) +#define REG_USB_REG_OUTCSRH REG8(USB_REG_OUTCSRH) +#define REG_USB_REG_OUTCOUNT REG16(USB_REG_OUTCOUNT) + +#define REG_USB_FIFO_EP0 REG32(USB_FIFO_EP0) +#define REG_USB_FIFO_EP1 REG32(USB_FIFO_EP1) +#define REG_USB_FIFO_EP2 REG32(USB_FIFO_EP2) + +#define REG_USB_REG_INTR REG8(USB_REG_INTR) +#define REG_USB_REG_CNTL1 REG32(USB_REG_CNTL1) +#define REG_USB_REG_ADDR1 REG32(USB_REG_ADDR1) +#define REG_USB_REG_COUNT1 REG32(USB_REG_COUNT1) +#define REG_USB_REG_CNTL2 REG32(USB_REG_CNTL2) +#define REG_USB_REG_ADDR2 REG32(USB_REG_ADDR2) +#define REG_USB_REG_COUNT2 REG32(USB_REG_COUNT2) + +#define REG_USB_REG_EPINFO REG16(USB_REG_EPINFO) +#define REG_USB_REG_RAMINFO REG8(USB_REG_RAMINFO) + + +/* Power register bit masks */ +#define USB_POWER_SUSPENDM 0x01 +#define USB_POWER_RESUME 0x04 +#define USB_POWER_HSMODE 0x10 +#define USB_POWER_HSENAB 0x20 +#define USB_POWER_SOFTCONN 0x40 + +/* Interrupt register bit masks */ +#define USB_INTR_SUSPEND 0x01 +#define USB_INTR_RESUME 0x02 +#define USB_INTR_RESET 0x04 + +#define USB_INTR_EP0 0x0001 +#define USB_INTR_INEP1 0x0002 +#define USB_INTR_INEP2 0x0004 +#define USB_INTR_OUTEP1 0x0002 +#define USB_INTR_OUTEP2 0x0004 + +#define USB_INTR_EP(n) ((n)==0 ? 1 : ((n)*2)) + +/* CSR0 bit masks */ +#define USB_CSR0_OUTPKTRDY 0x01 +#define USB_CSR0_INPKTRDY 0x02 +#define USB_CSR0_SENTSTALL 0x04 +#define USB_CSR0_DATAEND 0x08 +#define USB_CSR0_SETUPEND 0x10 +#define USB_CSR0_SENDSTALL 0x20 +#define USB_CSR0_SVDOUTPKTRDY 0x40 +#define USB_CSR0_SVDSETUPEND 0x80 + +/* Endpoint CSR register bits */ +#define USB_INCSRH_AUTOSET 0x80 +#define USB_INCSRH_ISO 0x40 +#define USB_INCSRH_MODE 0x20 +#define USB_INCSRH_DMAREQENAB 0x10 +#define USB_INCSRH_FRCDATATOG 0x08 +#define USB_INCSRH_DMAREQMODE 0x04 +#define USB_INCSR_CDT 0x40 +#define USB_INCSR_SENTSTALL 0x20 +#define USB_INCSR_SENDSTALL 0x10 +#define USB_INCSR_FF 0x08 +#define USB_INCSR_UNDERRUN 0x04 +#define USB_INCSR_FFNOTEMPT 0x02 +#define USB_INCSR_INPKTRDY 0x01 +#define USB_OUTCSRH_AUTOCLR 0x80 +#define USB_OUTCSRH_ISO 0x40 +#define USB_OUTCSRH_DMAREQENAB 0x20 +#define USB_OUTCSRH_DNYT 0x10 +#define USB_OUTCSRH_DMAREQMODE 0x08 +#define USB_OUTCSR_CDT 0x80 +#define USB_OUTCSR_SENTSTALL 0x40 +#define USB_OUTCSR_SENDSTALL 0x20 +#define USB_OUTCSR_FF 0x10 +#define USB_OUTCSR_DATAERR 0x08 +#define USB_OUTCSR_OVERRUN 0x04 +#define USB_OUTCSR_FFFULL 0x02 +#define USB_OUTCSR_OUTPKTRDY 0x01 + +/* Testmode register bits */ +#define USB_TEST_SE0NAK 0x01 +#define USB_TEST_J 0x02 +#define USB_TEST_K 0x04 +#define USB_TEST_PACKET 0x08 +#define USB_TEST_FORCE_HS 0x10 +#define USB_TEST_FORCE_FS 0x20 +#define USB_TEST_ALL ( USB_TEST_SE0NAK | USB_TEST_J \ + | USB_TEST_K | USB_TEST_PACKET \ + | USB_TEST_FORCE_HS | USB_TEST_FORCE_FS) + +/* DMA control bits */ +#define USB_CNTL_ENA 0x01 +#define USB_CNTL_DIR_IN 0x02 +#define USB_CNTL_MODE_1 0x04 +#define USB_CNTL_INTR_EN 0x08 +#define USB_CNTL_EP(n) ((n) << 4) +#define USB_CNTL_BURST_0 (0 << 9) +#define USB_CNTL_BURST_4 (1 << 9) +#define USB_CNTL_BURST_8 (2 << 9) +#define USB_CNTL_BURST_16 (3 << 9) + +/* DMA interrupt bits */ +#define USB_INTR_DMA_BULKIN 1 +#define USB_INTR_DMA_BULKOUT 2 + + +//---------------------------------------------------------------------- +// +// Module Operation Definitions +// +//---------------------------------------------------------------------- +#ifndef __ASSEMBLY__ + +/*************************************************************************** + * GPIO + ***************************************************************************/ + +//------------------------------------------------------ +// GPIO Pins Description +// +// PORT 0: +// +// PIN/BIT N FUNC0 FUNC1 +// 0 D0 - +// 1 D1 - +// 2 D2 - +// 3 D3 - +// 4 D4 - +// 5 D5 - +// 6 D6 - +// 7 D7 - +// 8 D8 - +// 9 D9 - +// 10 D10 - +// 11 D11 - +// 12 D12 - +// 13 D13 - +// 14 D14 - +// 15 D15 - +// 16 D16 - +// 17 D17 - +// 18 D18 - +// 19 D19 - +// 20 D20 - +// 21 D21 - +// 22 D22 - +// 23 D23 - +// 24 D24 - +// 25 D25 - +// 26 D26 - +// 27 D27 - +// 28 D28 - +// 29 D29 - +// 30 D30 - +// 31 D31 - +// +//------------------------------------------------------ +// PORT 1: +// +// PIN/BIT N FUNC0 FUNC1 +// 0 A0 - +// 1 A1 - +// 2 A2 - +// 3 A3 - +// 4 A4 - +// 5 A5 - +// 6 A6 - +// 7 A7 - +// 8 A8 - +// 9 A9 - +// 10 A10 - +// 11 A11 - +// 12 A12 - +// 13 A13 - +// 14 A14 - +// 15 A15/CL - +// 16 A16/AL - +// 17 LCD_CLS A21 +// 18 LCD_SPL A22 +// 19 DCS# - +// 20 RAS# - +// 21 CAS# - +// 22 RDWE#/BUFD# - +// 23 CKE - +// 24 CKO - +// 25 CS1# - +// 26 CS2# - +// 27 CS3# - +// 28 CS4# - +// 29 RD# - +// 30 WR# - +// 31 WE0# - +// +// Note: PIN15&16 are CL&AL when connecting to NAND flash. +//------------------------------------------------------ +// PORT 2: +// +// PIN/BIT N FUNC0 FUNC1 +// 0 LCD_D0 - +// 1 LCD_D1 - +// 2 LCD_D2 - +// 3 LCD_D3 - +// 4 LCD_D4 - +// 5 LCD_D5 - +// 6 LCD_D6 - +// 7 LCD_D7 - +// 8 LCD_D8 - +// 9 LCD_D9 - +// 10 LCD_D10 - +// 11 LCD_D11 - +// 12 LCD_D12 - +// 13 LCD_D13 - +// 14 LCD_D14 - +// 15 LCD_D15 - +// 16 LCD_D16 - +// 17 LCD_D17 - +// 18 LCD_PCLK - +// 19 LCD_HSYNC - +// 20 LCD_VSYNC - +// 21 LCD_DE - +// 22 LCD_PS A19 +// 23 LCD_REV A20 +// 24 WE1# - +// 25 WE2# - +// 26 WE3# - +// 27 WAIT# - +// 28 FRE# - +// 29 FWE# - +// 30(NOTE:FRB#) - - +// 31 - - +// +// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. +//------------------------------------------------------ +// PORT 3: +// +// PIN/BIT N FUNC0 FUNC1 +// 0 CIM_D0 - +// 1 CIM_D1 - +// 2 CIM_D2 - +// 3 CIM_D3 - +// 4 CIM_D4 - +// 5 CIM_D5 - +// 6 CIM_D6 - +// 7 CIM_D7 - +// 8 MSC_CMD - +// 9 MSC_CLK - +// 10 MSC_D0 - +// 11 MSC_D1 - +// 12 MSC_D2 - +// 13 MSC_D3 - +// 14 CIM_MCLK - +// 15 CIM_PCLK - +// 16 CIM_VSYNC - +// 17 CIM_HSYNC - +// 18 SSI_CLK SCLK_RSTN +// 19 SSI_CE0# BIT_CLK(AIC) +// 20 SSI_DT SDATA_OUT(AIC) +// 21 SSI_DR SDATA_IN(AIC) +// 22 SSI_CE1#&GPC SYNC(AIC) +// 23 PWM0 I2C_SDA +// 24 PWM1 I2C_SCK +// 25 PWM2 UART0_TxD +// 26 PWM3 UART0_RxD +// 27 PWM4 A17 +// 28 PWM5 A18 +// 29 - - +// 30 PWM6 UART0_CTS/UART1_RxD +// 31 PWM7 UART0_RTS/UART1_TxD +// +////////////////////////////////////////////////////////// + +/* + * p is the port number (0,1,2,3) + * o is the pin offset (0-31) inside the port + * n is the absolute number of a pin (0-127), regardless of the port + */ + +//------------------------------------------- +// Function Pins Mode + +#define __gpio_as_func0(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXFUNS(p) = (1 << o); \ + REG_GPIO_PXSELC(p) = (1 << o); \ +} while (0) + +#define __gpio_as_func1(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXFUNS(p) = (1 << o); \ + REG_GPIO_PXSELS(p) = (1 << o); \ +} while (0) + +/* + * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, + * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# + */ +#define __gpio_as_sdram_32bit() \ +do { \ + REG_GPIO_PXFUNS(0) = 0xffffffff; \ + REG_GPIO_PXSELC(0) = 0xffffffff; \ + REG_GPIO_PXPES(0) = 0xffffffff; \ + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ + REG_GPIO_PXSELC(1) = 0x81f9ffff; \ + REG_GPIO_PXPES(1) = 0x81f9ffff; \ + REG_GPIO_PXFUNS(2) = 0x07000000; \ + REG_GPIO_PXSELC(2) = 0x07000000; \ + REG_GPIO_PXPES(2) = 0x07000000; \ +} while (0) + +//#ifdef JZ4740_PAVO +#ifdef JZ4740_4740 +/* + * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, + * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# + */ +#define __gpio_as_sdram_16bit() \ +do { \ + REG_GPIO_PXFUNS(0) = 0x0000ffff; \ + REG_GPIO_PXFUNS(0) = 0x0000ffff; \ + REG_GPIO_PXPES(0) = 0x0000ffff; \ + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ + REG_GPIO_PXSELC(1) = 0x81f9ffff; \ + REG_GPIO_PXPES(1) = 0x81f9ffff; \ + REG_GPIO_PXFUNS(2) = 0x07000000; \ + REG_GPIO_PXSELC(2) = 0x07000000; \ + REG_GPIO_PXPES(2) = 0x07000000; \ +} while (0) + +#endif + +//#ifdef JZ4740_VIRGO +#ifdef JZ4740_4720 +/* + * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, + * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# + */ +#define __gpio_as_sdram_16bit() \ +do { \ + REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ + REG_GPIO_PXSELC(0) = 0x5442bfaa; \ + REG_GPIO_PXPES(0) = 0x5442bfaa; \ + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ + REG_GPIO_PXSELC(1) = 0x81f9ffff; \ + REG_GPIO_PXPES(1) = 0x81f9ffff; \ + REG_GPIO_PXFUNS(2) = 0x01000000; \ + REG_GPIO_PXSELC(2) = 0x01000000; \ + REG_GPIO_PXPES(2) = 0x01000000; \ +} while (0) +#endif + + +#ifdef JZ4740_4725 +/* + * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, + * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# + */ +#define __jz4725__gpio_as_sdram_16bit() \ +do { \ + REG_GPIO_PXFUNS(0) = 0x0000ffff; \ + REG_GPIO_PXSELC(0) = 0x0000ffff; \ + REG_GPIO_PXPES(0) = 0x0000ffff; \ + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ + REG_GPIO_PXSELC(1) = 0x81f9ffff; \ + REG_GPIO_PXPES(1) = 0x81f9ffff; \ + REG_GPIO_PXFUNS(2) = 0x07000000; \ + REG_GPIO_PXSELC(2) = 0x07000000; \ + REG_GPIO_PXPES(2) = 0x07000000; \ +} while (0) +#endif +/* + * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# + */ +#define __gpio_as_nand() \ +do { \ + REG_GPIO_PXFUNS(1) = 0x02018000; \ + REG_GPIO_PXSELC(1) = 0x02018000; \ + REG_GPIO_PXPES(1) = 0x02018000; \ + REG_GPIO_PXFUNS(2) = 0x30000000; \ + REG_GPIO_PXSELC(2) = 0x30000000; \ + REG_GPIO_PXPES(2) = 0x30000000; \ + REG_GPIO_PXFUNC(2) = 0x40000000; \ + REG_GPIO_PXSELC(2) = 0x40000000; \ + REG_GPIO_PXDIRC(2) = 0x40000000; \ + REG_GPIO_PXPES(2) = 0x40000000; \ + REG_GPIO_PXFUNS(1) = 0x00400000; \ + REG_GPIO_PXSELC(1) = 0x00400000; \ +} while (0) + +/* + * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 + */ +#define __gpio_as_nor_8bit() \ +do { \ + REG_GPIO_PXFUNS(0) = 0x000000ff; \ + REG_GPIO_PXSELC(0) = 0x000000ff; \ + REG_GPIO_PXPES(0) = 0x000000ff; \ + REG_GPIO_PXFUNS(1) = 0x7041ffff; \ + REG_GPIO_PXSELC(1) = 0x7041ffff; \ + REG_GPIO_PXPES(1) = 0x7041ffff; \ + REG_GPIO_PXFUNS(1) = 0x00060000; \ + REG_GPIO_PXSELS(1) = 0x00060000; \ + REG_GPIO_PXPES(1) = 0x00060000; \ + REG_GPIO_PXFUNS(2) = 0x08000000; \ + REG_GPIO_PXSELC(2) = 0x08000000; \ + REG_GPIO_PXPES(2) = 0x08000000; \ + REG_GPIO_PXFUNS(2) = 0x00c00000; \ + REG_GPIO_PXSELS(2) = 0x00c00000; \ + REG_GPIO_PXPES(2) = 0x00c00000; \ + REG_GPIO_PXFUNS(3) = 0x18000000; \ + REG_GPIO_PXSELS(3) = 0x18000000; \ + REG_GPIO_PXPES(3) = 0x18000000; \ +} while (0) + +/* + * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 + */ +#define __gpio_as_nor_16bit() \ +do { \ + REG_GPIO_PXFUNS(0) = 0x0000ffff; \ + REG_GPIO_PXSELC(0) = 0x0000ffff; \ + REG_GPIO_PXPES(0) = 0x0000ffff; \ + REG_GPIO_PXFUNS(1) = 0x7041ffff; \ + REG_GPIO_PXSELC(1) = 0x7041ffff; \ + REG_GPIO_PXPES(1) = 0x7041ffff; \ + REG_GPIO_PXFUNS(1) = 0x00060000; \ + REG_GPIO_PXSELS(1) = 0x00060000; \ + REG_GPIO_PXPES(1) = 0x00060000; \ + REG_GPIO_PXFUNS(2) = 0x08000000; \ + REG_GPIO_PXSELC(2) = 0x08000000; \ + REG_GPIO_PXPES(2) = 0x08000000; \ + REG_GPIO_PXFUNS(2) = 0x00c00000; \ + REG_GPIO_PXSELS(2) = 0x00c00000; \ + REG_GPIO_PXPES(2) = 0x00c00000; \ + REG_GPIO_PXFUNS(3) = 0x18000000; \ + REG_GPIO_PXSELS(3) = 0x18000000; \ + REG_GPIO_PXPES(3) = 0x18000000; \ +} while (0) + +/* + * UART0_TxD, UART_RxD0 + */ +#define __gpio_as_uart0() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x06000000; \ + REG_GPIO_PXSELS(3) = 0x06000000; \ + REG_GPIO_PXPES(3) = 0x06000000; \ +} while (0) + +/* + * UART1_TxD, UART1_RxD1 + */ +#define __gpio_as_uart1() \ +do { \ + REG_GPIO_PXFUNS(3) = 0xc0000000; \ + REG_GPIO_PXSELS(3) = 0xc0000000; \ + REG_GPIO_PXPES(3) = 0xc0000000; \ +} while (0) + +/* + * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE + */ +#define __gpio_as_lcd_16bit() \ +do { \ + REG_GPIO_PXFUNS(2) = 0x003cffff; \ + REG_GPIO_PXSELC(2) = 0x003cffff; \ + REG_GPIO_PXPES(2) = 0x003cffff; \ +} while (0) + +/* + * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE + */ +#define __gpio_as_lcd_18bit() \ +do { \ + REG_GPIO_PXFUNS(2) = 0x003fffff; \ + REG_GPIO_PXSELC(2) = 0x003fffff; \ + REG_GPIO_PXPES(2) = 0x003fffff; \ +} while (0) + + +/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ +#define __gpio_as_slcd_8bit() \ +do { \ + REG_GPIO_PXFUNS(2) = 0x001800ff; \ + REG_GPIO_PXSELC(2) = 0x001800ff; \ +} while (0) + +/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ +#define __gpio_as_slcd_9bit() \ +do { \ + REG_GPIO_PXFUNS(2) = 0x001801ff; \ + REG_GPIO_PXSELC(2) = 0x001801ff; \ +} while (0) + +/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ +#define __gpio_as_slcd_16bit() \ +do { \ + REG_GPIO_PXFUNS(2) = 0x0018ffff; \ + REG_GPIO_PXSELC(2) = 0x0018ffff; \ +} while (0) + +/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ +#define __gpio_as_slcd_18bit() \ +do { \ + REG_GPIO_PXFUNS(2) = 0x001bffff; \ + REG_GPIO_PXSELC(2) = 0x001bffff; \ +} while (0) + +/* + * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC + */ +#define __gpio_as_cim() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ + REG_GPIO_PXSELC(3) = 0x0003c0ff; \ + REG_GPIO_PXPES(3) = 0x0003c0ff; \ +} while (0) + +/* + * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET + */ +#define __gpio_as_aic() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x007c0000; \ + REG_GPIO_PXSELS(3) = 0x007c0000; \ + REG_GPIO_PXPES(3) = 0x007c0000; \ +} while (0) + +/* + * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 + */ +#define __gpio_as_msc() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x00003f00; \ + REG_GPIO_PXSELC(3) = 0x00003f00; \ + REG_GPIO_PXPES(3) = 0x00003f00; \ +} while (0) + +/* + * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR + */ +#define __gpio_as_ssi() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x003c0000; \ + REG_GPIO_PXSELC(3) = 0x003c0000; \ + REG_GPIO_PXPES(3) = 0x003c0000; \ +} while (0) + +/* + * I2C_SCK, I2C_SDA + */ +#define __gpio_as_i2c() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x01800000; \ + REG_GPIO_PXSELS(3) = 0x01800000; \ + REG_GPIO_PXPES(3) = 0x01800000; \ +} while (0) + +/* + * PWM0 + */ +#define __gpio_as_pwm0() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x00800000; \ + REG_GPIO_PXSELC(3) = 0x00800000; \ + REG_GPIO_PXPES(3) = 0x00800000; \ +} while (0) + +/* + * PWM1 + */ +#define __gpio_as_pwm1() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x01000000; \ + REG_GPIO_PXSELC(3) = 0x01000000; \ + REG_GPIO_PXPES(3) = 0x01000000; \ +} while (0) + +/* + * PWM2 + */ +#define __gpio_as_pwm2() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x02000000; \ + REG_GPIO_PXSELC(3) = 0x02000000; \ + REG_GPIO_PXPES(3) = 0x02000000; \ +} while (0) + +/* + * PWM3 + */ +#define __gpio_as_pwm3() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x04000000; \ + REG_GPIO_PXSELC(3) = 0x04000000; \ + REG_GPIO_PXPES(3) = 0x04000000; \ +} while (0) + +/* + * PWM4 + */ +#define __gpio_as_pwm4() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x08000000; \ + REG_GPIO_PXSELC(3) = 0x08000000; \ + REG_GPIO_PXPES(3) = 0x08000000; \ +} while (0) + +/* + * PWM5 + */ +#define __gpio_as_pwm5() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x10000000; \ + REG_GPIO_PXSELC(3) = 0x10000000; \ + REG_GPIO_PXPES(3) = 0x10000000; \ +} while (0) + +/* + * PWM6 + */ +#define __gpio_as_pwm6() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x40000000; \ + REG_GPIO_PXSELC(3) = 0x40000000; \ + REG_GPIO_PXPES(3) = 0x40000000; \ +} while (0) + +/* + * PWM7 + */ +#define __gpio_as_pwm7() \ +do { \ + REG_GPIO_PXFUNS(3) = 0x80000000; \ + REG_GPIO_PXSELC(3) = 0x80000000; \ + REG_GPIO_PXPES(3) = 0x80000000; \ +} while (0) + +/* + * n = 0 ~ 7 + */ +#define ___gpio_as_pwm(n) __gpio_as_pwm ## n() +#define __gpio_as_pwm(n) ___gpio_as_pwm(n) + +//------------------------------------------- +// GPIO or Interrupt Mode + +#define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) + +#define __gpio_port_as_output(p, o) \ +do { \ + REG_GPIO_PXFUNC(p) = (1 << (o)); \ + REG_GPIO_PXSELC(p) = (1 << (o)); \ + REG_GPIO_PXDIRS(p) = (1 << (o)); \ +} while (0) + +#define __gpio_port_as_input(p, o) \ +do { \ + REG_GPIO_PXFUNC(p) = (1 << (o)); \ + REG_GPIO_PXSELC(p) = (1 << (o)); \ + REG_GPIO_PXDIRC(p) = (1 << (o)); \ +} while (0) + +#define __gpio_as_output(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + __gpio_port_as_output(p, o); \ +} while (0) + +#define __gpio_as_input(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + __gpio_port_as_input(p, o); \ +} while (0) + +#define __gpio_set_pin(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXDATS(p) = (1 << o); \ +} while (0) + +#define __gpio_clear_pin(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXDATC(p) = (1 << o); \ +} while (0) + +#define __gpio_get_pin(n) \ +({ \ + unsigned int p, o, v; \ + p = (n) / 32; \ + o = (n) % 32; \ + if (__gpio_get_port(p) & (1 << o)) \ + v = 1; \ + else \ + v = 0; \ + v; \ +}) + +#define __gpio_as_irq_high_level(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXIMS(p) = (1 << o); \ + REG_GPIO_PXTRGC(p) = (1 << o); \ + REG_GPIO_PXFUNC(p) = (1 << o); \ + REG_GPIO_PXSELS(p) = (1 << o); \ + REG_GPIO_PXDIRS(p) = (1 << o); \ + REG_GPIO_PXFLGC(p) = (1 << o); \ + REG_GPIO_PXIMC(p) = (1 << o); \ +} while (0) + +#define __gpio_as_irq_low_level(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXIMS(p) = (1 << o); \ + REG_GPIO_PXTRGC(p) = (1 << o); \ + REG_GPIO_PXFUNC(p) = (1 << o); \ + REG_GPIO_PXSELS(p) = (1 << o); \ + REG_GPIO_PXDIRC(p) = (1 << o); \ + REG_GPIO_PXFLGC(p) = (1 << o); \ + REG_GPIO_PXIMC(p) = (1 << o); \ +} while (0) + +#define __gpio_as_irq_rise_edge(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXIMS(p) = (1 << o); \ + REG_GPIO_PXTRGS(p) = (1 << o); \ + REG_GPIO_PXFUNC(p) = (1 << o); \ + REG_GPIO_PXSELS(p) = (1 << o); \ + REG_GPIO_PXDIRS(p) = (1 << o); \ + REG_GPIO_PXFLGC(p) = (1 << o); \ + REG_GPIO_PXIMC(p) = (1 << o); \ +} while (0) + +#define __gpio_as_irq_fall_edge(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXIMS(p) = (1 << o); \ + REG_GPIO_PXTRGS(p) = (1 << o); \ + REG_GPIO_PXFUNC(p) = (1 << o); \ + REG_GPIO_PXSELS(p) = (1 << o); \ + REG_GPIO_PXDIRC(p) = (1 << o); \ + REG_GPIO_PXFLGC(p) = (1 << o); \ + REG_GPIO_PXIMC(p) = (1 << o); \ +} while (0) + +#define __gpio_mask_irq(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXIMS(p) = (1 << o); \ +} while (0) + +#define __gpio_unmask_irq(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXIMC(p) = (1 << o); \ +} while (0) + +#define __gpio_ack_irq(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXFLGC(p) = (1 << o); \ +} while (0) + +#define __gpio_get_irq() \ +({ \ + unsigned int p, i, tmp, v = 0; \ + for (p = 3; p >= 0; p--) { \ + tmp = REG_GPIO_PXFLG(p); \ + for (i = 0; i < 32; i++) \ + if (tmp & (1 << i)) \ + v = (32*p + i); \ + } \ + v; \ +}) + +#define __gpio_group_irq(n) \ +({ \ + register int tmp, i; \ + tmp = REG_GPIO_PXFLG((n)); \ + for (i=31;i>=0;i--) \ + if (tmp & (1 << i)) \ + break; \ + i; \ +}) + +#define __gpio_enable_pull(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXPEC(p) = (1 << o); \ +} while (0) + +#define __gpio_disable_pull(n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + REG_GPIO_PXPES(p) = (1 << o); \ +} while (0) + + +/*************************************************************************** + * CPM + ***************************************************************************/ +#define __cpm_get_pllm() \ + ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) +#define __cpm_get_plln() \ + ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) +#define __cpm_get_pllod() \ + ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) + +#define __cpm_get_cdiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) +#define __cpm_get_hdiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) +#define __cpm_get_pdiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) +#define __cpm_get_mdiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) +#define __cpm_get_ldiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) +#define __cpm_get_udiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) +#define __cpm_get_i2sdiv() \ + ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) +#define __cpm_get_pixdiv() \ + ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) +#define __cpm_get_mscdiv() \ + ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) + +#define __cpm_set_cdiv(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) +#define __cpm_set_hdiv(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) +#define __cpm_set_pdiv(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) +#define __cpm_set_mdiv(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) +#define __cpm_set_ldiv(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) +#define __cpm_set_udiv(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) +#define __cpm_set_i2sdiv(v) \ + (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) +#define __cpm_set_pixdiv(v) \ + (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) +#define __cpm_set_mscdiv(v) \ + (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) + +#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) +#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) +#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) +#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) +#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) +#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) +#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) +#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) + +#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) +#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) +#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) + +#define __cpm_get_cclk_doze_duty() \ + ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) +#define __cpm_set_cclk_doze_duty(v) \ + (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) + +#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) +#define __cpm_idle_mode() \ + (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) +#define __cpm_sleep_mode() \ + (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) + +#define __cpm_stop_all() (REG_CPM_CLKGR = 0xffff) +#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) +#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) +#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) +#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) +#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) +#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) +#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) +#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) +#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) +#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) +#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) +#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) +#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) +#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) +#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) +#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) + +#define __cpm_start_all() (REG_CPM_CLKGR = 0x0) +#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) +#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) +#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) +#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) +#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) +#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) +#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) +#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) +#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) +#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) +#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) +#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) +#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) +#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) +#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) +#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) + +#define __cpm_get_o1st() \ + ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) +#define __cpm_set_o1st(v) \ + (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) +#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) +#define __cpm_suspend_usbhost() (REG_CPM_SCR |= CPM_SCR_USBHOST_SUSPEND) +#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) + +#ifdef CFG_EXTAL +#define JZ_EXTAL CFG_EXTAL +#else +#define JZ_EXTAL 3686400 +#warning Default EXTCLK is used! +#endif +#define JZ_EXTAL2 32768 /* RTC clock */ + +/* PLL output frequency */ +static __inline__ unsigned int __cpm_get_pllout(void) +{ + unsigned long m, n, no, pllout; + unsigned long cppcr = REG_CPM_CPPCR; + unsigned long od[4] = {1, 2, 2, 4}; + + if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) + { + m = __cpm_get_pllm() + 2; + n = __cpm_get_plln() + 2; + no = od[__cpm_get_pllod()]; + pllout = ((JZ_EXTAL) / (n * no)) * m; + } + else + pllout = JZ_EXTAL; + + return pllout; +} + +/* PLL output frequency for MSC/I2S/LCD/USB */ +static __inline__ unsigned int __cpm_get_pllout2(void) +{ + if (REG_CPM_CPCCR & CPM_CPCCR_PCS) + return __cpm_get_pllout(); + else + return __cpm_get_pllout()/2; +} + +/* CPU core clock */ +static __inline__ unsigned int __cpm_get_cclk(void) +{ + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + return __cpm_get_pllout() / div[__cpm_get_cdiv()]; +} + +/* AHB system bus clock */ +static __inline__ unsigned int __cpm_get_hclk(void) +{ + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + return __cpm_get_pllout() / div[__cpm_get_hdiv()]; +} + +/* Memory bus clock */ +static __inline__ unsigned int __cpm_get_mclk(void) +{ + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + return __cpm_get_pllout() / div[__cpm_get_mdiv()]; +} + +/* APB peripheral bus clock */ +static __inline__ unsigned int __cpm_get_pclk(void) +{ + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + return __cpm_get_pllout() / div[__cpm_get_pdiv()]; +} + +/* LCDC module clock */ +static __inline__ unsigned int __cpm_get_lcdclk(void) +{ + return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); +} + +/* LCD pixel clock */ +static __inline__ unsigned int __cpm_get_pixclk(void) +{ + return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); +} + +/* I2S clock */ +static __inline__ unsigned int __cpm_get_i2sclk(void) +{ + if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) + return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); + else + return JZ_EXTAL; +} + +/* USB clock */ +static __inline__ unsigned int __cpm_get_usbclk(void) +{ + if (REG_CPM_CPCCR & CPM_CPCCR_UCS) + return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); + else + return JZ_EXTAL; +} + +/* MSC clock */ +static __inline__ unsigned int __cpm_get_mscclk(void) +{ + return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); +} + +/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ +static __inline__ unsigned int __cpm_get_extalclk(void) +{ + return JZ_EXTAL; +} + +/* RTC clock for CPM,INTC,RTC,TCU,WDT */ +static __inline__ unsigned int __cpm_get_rtcclk(void) +{ + return JZ_EXTAL2; +} + +/* + * Output 24MHz for SD and 16MHz for MMC. + */ +static __inline__ void __cpm_select_msc_clk(int sd) +{ + unsigned int pllout2 = __cpm_get_pllout2(); + unsigned int div = 0; + + if (sd) + div = pllout2 / 24000000; + else + div = pllout2 / 16000000; + + REG_CPM_MSCCDR = div - 1; +} + +/* + * Output 48MHz for SD and 16MHz for MMC. + */ +static __inline__ void __cpm_select_msc_hs_clk(int sd) +{ + unsigned int pllout2 = __cpm_get_pllout2(); + unsigned int div = 0; + + if (sd) + div = pllout2 / 48000000; + else + div = pllout2 / 16000000; + + REG_CPM_MSCCDR = div - 1; +} + +/*************************************************************************** + * TCU + ***************************************************************************/ +// where 'n' is the TCU channel +#define __tcu_select_extalclk(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) +#define __tcu_select_rtcclk(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) +#define __tcu_select_pclk(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) + +#define __tcu_select_clk_div1(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) +#define __tcu_select_clk_div4(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) +#define __tcu_select_clk_div16(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) +#define __tcu_select_clk_div64(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) +#define __tcu_select_clk_div256(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) +#define __tcu_select_clk_div1024(n) \ + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) + +#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) +#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) + +#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) +#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) + +#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) +#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) + +#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) +#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) + +#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) +#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) +#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) +#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) +#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) +#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) +#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) +#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) +#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) +#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) + +#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) +#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) + +#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) +#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) + +#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) +#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) + +#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) +#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) +#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) +#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) + + +/*************************************************************************** + * WDT + ***************************************************************************/ +#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) +#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) +#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) +#define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) + +#define __wdt_select_extalclk() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) +#define __wdt_select_rtcclk() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) +#define __wdt_select_pclk() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) + +#define __wdt_select_clk_div1() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) +#define __wdt_select_clk_div4() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) +#define __wdt_select_clk_div16() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) +#define __wdt_select_clk_div64() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) +#define __wdt_select_clk_div256() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) +#define __wdt_select_clk_div1024() \ + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) + + +/*************************************************************************** + * UART + ***************************************************************************/ + +#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) +#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) + +#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) +#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) + +#define __uart_enable_receive_irq() \ + ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) +#define __uart_disable_receive_irq() \ + ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) + +#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) +#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) + +#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) + +#define __uart_set_baud(devclk, baud) \ + do { \ + REG8(UART0_LCR) |= UARTLCR_DLAB; \ + REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ + REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ + REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ + } while (0) + +#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) +#define __uart_clear_errors() \ + ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) + +#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) +#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) +#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) +#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) +#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) +#define __uart_receive_char() REG8(UART0_RDR) +#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) +#define __uart_enable_irda() \ + /* Tx high pulse as 0, Rx low pulse as 0 */ \ + ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) + + +/*************************************************************************** + * DMAC + ***************************************************************************/ + +/* n is the DMA channel (0 - 5) */ + +#define __dmac_enable_module() \ + ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) +#define __dmac_disable_module() \ + ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) + +/* p=0,1,2,3 */ +#define __dmac_set_priority(p) \ +do { \ + REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ + REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ +} while (0) + +#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) +#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) + +#define __dmac_enable_descriptor(n) \ + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) +#define __dmac_disable_descriptor(n) \ + ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) + +#define __dmac_enable_channel(n) \ + ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) +#define __dmac_disable_channel(n) \ + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) +#define __dmac_channel_enabled(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) + +#define __dmac_channel_enable_irq(n) \ + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) +#define __dmac_channel_disable_irq(n) \ + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) + +#define __dmac_channel_transmit_halt_detected(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) +#define __dmac_channel_transmit_end_detected(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) +#define __dmac_channel_address_error_detected(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) +#define __dmac_channel_count_terminated_detected(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) +#define __dmac_channel_descriptor_invalid_detected(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) + +#define __dmac_channel_clear_transmit_halt(n) \ + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) +#define __dmac_channel_clear_transmit_end(n) \ + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) +#define __dmac_channel_clear_address_error(n) \ + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) +#define __dmac_channel_clear_count_terminated(n) \ + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) +#define __dmac_channel_clear_descriptor_invalid(n) \ + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) + +#define __dmac_channel_set_single_mode(n) \ + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) +#define __dmac_channel_set_block_mode(n) \ + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) + +#define __dmac_channel_set_transfer_unit_32bit(n) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ +} while (0) + +#define __dmac_channel_set_transfer_unit_16bit(n) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ +} while (0) + +#define __dmac_channel_set_transfer_unit_8bit(n) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ +} while (0) + +#define __dmac_channel_set_transfer_unit_16byte(n) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ +} while (0) + +#define __dmac_channel_set_transfer_unit_32byte(n) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ +} while (0) + +/* w=8,16,32 */ +#define __dmac_channel_set_dest_port_width(n,w) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ +} while (0) + +/* w=8,16,32 */ +#define __dmac_channel_set_src_port_width(n,w) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ + REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ +} while (0) + +/* v=0-15 */ +#define __dmac_channel_set_rdil(n,v) \ +do { \ + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ + REG_DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT); \ +} while (0) + +#define __dmac_channel_dest_addr_fixed(n) \ + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) +#define __dmac_channel_dest_addr_increment(n) \ + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) + +#define __dmac_channel_src_addr_fixed(n) \ + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) +#define __dmac_channel_src_addr_increment(n) \ + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) + +#define __dmac_channel_set_doorbell(n) \ + ( REG_DMAC_DMADBSR = (1 << (n)) ) + +#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) +#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) + +static __inline__ int __dmac_get_irq(void) +{ + int i; + for (i = 0; i < MAX_DMA_NUM; i++) + if (__dmac_channel_irq_detected(i)) + return i; + return -1; +} + + +/*************************************************************************** + * AIC (AC'97 & I2S Controller) + ***************************************************************************/ + +#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) +#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) + +#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) +#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) + +#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) +#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) +#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) + +#define __aic_reset() \ +do { \ + REG_AIC_FR |= AIC_FR_RST; \ +} while(0) + + +#define __aic_set_transmit_trigger(n) \ +do { \ + REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ + REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ +} while(0) + +#define __aic_set_receive_trigger(n) \ +do { \ + REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ + REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ +} while(0) + +#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) +#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) +#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) +#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) +#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) +#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) + +#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) +#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) + +#define __aic_enable_transmit_intr() \ + ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) +#define __aic_disable_transmit_intr() \ + ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) +#define __aic_enable_receive_intr() \ + ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) +#define __aic_disable_receive_intr() \ + ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) + +#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) +#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) +#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) +#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) + +#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) +#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) +#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) +#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) +#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) +#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) + +#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 +#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 +#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 +#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 +#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 +#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 + +#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 +#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 +#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 +#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 +#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 +#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 + +#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) +#define __ac97_set_xs_mono() \ +do { \ + REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ + REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ +} while(0) +#define __ac97_set_xs_stereo() \ +do { \ + REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ + REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ +} while(0) + +/* In fact, only stereo is support now. */ +#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) +#define __ac97_set_rs_mono() \ +do { \ + REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ + REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ +} while(0) +#define __ac97_set_rs_stereo() \ +do { \ + REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ + REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ +} while(0) + +#define __ac97_warm_reset_codec() \ + do { \ + REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ + REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ + udelay(2); \ + REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ + REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ + } while (0) + +#define __ac97_cold_reset_codec() \ + do { \ + REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ + udelay(2); \ + REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ + } while (0) + +/* n=8,16,18,20 */ +#define __ac97_set_iass(n) \ + ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) +#define __ac97_set_oass(n) \ + ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) + +#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) +#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) + +/* n=8,16,18,20,24 */ +/*#define __i2s_set_sample_size(n) \ + ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ + +#define __i2s_set_oss_sample_size(n) \ + ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) +#define __i2s_set_iss_sample_size(n) \ + ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) + +#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) +#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) + +#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) +#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) +#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) +#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) + +#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) + +#define __aic_get_transmit_resident() \ + ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) +#define __aic_get_receive_count() \ + ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) + +#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) +#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) +#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) +#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) +#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) +#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) +#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) + +#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) + +#define CODEC_READ_CMD (1 << 19) +#define CODEC_WRITE_CMD (0 << 19) +#define CODEC_REG_INDEX_BIT 12 +#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ +#define CODEC_REG_DATA_BIT 4 +#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ + +#define __ac97_out_rcmd_addr(reg) \ +do { \ + REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ +} while (0) + +#define __ac97_out_wcmd_addr(reg) \ +do { \ + REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ +} while (0) + +#define __ac97_out_data(value) \ +do { \ + REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ +} while (0) + +#define __ac97_in_data() \ + ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) + +#define __ac97_in_status_addr() \ + ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) + +#define __i2s_set_sample_rate(i2sclk, sync) \ + ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) + +#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) +#define __aic_read_rfifo() ( REG_AIC_DR ) + +#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) +#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) + +#define AIC_FR_LSMP (1 << 6) +#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) +// +// Define next ops for AC97 compatible +// + +#define AC97_ACSR AIC_ACSR + +#define __ac97_enable() __aic_enable(); __aic_select_ac97() +#define __ac97_disable() __aic_disable() +#define __ac97_reset() __aic_reset() + +#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) +#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) + +#define __ac97_enable_record() __aic_enable_record() +#define __ac97_disable_record() __aic_disable_record() +#define __ac97_enable_replay() __aic_enable_replay() +#define __ac97_disable_replay() __aic_disable_replay() +#define __ac97_enable_loopback() __aic_enable_loopback() +#define __ac97_disable_loopback() __aic_disable_loopback() + +#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() +#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() +#define __ac97_enable_receive_dma() __aic_enable_receive_dma() +#define __ac97_disable_receive_dma() __aic_disable_receive_dma() + +#define __ac97_transmit_request() __aic_transmit_request() +#define __ac97_receive_request() __aic_receive_request() +#define __ac97_transmit_underrun() __aic_transmit_underrun() +#define __ac97_receive_overrun() __aic_receive_overrun() + +#define __ac97_clear_errors() __aic_clear_errors() + +#define __ac97_get_transmit_resident() __aic_get_transmit_resident() +#define __ac97_get_receive_count() __aic_get_receive_count() + +#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() +#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() +#define __ac97_enable_receive_intr() __aic_enable_receive_intr() +#define __ac97_disable_receive_intr() __aic_disable_receive_intr() + +#define __ac97_write_tfifo(v) __aic_write_tfifo(v) +#define __ac97_read_rfifo() __aic_read_rfifo() + +// +// Define next ops for I2S compatible +// + +#define I2S_ACSR AIC_I2SSR + +#define __i2s_enable() __aic_enable(); __aic_select_i2s() +#define __i2s_disable() __aic_disable() +#define __i2s_reset() __aic_reset() + +#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) +#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) + +#define __i2s_enable_record() __aic_enable_record() +#define __i2s_disable_record() __aic_disable_record() +#define __i2s_enable_replay() __aic_enable_replay() +#define __i2s_disable_replay() __aic_disable_replay() +#define __i2s_enable_loopback() __aic_enable_loopback() +#define __i2s_disable_loopback() __aic_disable_loopback() + +#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() +#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() +#define __i2s_enable_receive_dma() __aic_enable_receive_dma() +#define __i2s_disable_receive_dma() __aic_disable_receive_dma() + +#define __i2s_transmit_request() __aic_transmit_request() +#define __i2s_receive_request() __aic_receive_request() +#define __i2s_transmit_underrun() __aic_transmit_underrun() +#define __i2s_receive_overrun() __aic_receive_overrun() + +#define __i2s_clear_errors() __aic_clear_errors() + +#define __i2s_get_transmit_resident() __aic_get_transmit_resident() +#define __i2s_get_receive_count() __aic_get_receive_count() + +#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() +#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() +#define __i2s_enable_receive_intr() __aic_enable_receive_intr() +#define __i2s_disable_receive_intr() __aic_disable_receive_intr() + +#define __i2s_write_tfifo(v) __aic_write_tfifo(v) +#define __i2s_read_rfifo() __aic_read_rfifo() + +#define __i2s_reset_codec() \ + do { \ + } while (0) + + +/*************************************************************************** + * ICDC + ***************************************************************************/ +#define __i2s_internal_codec() __aic_internal_codec() +#define __i2s_external_codec() __aic_external_codec() + +/*************************************************************************** + * INTC + ***************************************************************************/ +#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) +#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) +#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) + + +/*************************************************************************** + * I2C + ***************************************************************************/ + +#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) +#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) + +#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) +#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) +#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) +#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) + +#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) +#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) +#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) + +#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) +#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) +#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) + +#define __i2c_set_clk(dev_clk, i2c_clk) \ + ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) + +#define __i2c_read() ( REG_I2C_DR ) +#define __i2c_write(val) ( REG_I2C_DR = (val) ) + + +/*************************************************************************** + * MSC + ***************************************************************************/ + +#define __msc_start_op() \ + ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) + +#define __msc_set_resto(to) ( REG_MSC_RESTO = to ) +#define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) +#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) +#define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) +#define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) +#define __msc_get_nob() ( REG_MSC_NOB ) +#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) +#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) +#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) +#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) + +#define __msc_set_cmdat_bus_width1() \ +do { \ + REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ + REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ +} while(0) + +#define __msc_set_cmdat_bus_width4() \ +do { \ + REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ + REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ +} while(0) + +#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) +#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) +#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) +#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) +#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) +#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) +#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) +#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) + +/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ +#define __msc_set_cmdat_res_format(r) \ +do { \ + REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ + REG_MSC_CMDAT |= (r); \ +} while(0) + +#define __msc_clear_cmdat() \ + REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ + MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ + MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) + +#define __msc_get_imask() ( REG_MSC_IMASK ) +#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) +#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) +#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) +#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) +#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) +#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) +#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) +#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) +#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) +#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) +#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) +#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) + +/* n=0,1,2,3,4,5,6,7 */ +#define __msc_set_clkrt(n) \ +do { \ + REG_MSC_CLKRT = n; \ +} while(0) + +#define __msc_get_ireg() ( REG_MSC_IREG ) +#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) +#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) +#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) +#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) +#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) +#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) +#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) +#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) + +#define __msc_get_stat() ( REG_MSC_STAT ) +#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) +#define __msc_stat_crc_err() \ + ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) +#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) +#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) +#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) +#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) +#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) + +#define __msc_rd_resfifo() ( REG_MSC_RES ) +#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) +#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) + +#define __msc_reset() \ +do { \ + REG_MSC_STRPCL = MSC_STRPCL_RESET; \ + while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ +} while (0) + +#define __msc_start_clk() \ +do { \ + REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ +} while (0) + +#define __msc_stop_clk() \ +do { \ + REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ +} while (0) + +#define MMC_CLK 19169200 +#define SD_CLK 24576000 + +/* msc_clk should little than pclk and little than clk retrieve from card */ +#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ +do { \ + unsigned int rate, pclk, i; \ + pclk = dev_clk; \ + rate = type?SD_CLK:MMC_CLK; \ + if (msc_clk && msc_clk < pclk) \ + pclk = msc_clk; \ + i = 0; \ + while (pclk < rate) \ + { \ + i ++; \ + rate >>= 1; \ + } \ + lv = i; \ +} while(0) + +/* divide rate to little than or equal to 400kHz */ +#define __msc_calc_slow_clk_divisor(type, lv) \ +do { \ + unsigned int rate, i; \ + rate = (type?SD_CLK:MMC_CLK)/1000/400; \ + i = 0; \ + while (rate > 0) \ + { \ + rate >>= 1; \ + i ++; \ + } \ + lv = i; \ +} while(0) + + +/*************************************************************************** + * SSI + ***************************************************************************/ + +#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) +#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) +#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) + +#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) + +#define __ssi_select_ce2() \ +do { \ + REG_SSI_CR0 |= SSI_CR0_FSEL; \ + REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ +} while (0) + +#define __ssi_select_gpc() \ +do { \ + REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ + REG_SSI_CR1 |= SSI_CR1_MULTS; \ +} while (0) + +#define __ssi_enable_tx_intr() \ + ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) + +#define __ssi_disable_tx_intr() \ + ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) + +#define __ssi_enable_rx_intr() \ + ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) + +#define __ssi_disable_rx_intr() \ + ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) + +#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) +#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) + +#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) +#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) + +#define __ssi_finish_receive() \ + ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) + +#define __ssi_disable_recvfinish() \ + ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) + +#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) +#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) + +#define __ssi_flush_fifo() \ + ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) + +#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) + +#define __ssi_spi_format() \ +do { \ + REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ + REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ + REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ + REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ +} while (0) + +/* TI's SSP format, must clear SSI_CR1.UNFIN */ +#define __ssi_ssp_format() \ +do { \ + REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ + REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ +} while (0) + +/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ +#define __ssi_microwire_format() \ +do { \ + REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ + REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ + REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ + REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ + REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ +} while (0) + +/* CE# level (FRMHL), CE# in interval time (ITFRM), + clock phase and polarity (PHA POL), + interval time (SSIITR), interval characters/frame (SSIICR) */ + + /* frmhl,endian,mcom,flen,pha,pol MASK */ +#define SSICR1_MISC_MASK \ + ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ + | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ + +#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ +do { \ + REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ + REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ + (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ + ((pha) << 1) | (pol); \ +} while(0) + +/* Transfer with MSB or LSB first */ +#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) +#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) + +#define __ssi_set_frame_length(n) \ + REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) + +/* n = 1 - 16 */ +#define __ssi_set_microwire_command_length(n) \ + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) + +/* Set the clock phase for SPI */ +#define __ssi_set_spi_clock_phase(n) \ + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) + +/* Set the clock polarity for SPI */ +#define __ssi_set_spi_clock_polarity(n) \ + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) + +/* n = ix8 */ +#define __ssi_set_tx_trigger(n) \ +do { \ + REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ + REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ +} while (0) + +/* n = ix8 */ +#define __ssi_set_rx_trigger(n) \ +do { \ + REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ + REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ +} while (0) + +#define __ssi_get_txfifo_count() \ + ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) + +#define __ssi_get_rxfifo_count() \ + ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) + +#define __ssi_clear_errors() \ + ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) + +#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) +#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) + +#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) +#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) +#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) + +#define __ssi_set_clk(dev_clk, ssi_clk) \ + ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) + +#define __ssi_receive_data() REG_SSI_DR +#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) + + +/*************************************************************************** + * CIM + ***************************************************************************/ + +#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) +#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) + +#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) +#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) + +#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) +#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) + +#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) +#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) + +#define __cim_sample_data_at_pclk_falling_edge() \ + ( REG_CIM_CFG |= CIM_CFG_PCP ) +#define __cim_sample_data_at_pclk_rising_edge() \ + ( REG_CIM_CFG &= ~CIM_CFG_PCP ) + +#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) +#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) + +#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) +#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) + +/* n=0-7 */ +#define __cim_set_data_packing_mode(n) \ +do { \ + REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ + REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ +} while (0) + +#define __cim_enable_ccir656_progressive_mode() \ +do { \ + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ + REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ +} while (0) + +#define __cim_enable_ccir656_interlace_mode() \ +do { \ + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ + REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ +} while (0) + +#define __cim_enable_gated_clock_mode() \ +do { \ + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ + REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ +} while (0) + +#define __cim_enable_nongated_clock_mode() \ +do { \ + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ + REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ +} while (0) + +/* sclk:system bus clock + * mclk: CIM master clock + */ +#define __cim_set_master_clk(sclk, mclk) \ +do { \ + REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ + REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ +} while (0) + +#define __cim_enable_sof_intr() \ + ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) +#define __cim_disable_sof_intr() \ + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) + +#define __cim_enable_eof_intr() \ + ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) +#define __cim_disable_eof_intr() \ + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) + +#define __cim_enable_stop_intr() \ + ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) +#define __cim_disable_stop_intr() \ + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) + +#define __cim_enable_trig_intr() \ + ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) +#define __cim_disable_trig_intr() \ + ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) + +#define __cim_enable_rxfifo_overflow_intr() \ + ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) +#define __cim_disable_rxfifo_overflow_intr() \ + ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) + +/* n=1-16 */ +#define __cim_set_frame_rate(n) \ +do { \ + REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ + REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ +} while (0) + +#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) +#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) + +#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) +#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) + +/* n=4,8,12,16,20,24,28,32 */ +#define __cim_set_rxfifo_trigger(n) \ +do { \ + REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ + REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ +} while (0) + +#define __cim_clear_state() ( REG_CIM_STATE = 0 ) + +#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) +#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) +#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) +#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) +#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) +#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) +#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) +#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) + +#define __cim_get_iid() ( REG_CIM_IID ) +#define __cim_get_image_data() ( REG_CIM_RXFIFO ) +#define __cim_get_dam_cmd() ( REG_CIM_CMD ) + +#define __cim_set_da(a) ( REG_CIM_DA = (a) ) + +/*************************************************************************** + * LCD + ***************************************************************************/ +#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<> LCD_VSYNC_VPS_BIT ) + +#define __lcd_vsync_get_vpe() \ + ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) +#define __lcd_vsync_set_vpe(n) \ +do { \ + REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ + REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ +} while (0) + +#define __lcd_hsync_get_hps() \ + ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) +#define __lcd_hsync_set_hps(n) \ +do { \ + REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ + REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ +} while (0) + +#define __lcd_hsync_get_hpe() \ + ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) +#define __lcd_hsync_set_hpe(n) \ +do { \ + REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ + REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ +} while (0) + +#define __lcd_vat_get_ht() \ + ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) +#define __lcd_vat_set_ht(n) \ +do { \ + REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ + REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ +} while (0) + +#define __lcd_vat_get_vt() \ + ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) +#define __lcd_vat_set_vt(n) \ +do { \ + REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ + REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ +} while (0) + +#define __lcd_dah_get_hds() \ + ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) +#define __lcd_dah_set_hds(n) \ +do { \ + REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ + REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ +} while (0) + +#define __lcd_dah_get_hde() \ + ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) +#define __lcd_dah_set_hde(n) \ +do { \ + REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ + REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ +} while (0) + +#define __lcd_dav_get_vds() \ + ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) +#define __lcd_dav_set_vds(n) \ +do { \ + REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ + REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ +} while (0) + +#define __lcd_dav_get_vde() \ + ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) +#define __lcd_dav_set_vde(n) \ +do { \ + REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ + REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ +} while (0) + +#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) +#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) +#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) +#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) + +#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) +#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) +#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) +#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) + +#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) +#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) + +#define __lcd_cmd0_get_len() \ + ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) +#define __lcd_cmd1_get_len() \ + ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) + +/*************************************************************************** + * RTC ops + ***************************************************************************/ + +#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) +#define __rtc_enabled() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR |= RTC_RCR_RTCE ; \ +}while(0) \ + +#define __rtc_disabled() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR &= ~RTC_RCR_RTCE; \ +}while(0) +#define __rtc_enable_alarm() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR |= RTC_RCR_AE; \ +}while(0) + +#define __rtc_disable_alarm() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR &= ~RTC_RCR_AE; \ +}while(0) + +#define __rtc_enable_alarm_irq() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR |= RTC_RCR_AIE; \ +}while(0) + +#define __rtc_disable_alarm_irq() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR &= ~RTC_RCR_AIE; \ +}while(0) +#define __rtc_enable_Hz_irq() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR |= RTC_RCR_HZIE; \ +}while(0) + +#define __rtc_disable_Hz_irq() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR &= ~RTC_RCR_HZIE; \ +}while(0) +#define __rtc_get_1Hz_flag() \ +do{ \ + while(!__rtc_write_ready()); \ + ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ +}while(0) +#define __rtc_clear_1Hz_flag() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR &= ~RTC_RCR_HZ; \ +}while(0) +#define __rtc_get_alarm_flag() \ +do{ \ + while(!__rtc_write_ready()); \ + ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1); \ +while(0) + +///( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 ) + +#define __rtc_clear_alarm_flag() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RCR &= ~RTC_RCR_AF; \ +}while(0) +//do +#define __rtc_get_second() \ +({ \ + while(!__rtc_write_ready());\ + REG_RTC_RSR; \ +}) +//while(0) + +#define __rtc_set_second(v) \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RSR = v; \ + while(!__rtc_write_ready());\ +}while(0) + +#define __rtc_get_alarm_second() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RSAR; \ +}while(0) + + +#define __rtc_set_alarm_second(v) \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RSAR = v; \ +}while(0) + +#define __rtc_RGR_is_locked() \ +({ \ + while(!__rtc_write_ready()); \ + REG_RTC_RGR >> RTC_RGR_LOCK; \ +}) +#define __rtc_lock_RGR() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RGR |= RTC_RGR_LOCK; \ +}while(0) + +#define __rtc_unlock_RGR() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RGR &= ~RTC_RGR_LOCK; \ +}while(0) + +#define __rtc_get_adjc_val() \ +do{ \ + while(!__rtc_write_ready()); \ + ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ +}while(0) +#define __rtc_set_adjc_val(v) \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_ADJC_MASK)) |(v << RTC_RGR_ADJC_BIT); \ +}while(0) + +#define __rtc_get_nc1Hz_val() \ + ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) + +#define __rtc_set_nc1Hz_val(v) \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_NC1HZ_MASK)) | (v << RTC_RGR_NC1HZ_BIT);\ +}while(0) +#define __rtc_power_down() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_HCR |= RTC_HCR_PD; \ +}while(0) + +#define __rtc_get_hwfcr_val() \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_HWFCR & RTC_HWFCR_MASK; \ +}while(0) +#define __rtc_set_hwfcr_val(v) \ +do{ \ + while(!__rtc_write_ready()); \ + REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ +}while(0) + +#define __rtc_get_hrcr_val() \ +do{ \ + while(!__rtc_write_ready()); \ + ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ +}while(0) +#define __rtc_set_hrcr_val(v) \ +do{ \ + while(!__rtc_write_ready()); \ + ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ +}while(0) + +#define __rtc_enable_alarm_wakeup() \ +do{ \ + while(!__rtc_write_ready()); \ + ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ +}while(0) + +#define __rtc_disable_alarm_wakeup() \ +do{ \ + while(!__rtc_write_ready()); \ + ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ +}while(0) + +#define __rtc_status_hib_reset_occur() \ +({ \ + (REG_RTC_HWRSR & RTC_HWRSR_HR); \ +}) +#define __rtc_status_ppr_reset_occur() \ +do{ \ + while(!__rtc_write_ready()); \ + ( (REG_RTC_HWRSR & RTC_HWRSR_PPR) & 0x1 ); \ +}while(0) +#define __rtc_status_wakeup_pin_waken_up() \ +do{ \ + while(!__rtc_write_ready()); \ + ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ +}while(0) +#define __rtc_status_alarm_waken_up() \ +do{ \ + while(!__rtc_write_ready()); \ + ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ +}while(0) +#define __rtc_clear_hib_stat_all() \ +do{ \ + while(!__rtc_write_ready()); \ + ( REG_RTC_HWRSR = 0 ); \ +}while(0) + +#define __rtc_get_scratch_pattern() \ +({ while(!__rtc_write_ready()); \ + (REG_RTC_HSPR);}) +#define __rtc_set_scratch_pattern(n) \ +do{ \ + while(!__rtc_write_ready()); \ + (REG_RTC_HSPR = n ); \ +}while(0) + + +#endif /* !__ASSEMBLY__ */ + + +#ifndef _IPU_H_ +#define _IPU_H_ + +// IPU_REG_BASE +#define IPU_P_BASE 0x13080000 +#define IPU_V_BASE 0xB3080000 +#define IPU__SIZE 0x00001000 + +struct ipu_module +{ + unsigned int reg_ctrl; // 0x0 + unsigned int reg_status; // 0x4 + unsigned int reg_d_fmt; // 0x8 + unsigned int reg_y_addr; // 0xc + unsigned int reg_u_addr; // 0x10 + unsigned int reg_v_addr; // 0x14 + unsigned int reg_in_fm_gs; // 0x18 + unsigned int reg_y_stride; // 0x1c + unsigned int reg_uv_stride; // 0x20 + unsigned int reg_out_addr; // 0x24 + unsigned int reg_out_gs; // 0x28 + unsigned int reg_out_stride; // 0x2c + unsigned int rsz_coef_index; // 0x30 + unsigned int reg_csc_c0_coef; // 0x34 + unsigned int reg_csc_c1_coef; // 0x38 + unsigned int reg_csc_c2_coef; // 0x3c + unsigned int reg_csc_c3_coef; // 0x40 + unsigned int reg_csc_c4_coef; // 0x44 + unsigned int hrsz_coef_lut[20]; // 0x48 + unsigned int vrsz_coef_lut[20]; // 0x98 +}; + +typedef struct +{ + unsigned int coef; + unsigned short int in_n; + unsigned short int out_n; +} rsz_lut; + +struct Ration2m +{ + float ratio; + int n, m; +}; + + +// Register offset +#define REG_CTRL 0x0 +#define REG_STATUS 0x4 +#define REG_D_FMT 0x8 +#define REG_Y_ADDR 0xc +#define REG_U_ADDR 0x10 +#define REG_V_ADDR 0x14 +#define REG_IN_FM_GS 0x18 +#define REG_Y_STRIDE 0x1c +#define REG_UV_STRIDE 0x20 +#define REG_OUT_ADDR 0x24 +#define REG_OUT_GS 0x28 +#define REG_OUT_STRIDE 0x2c +#define REG_RSZ_COEF_INDEX 0x30 +#define REG_CSC_C0_COEF 0x34 +#define REG_CSC_C1_COEF 0x38 +#define REG_CSC_C2_COEF 0x3c +#define REG_CSC_C3_COEF 0x40 +#define REG_CSC_C4_COEF 0x44 +#define HRSZ_LUT_BASE 0x48 +#define VRSZ_LUT_BASE 0x98 + +// REG_CTRL field define +#define IPU_EN (1 << 0) +#define RSZ_EN (1 << 1) +#define FM_IRQ_EN (1 << 2) +#define IPU_RESET (1 << 3) +#define H_UP_SCALE (1 << 8) +#define V_UP_SCALE (1 << 9) +#define H_SCALE_SHIFT (8) +#define V_SCALE_SHIFT (9) + +// REG_STATUS field define +#define OUT_END (1 << 0) + +// REG_D_FMT field define +#define INFMT_YUV420 (0 << 0) +#define INFMT_YUV422 (1 << 0) +#define INFMT_YUV444 (2 << 0) +#define INFMT_YUV411 (3 << 0) +#define INFMT_YCbCr420 (4 << 0) +#define INFMT_YCbCr422 (5 << 0) +#define INFMT_YCbCr444 (6 << 0) +#define INFMT_YCbCr411 (7 << 0) +#define INFMT_MASK (7) + +#define OUTFMT_RGB555 (0 << 16) +#define OUTFMT_RGB565 (1 << 16) +#define OUTFMT_RGB888 (2 << 16) +#define OUTFMT_MASK (3 << 16) + +// REG_IN_FM_GS field define +#define IN_FM_W(val) ((val) << 16) +#define IN_FM_H(val) ((val) << 0) + +// REG_IN_FM_GS field define +#define OUT_FM_W(val) ((val) << 16) +#define OUT_FM_H(val) ((val) << 0) + +// REG_UV_STRIDE field define +#define U_STRIDE(val) ((val) << 16) +#define V_STRIDE(val) ((val) << 0) + +#define VE_IDX_SFT 0 +#define HE_IDX_SFT 16 + +// RSZ_LUT_FIELD +#define OUT_N_SFT 0 +#define OUT_N_MSK 0x1 +#define IN_N_SFT 1 +#define IN_N_MSK 0x1 +#define W_COEF_SFT 2 +#define W_COEF_MSK 0xFF + +// function about REG_CTRL +#define IPU_STOP_IPU() \ + REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; + +#define IPU_RUN_IPU() \ + REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; + +#define IPU_RESET_IPU() \ + REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; + +#define IPU_DISABLE_IRQ() \ + REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; + +#define IPU_ENABLE_IRQ() \ + REG32(IPU_V_BASE + REG_CTRL) |= FM_IRQ_EN; + +#define IPU_DISABLE_RSIZE() \ + REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; + +#define IPU_ENABLE_RSIZE() \ + REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; + +#define IPU_IS_ENABLED() \ + (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) + +// function about REG_STATUS +#define IPU_CLEAR_END_FLAG() \ + REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; + +#define IPU_POLLING_END_FLAG() \ + (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) + +#define IPU_SET_INFMT(fmt) \ + REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~INFMT_MASK) | (fmt); + +#define IPU_SET_OUTFMT(fmt) \ + REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~OUTFMT_MASK) | (fmt); + +#define IPU_SET_IN_FM(w, h) \ + REG32(IPU_V_BASE + REG_IN_FM_GS) = IN_FM_W(w) | IN_FM_H(h); + +#define IPU_SET_Y_STRIDE(stride) \ + REG32(IPU_V_BASE + REG_Y_STRIDE) = (stride); + +#define IPU_SET_UV_STRIDE(u, v) \ + REG32(IPU_V_BASE + REG_UV_STRIDE) = U_STRIDE(u) | V_STRIDE(v); + +#define IPU_SET_Y_ADDR(addr) \ + REG32(IPU_V_BASE + REG_Y_ADDR) = (addr); + +#define IPU_SET_U_ADDR(addr) \ + REG32(IPU_V_BASE + REG_U_ADDR) = (addr); + +#define IPU_SET_V_ADDR(addr) \ + REG32(IPU_V_BASE + REG_V_ADDR) = (addr); + +#define IPU_SET_OUT_ADDR(addr) \ + REG32(IPU_V_BASE + REG_OUT_ADDR) = (addr); + +#define IPU_SET_OUT_FM(w, h) \ + REG32(IPU_V_BASE + REG_OUT_GS) = OUT_FM_W(w) | OUT_FM_H(h); + +#define IPU_SET_OUT_STRIDE(stride) \ + REG32(IPU_V_BASE + REG_OUT_STRIDE) = (stride); + +#define IPU_SET_CSC_C0_COEF(coef) \ + REG32(IPU_V_BASE + REG_CSC_C0_COEF) = (coef); + +#define IPU_SET_CSC_C1_COEF(coef) \ + REG32(IPU_V_BASE + REG_CSC_C1_COEF) = (coef); + +#define IPU_SET_CSC_C2_COEF(coef) \ + REG32(IPU_V_BASE + REG_CSC_C2_COEF) = (coef); + +#define IPU_SET_CSC_C3_COEF(coef) \ + REG32(IPU_V_BASE + REG_CSC_C3_COEF) = (coef); + +#define IPU_SET_CSC_C4_COEF(coef) \ + REG32(IPU_V_BASE + REG_CSC_C4_COEF) = (coef); + +/* YCbCr */ +/* parameter + R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1} + G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3} + B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4} +*/ +#define YCBCR_CSC_C0 0x4A8 /* 1.164 * 1024 */ +#define YCBCR_CSC_C1 0x662 /* 1.596 * 1024 */ +#define YCBCR_CSC_C2 0x191 /* 0.392 * 1024 */ +#define YCBCR_CSC_C3 0x341 /* 0.813 * 1024 */ +#define YCBCR_CSC_C4 0x811 /* 2.017 * 1024 */ + + +/* YUV */ +/* parameter + R = 1 * (Y – 0) + 1.4026 * (V - 128) {C0, C1} + G = 1 * (Y – 0) – 0.3444 * (U - 128) – 0.7144 * (V - 128) {C0, C2, C3} + B = 1 * (Y – 0) + 1.7730 * (U - 128) {C0, C4} +*/ +#define YUV_CSC_C0 0x400 +#define YUV_CSC_C1 0x59C +#define YUV_CSC_C2 0x161 +#define YUV_CSC_C3 0x2DC +#define YUV_CSC_C4 0x718 + +#endif /* _IPU_H_ */ + +/* Rockbox USB defines */ +#define USB_NUM_ENDPOINTS 3 +#define USB_DEVBSS_ATTR IBSS_ATTR + +#endif /* __JZ4740_H__ */ diff --git a/src/linkapp.cpp b/src/linkapp.cpp index b076ec5..88d27e1 100644 --- a/src/linkapp.cpp +++ b/src/linkapp.cpp @@ -37,15 +37,11 @@ LinkApp::LinkApp(GMenu2X *gmenu2x, const char* linkfile) file = linkfile; wrapper = false; dontleave = false; -#ifdef TARGET_GP2X - setClock(200); -#endif -#ifdef TARGET_WIZ - setClock(550); -#endif + setClock(336); setVolume(-1); //G - setGamma(0); + //setGamma(0); + setBacklight(100); selectordir = ""; selectorfilter = ""; icon = iconPath = ""; @@ -85,6 +81,8 @@ LinkApp::LinkApp(GMenu2X *gmenu2x, const char* linkfile) //G } else if (name == "gamma") { setGamma( atoi(value.c_str()) ); + } else if (name == "backlight") { + setBacklight( atoi(value.c_str()) ); } else if (name == "volume") { setVolume( atoi(value.c_str()) ); } else if (name == "selectordir") { @@ -141,12 +139,7 @@ string LinkApp::clockStr(int maxClock) { } void LinkApp::setClock(int mhz) { -#ifdef TARGET_GP2X - iclock = constrain(mhz,50,325); -#endif -#ifdef TARGET_WIZ - iclock = constrain(mhz,50,900); -#endif + iclock = constrain(mhz,200,430); stringstream ss; sclock = ""; ss << iclock << "Mhz"; @@ -176,6 +169,26 @@ void LinkApp::setVolume(int vol) { edited = true; } +int LinkApp::backlight() +{ + return ibacklight; +} + +string LinkApp::backlightStr() +{ + return sbacklight; +} + +void LinkApp::setBacklight(int val) +{ + ibacklight = constrain(val,5,100); + stringstream ss; + sbacklight = ""; + ss << ibacklight; + ss >> sbacklight; + + edited = true; +} //G int LinkApp::gamma() { return igamma; @@ -197,7 +210,7 @@ void LinkApp::setGamma(int gamma) { // /G bool LinkApp::targetExists() { -#if !defined(TARGET_GP2X) && !defined(TARGET_WIZ) +#ifndef TARGET_GP2X return true; //For displaying elements during testing on pc #endif @@ -225,6 +238,7 @@ bool LinkApp::save() { if (ivolume>0 ) f << "volume=" << ivolume << endl; //G if (igamma!=0 ) f << "gamma=" << igamma << endl; + if (ibacklight!=0 ) f << "backlight=" << ibacklight << endl; if (selectordir!="" ) f << "selectordir=" << selectordir << endl; if (selectorbrowser ) f << "selectorbrowser=true" << endl; if (selectorfilter!="" ) f << "selectorfilter=" << selectorfilter << endl; @@ -233,6 +247,7 @@ bool LinkApp::save() { if (wrapper ) f << "wrapper=true" << endl; if (dontleave ) f << "dontleave=true" << endl; f.close(); + sync(); return true; } else cout << "\033[0;34mGMENU2X:\033[0;31m Error while opening the file '" << file << "' for write\033[0m" << endl; @@ -277,7 +292,7 @@ void LinkApp::showManual() { string ext8 = manual.substr(manual.size()-8,8); if (ext8==".man.png" || ext8==".man.bmp" || ext8==".man.jpg" || manual.substr(manual.size()-9,9)==".man.jpeg") { //Raise the clock to speed-up the loading of the manual - gmenu2x->setClock(200); + gmenu2x->setClock(336); Surface pngman(manual); Surface bg(gmenu2x->confStr["wallpaper"],false); @@ -329,7 +344,7 @@ void LinkApp::showManual() { string line; ifstream infile(manual.c_str(), ios_base::in); if (infile.is_open()) { - gmenu2x->setClock(200); + gmenu2x->setClock(336); while (getline(infile, line, '\n')) txtman.push_back(line); infile.close(); @@ -347,7 +362,7 @@ void LinkApp::showManual() { string line; ifstream infile(manual.c_str(), ios_base::in); if (infile.is_open()) { - gmenu2x->setClock(200); + gmenu2x->setClock(336); while (getline(infile, line, '\n')) readme.push_back(line); infile.close(); @@ -370,7 +385,7 @@ void LinkApp::selector(int startSelection, string selectorDir) { void LinkApp::launch(string selectedFile, string selectedDir) { drawRun(); save(); -#if !defined(TARGET_GP2X) && !defined(TARGET_WIZ) +#ifndef TARGET_GP2X //delay for testing SDL_Delay(1000); #endif @@ -446,11 +461,14 @@ void LinkApp::launch(string selectedFile, string selectedDir) { gmenu2x->writeConfigOpen2x(); if (selectedFile=="") gmenu2x->writeTmp(); - gmenu2x->quit(); + gmenu2x->quit(); if (clock()!=gmenu2x->confInt["menuClock"]) gmenu2x->setClock(clock()); - if (gamma()!=0 && gamma()!=gmenu2x->confInt["gamma"]) - gmenu2x->setGamma(gamma()); + //if (gamma()!=0 && gamma()!=gmenu2x->confInt["gamma"]) + // gmenu2x->setGamma(gamma()); + if((backlight() != 0) && (backlight() != gmenu2x->confInt["backlight"])) + gmenu2x->setBacklight(backlight()); + execlp("/bin/sh","/bin/sh","-c",command.c_str(),NULL); //if execution continues then something went wrong and as we already called SDL_Quit we cannot continue //try relaunching gmenu2x diff --git a/src/linkapp.h b/src/linkapp.h index 3ebd2f6..37a0b1d 100644 --- a/src/linkapp.h +++ b/src/linkapp.h @@ -40,8 +40,10 @@ class LinkApp : public Link { int iclock, ivolume; //G string sgamma; + string sbacklight; //G int igamma; + int ibacklight; string exec, params, workdir, manual, selectordir, selectorfilter, selectorscreens; bool selectorbrowser, useRamTimings; void drawRun(); @@ -87,6 +89,10 @@ class LinkApp : public Link { int gamma(); string gammaStr(); void setGamma(int gamma); + + int backlight(); + string backlightStr(); + void setBacklight(int val); // /G bool wrapper; diff --git a/src/menu.cpp b/src/menu.cpp index c9a6a39..158219c 100644 --- a/src/menu.cpp +++ b/src/menu.cpp @@ -185,8 +185,8 @@ bool Menu::addLink(string path, string file, string section) { } if (path[path.length()-1]!='/') path += "/"; - //if the extension is not equal to gpu or gpe then enable the wrapepr by default - bool wrapper = true, pxml = false; + //if the extension is not equal to gpu or dge then enable the wrapepr by default + bool wrapper = false, pxml = false; //strip the extension from the filename string title = file; @@ -194,7 +194,7 @@ bool Menu::addLink(string path, string file, string section) { if (pos!=string::npos && pos>0) { string ext = title.substr(pos, title.length()); transform(ext.begin(), ext.end(), ext.begin(), (int(*)(int)) tolower); - if (ext == ".gpu" || ext == ".gpe") wrapper = false; + if (ext == ".gpu" || ext == ".dge") wrapper = false; else if (ext == ".pxml") pxml = true; title = title.substr(0, pos); } @@ -269,10 +269,10 @@ bool Menu::addLink(string path, string file, string section) { shorttitle = title; exec = path+file; } - + //Reduce title lenght to fit the link width - if ((int)gmenu2x->font->getTextWidth(shorttitle)>gmenu2x->skinConfInt["linkWidth"]) { - while ((int)gmenu2x->font->getTextWidth(shorttitle+"..")>gmenu2x->skinConfInt["linkWidth"]) + if (gmenu2x->font->getTextWidth(shorttitle)>gmenu2x->skinConfInt["linkWidth"]) { + while (gmenu2x->font->getTextWidth(shorttitle+"..")>gmenu2x->skinConfInt["linkWidth"]) shorttitle = shorttitle.substr(0,shorttitle.length()-1); shorttitle += ".."; } @@ -286,26 +286,15 @@ bool Menu::addLink(string path, string file, string section) { if (!manual.empty()) f << "manual=" << manual << endl; if (wrapper) f << "wrapper=true" << endl; f.close(); - + sync(); int isection = find(sections.begin(),sections.end(),section) - sections.begin(); if (isection>=0 && isection<(int)sections.size()) { #ifdef DEBUG cout << "\033[0;34mGMENU2X:\033[0m Section: " << sections[isection] << "(" << isection << ")" << endl; #endif - - //senquack - fixing bug where adding a new link does not allow the new link - // to be displayed correctly until menu is reloaded: - //senquack - orig. line: -// links[isection].push_back( new LinkApp(gmenu2x, linkpath.c_str()) ); - - //senquack - new code (pulled from Menu::readLinks()) - LinkApp *link = new LinkApp(gmenu2x, linkpath.c_str()); + LinkApp* link = new LinkApp(gmenu2x, linkpath.c_str()); link->setSize(gmenu2x->skinConfInt["linkWidth"],gmenu2x->skinConfInt["linkHeight"]); - if (link->targetExists()) - links[isection].push_back( link ); - else - free(link); - + links[isection].push_back( link ); } } else { #ifdef DEBUG diff --git a/src/menusetting.h b/src/menusetting.h index b360a9c..6f83341 100644 --- a/src/menusetting.h +++ b/src/menusetting.h @@ -20,7 +20,7 @@ #ifndef MENUSETTING_H #define MENUSETTING_H -#if defined(TARGET_GP2X) || defined(TARGET_WIZ) +#ifdef TARGET_GP2X #include "inputmanager.h" #endif diff --git a/src/menusettingint.cpp b/src/menusettingint.cpp index 4338dc6..b72112d 100644 --- a/src/menusettingint.cpp +++ b/src/menusettingint.cpp @@ -24,14 +24,13 @@ using namespace std; using namespace fastdelegate; -MenuSettingInt::MenuSettingInt(GMenu2X *gmenu2x, string name, string description, int *value, int min, int max, int delta) +MenuSettingInt::MenuSettingInt(GMenu2X *gmenu2x, string name, string description, int *value, int min, int max) : MenuSetting(gmenu2x,name,description) { this->gmenu2x = gmenu2x; _value = value; originalValue = *value; this->min = min; this->max = max; - this->delta = delta; setValue(this->value()); //Delegates @@ -69,11 +68,11 @@ void MenuSettingInt::manageInput() { } void MenuSettingInt::inc() { - setValue(value()+delta); + setValue(value()+1); } void MenuSettingInt::dec() { - setValue(value()-delta); + setValue(value()-1); } void MenuSettingInt::setValue(int value) { diff --git a/src/menusettingint.h b/src/menusettingint.h index c483a14..57158ff 100644 --- a/src/menusettingint.h +++ b/src/menusettingint.h @@ -39,7 +39,7 @@ class MenuSettingInt : public MenuSetting { void dec(); public: - MenuSettingInt(GMenu2X *gmenu2x, string name, string description, int *value, int min, int max, int delta=1); + MenuSettingInt(GMenu2X *gmenu2x, string name, string description, int *value, int min, int max); virtual ~MenuSettingInt() {}; virtual void draw(int y); @@ -49,7 +49,7 @@ class MenuSettingInt : public MenuSetting { virtual void drawSelected(int y); virtual bool edited(); - int min, max, delta; + int min, max; virtual void setValue(int value); int value(); }; diff --git a/src/selector.cpp b/src/selector.cpp index 18e112d..2b014b3 100644 --- a/src/selector.cpp +++ b/src/selector.cpp @@ -149,7 +149,7 @@ int Selector::exec(int startSelection) { if ( gmenu2x->input[ACTION_X] ) { if (link->getSelectorBrowser()) { string::size_type p = dir.rfind("/", dir.size()-2); - if (p==string::npos || dir.substr(0,4)!="/mnt" || p<4) { + if (p==string::npos || dir.substr(0,4)!="/boot/local" || p<4) { close = true; result = false; } else { diff --git a/src/selectordetector.h b/src/selectordetector.h index 9a096e3..7c279c5 100644 --- a/src/selectordetector.h +++ b/src/selectordetector.h @@ -2,7 +2,7 @@ #define SELECTORDETECTOR_H /* This class is for handling applications that use Kounch's Selector, to correctly import their settings to GMenu - * It provides interfaces to examine the gpe file to detect Selector and from there, parse the config files. + * It provides interfaces to examine the dge file to detect Selector and from there, parse the config files. */ @@ -23,7 +23,7 @@ skinPath=./ // use possibly cmdLine=./race // USE #path to base directory for file explorer -baseDir=/mnt/sd/roms/ngpc/ // USE +baseDir=/boot/local/gmenu2x/roms/ngpc/ // USE #File filters // USE fileFilter=ngp diff --git a/src/sfontplus.cpp b/src/sfontplus.cpp index 32520e7..4959a2f 100644 --- a/src/sfontplus.cpp +++ b/src/sfontplus.cpp @@ -1,32 +1,54 @@ #include "sfontplus.h" -#include "surface.h" -#include "utilities.h" #include #include -#include #include using namespace std; +Uint32 SFontPlus::getPixel(Sint32 x, Sint32 y) { + assert(x>=0); + assert(xw); + + Uint32 Bpp = surface->format->BytesPerPixel; + + // Get the pixel + switch(Bpp) { + case 1: + return *((Uint8 *)surface->pixels + y * surface->pitch + x); + break; + case 2: + return *((Uint16 *)surface->pixels + y * surface->pitch/2 + x); + break; + case 3: { // Format/endian independent + Uint8 *bits = ((Uint8 *)surface->pixels)+y*surface->pitch+x*Bpp; + Uint8 r, g, b; + r = *((bits)+surface->format->Rshift/8); + g = *((bits)+surface->format->Gshift/8); + b = *((bits)+surface->format->Bshift/8); + return SDL_MapRGB(surface->format, r, g, b); + } + break; + case 4: + return *((Uint32 *)surface->pixels + y * surface->pitch/4 + x); + break; + } + + return 0; +} + SFontPlus::SFontPlus() { surface = NULL; - ttf = false; } SFontPlus::SFontPlus(SDL_Surface* font) { surface = NULL; - ttf = false; initFont(font); } -SFontPlus::SFontPlus(string font, bool ttf, SDL_Color textColor, SDL_Color outlineColor) { +SFontPlus::SFontPlus(string font) { surface = NULL; - this->ttf = false; - if (ttf) - initTTF(font, SDL_HWSURFACE|SDL_SRCALPHA, textColor, outlineColor); - else - initFont(font); + initFont(font); } SFontPlus::~SFontPlus() { @@ -35,79 +57,12 @@ SFontPlus::~SFontPlus() { bool SFontPlus::utf8Code(unsigned char c) { return (c>=194 && c<=198) || c==208 || c==209; -} - -void SFontPlus::initTTF(string fontfile, Uint32 flags, SDL_Color textColor, SDL_Color outlineColor, string characters) { - if (!TTF_WasInit()) TTF_Init(); - TTF_Font *font = TTF_OpenFont(fontfile.c_str(), FONTSIZE); - if (font != NULL) { - ttf = true; - freeFont(); - this->characters = characters; - - int w,h; - if (TTF_SizeUTF8(font, characters.c_str(), &w,&h) == 0) { - lineHeight = h; - - surface = new Surface(w+2*characters.length(), h+2, flags); - Uint32 colorkey = SDL_MapRGB(surface->format(), 0, 255, 255); - SDL_SetColorKey(surface->raw, SDL_SRCCOLORKEY, colorkey); - SDL_FillRect(surface->raw, NULL, colorkey); - - SDL_Rect dstRect; - int charX = 0, xOffset = 0; - const char *c = NULL; - for (uint i=0; i0 && utf8Code(characters[i-1])) - c = characters.substr(i-1,2).c_str(); - else - c = characters.substr(i,1).c_str(); - - int charWidth; - TTF_SizeUTF8(font, c, &charWidth,NULL); - SDL_Surface *tmpSurface = TTF_RenderUTF8_Solid(font, c, outlineColor); - if (tmpSurface != NULL) { - SDL_SetAlpha(tmpSurface, SDL_RLEACCEL, 128); - - for (xOffset=0; xOffset<=2; xOffset++) { - for (dstRect.y=0; dstRect.y<=2; dstRect.y++) { - if (!(xOffset==1 && dstRect.y==1)) { - dstRect.x = xOffset+charX; - SDL_BlitSurface(tmpSurface, NULL, surface->raw, &dstRect); - } - } - } - - dstRect.x = charX+1; - dstRect.y = 1; - SDL_Surface *tmpSurface2 = TTF_RenderUTF8_Blended(font, c, textColor); - if (tmpSurface2 != NULL) { - SDL_BlitSurface(tmpSurface2, NULL, surface->raw, &dstRect); - } - - } - - charX += charWidth+2; - } - } - - TTF_CloseFont(font); - } - - postInit(); + //return c>=194; } void SFontPlus::initFont(string font, string characters) { SDL_Surface *buf = IMG_Load(font.c_str()); - if (!buf) { - //assume ttf file - initTTF(font); - } else { + if (buf!=NULL) { initFont( SDL_DisplayFormatAlpha(buf), characters ); SDL_FreeSurface(buf); } @@ -118,8 +73,8 @@ void SFontPlus::initFont(SDL_Surface *font, string characters) { this->characters = characters; if (font==NULL) return; - surface = new Surface(font); - Uint32 pink = SDL_MapRGB(surface->format(), 255,0,255); + surface = font; + Uint32 pink = SDL_MapRGB(surface->format, 255,0,255); #ifdef _DEBUG bool utf8 = false; @@ -131,14 +86,14 @@ void SFontPlus::initFont(SDL_Surface *font, string characters) { uint c = 0; - surface->lock(); - for (uint x=0; x<(uint)surface->raw->w && cpixel(x,0) == pink) { + SDL_LockSurface(surface); + for (uint x=0; x<(uint)surface->w && craw->w && surface->pixel(x,0) == pink) x++; + while (x<(uint)surface->w && getPixel(x,0) == pink) x++; charpos.push_back(x); //utf8 characters @@ -151,32 +106,25 @@ void SFontPlus::initFont(SDL_Surface *font, string characters) { c++; } } - surface->unlock(); - Uint32 colKey = surface->pixel(0,surface->raw->h-1); - SDL_SetColorKey(surface->raw, SDL_SRCCOLORKEY, colKey); + SDL_UnlockSurface(surface); + Uint32 colKey = getPixel(0,surface->h-1); + SDL_SetColorKey(surface, SDL_SRCCOLORKEY, colKey); string::size_type pos = characters.find("0")*2; - SDL_Rect srcrect = {charpos[pos], 1, charpos[pos+2] - charpos[pos], surface->raw->h-1}; + SDL_Rect srcrect = {charpos[pos], 1, charpos[pos+2] - charpos[pos], surface->h-1}; uint y = srcrect.h+1; bool nonKeyFound = false; while (y-->0 && !nonKeyFound) { uint x = srcrect.w+1; while (x-->0 && !nonKeyFound) - nonKeyFound = surface->pixel(x+srcrect.x,y+srcrect.y) != colKey; + nonKeyFound = getPixel(x+srcrect.x,y+srcrect.y) != colKey; } lineHeight = y+1; - - postInit(); -} - -void SFontPlus::postInit() { - halfHeight = getHeight()/2; - halfLineHeight = getLineHeight()/2; } void SFontPlus::freeFont() { if (surface!=NULL) { - free(surface); + SDL_FreeSurface(surface); surface = NULL; } } @@ -190,9 +138,9 @@ void SFontPlus::write(SDL_Surface *s, string text, int x, int y) { // these values won't change in the loop srcrect.y = 1; dstrect.y = y; - srcrect.h = dstrect.h = surface->raw->h-1; + srcrect.h = dstrect.h = surface->h-1; - for(uint i=0; iraw->w; i++) { + for(uint i=0; iw; i++) { //Utf8 characters if (utf8Code(text[i]) && i+1raw, &srcrect, s, &dstrect); + SDL_BlitSurface(surface, &srcrect, s, &dstrect); x += charpos[pos+2] - charpos[pos+1]; } } -void SFontPlus::write(SDL_Surface* surface, const string& text, int x, int y, const unsigned short halign, const unsigned short valign) { - switch (halign) { - case SFontHAlignCenter: - x -= getTextWidth(text)/2; - break; - case SFontHAlignRight: - x -= getTextWidth(text); - break; - } - - switch (valign) { - case SFontVAlignMiddle: - y -= getHalfHeight(); - break; - case SFontVAlignBottom: - y -= getHeight(); - break; - } - - write(surface, text, x, y); -} - -void SFontPlus::write(SDL_Surface* surface, vector *text, int x, int y, const unsigned short halign, const unsigned short valign) { - switch (valign) { - case SFontVAlignMiddle: - y -= getHalfHeight()*text->size(); - break; - case SFontVAlignBottom: - y -= getHeight()*text->size(); - break; - } - - for (uint i=0; isize(); i++) { - int ix = x; - switch (halign) { - case SFontHAlignCenter: - ix -= getTextWidth(text->at(i))/2; - break; - case SFontHAlignRight: - ix -= getTextWidth(text->at(i)); - break; - } - - write(surface, text->at(i), x, y+getHeight()*i); - } -} - -void SFontPlus::write(Surface* surface, const string& text, int x, int y, const unsigned short halign, const unsigned short valign) { - if (text.find("\n",0)!=string::npos) { - vector textArr; - split(textArr,text,"\n"); - write(surface->raw, &textArr, x, y, halign, valign); - } else - write(surface->raw, text, x, y, halign, valign); -} - -uint SFontPlus::getLineWidth(const string& text) { +uint SFontPlus::getTextWidth(string text) { string::size_type pos; int width = 0; @@ -294,31 +186,11 @@ uint SFontPlus::getLineWidth(const string& text) { return width; } -uint SFontPlus::getTextWidth(const string& text) { - if (text.find("\n",0)!=string::npos) { - vector textArr; - split(textArr,text,"\n"); - return getTextWidth(&textArr); - } else - return getLineWidth(text); -} -uint SFontPlus::getTextWidth(vector *text) { - int w = 0; - for (uint i=0; isize(); i++) - w = max( getLineWidth(text->at(i)), w ); - return w; -} uint SFontPlus::getHeight() { - return surface->raw->h - 1; -} -uint SFontPlus::getHalfHeight() { - return halfHeight; + return surface->h - 1; } uint SFontPlus::getLineHeight() { return lineHeight; } -uint SFontPlus::getHalfLineHeight() { - return halfLineHeight; -} diff --git a/src/sfontplus.h b/src/sfontplus.h index a29cc87..9c9d7fb 100644 --- a/src/sfontplus.h +++ b/src/sfontplus.h @@ -12,60 +12,32 @@ using std::vector; using std::string; -const unsigned short SFontHAlignLeft = 0; -const unsigned short SFontHAlignRight = 1; -const unsigned short SFontHAlignCenter = 2; -const unsigned short SFontVAlignTop = 0; -const unsigned short SFontVAlignBottom = 1; -const unsigned short SFontVAlignMiddle = 2; - -#ifdef TARGET_PANDORA - #define FONTSIZE 12 -#else - #define FONTSIZE 9 -#endif - -class Surface; - class SFontPlus { private: + Uint32 getPixel(Sint32 x, Sint32 y); + SDL_Surface *surface; vector charpos; string characters; - uint height, lineHeight, halfHeight, halfLineHeight; - bool ttf; - - void postInit(); + uint height, lineHeight; public: - Surface *surface; SFontPlus(); SFontPlus(SDL_Surface *font); - SFontPlus(string font, bool ttf = false, SDL_Color textColor = (SDL_Color){255,255,255}, SDL_Color outlineColor = (SDL_Color){5,5,5}); + SFontPlus(string font); ~SFontPlus(); bool utf8Code(unsigned char c); - void initTTF(string fontfile, Uint32 flags = SDL_HWSURFACE|SDL_SRCALPHA, SDL_Color textColor = (SDL_Color){255,255,255}, SDL_Color outlineColor = (SDL_Color){5,5,5}, string characters = SFONTPLUS_CHARSET); void initFont(SDL_Surface *font, string characters = SFONTPLUS_CHARSET); void initFont(string font, string characters = SFONTPLUS_CHARSET); void freeFont(); - - bool isTTF(); void write(SDL_Surface *s, string text, int x, int y); - void write(SDL_Surface* surface, const string& text, int x, int y, const unsigned short halign, const unsigned short valign = 0); - void write(SDL_Surface* surface, vector *text, int x, int y, const unsigned short halign=0, const unsigned short valign = 0); - void write(Surface* surface, const string& text, int x, int y, const unsigned short halign=0, const unsigned short valign = 0); - uint getLineWidth(const string& text); - uint getTextWidth(const string& text); - uint getTextWidth(vector *text); - + uint getTextWidth(string text); uint getHeight(); - uint getHalfHeight(); uint getLineHeight(); - uint getHalfLineHeight(); }; #endif /* SFONTPLUS_H */ diff --git a/src/surface.cpp b/src/surface.cpp index 08d4f1c..edbc735 100644 --- a/src/surface.cpp +++ b/src/surface.cpp @@ -35,10 +35,6 @@ RGBAColor strtorgba(string strColor) { return c; } -SDL_Color rgbatosdl(RGBAColor color) { - return (SDL_Color){color.r, color.g, color.b, color.a}; -} - Surface::Surface() { raw = NULL; dblbuffer = NULL; @@ -89,7 +85,7 @@ Surface::Surface(int w, int h, Uint32 flags) { bmask = 0x00ff0000; amask = 0xff000000; #endif - raw = SDL_DisplayFormat( SDL_CreateRGBSurface( flags, w, h, 16, rmask, gmask, bmask, amask ) ); + raw = SDL_CreateRGBSurface( flags, w, h, 16, rmask, gmask, bmask, amask ); halfW = w/2; halfH = h/2; } @@ -268,7 +264,7 @@ void Surface::blendAdd(Surface *target, int x, int y) { */ } -void Surface::write(SFontPlus *font, string text, int x, int y, const unsigned short halign, const unsigned short valign) { +void Surface::write(ASFont *font, string text, int x, int y, const unsigned short halign, const unsigned short valign) { font->write(this,text,x,y,halign,valign); } diff --git a/src/surface.h b/src/surface.h index 1e5203e..83dad91 100644 --- a/src/surface.h +++ b/src/surface.h @@ -24,7 +24,7 @@ #include #include -#include "sfontplus.h" +#include "asfont.h" using std::string; @@ -33,7 +33,6 @@ struct RGBAColor { }; RGBAColor strtorgba(string strColor); -SDL_Color rgbatosdl(RGBAColor color); /** Wrapper around SDL_Surface @@ -84,7 +83,7 @@ class Surface { bool blitRight(Surface *destination, int x, int y, int w=0, int h=0, int a=-1); bool blitRight(SDL_Surface *destination, int x, int y, int w=0, int h=0, int a=-1); - void write(SFontPlus *font, string text, int x, int y, const unsigned short halign=0, const unsigned short valign=0); + void write(ASFont *font, string text, int x, int y, const unsigned short halign=0, const unsigned short valign=0); int box(Sint16, Sint16, Sint16, Sint16, Uint8, Uint8, Uint8, Uint8); int box(Sint16, Sint16, Sint16, Sint16, Uint8, Uint8, Uint8); diff --git a/src/textdialog.cpp b/src/textdialog.cpp index b2b841e..038078d 100644 --- a/src/textdialog.cpp +++ b/src/textdialog.cpp @@ -40,13 +40,13 @@ void TextDialog::preProcess() { row = trim(text->at(i)); //check if this row is not too long - if (gmenu2x->font->getTextWidth(row)>gmenu2x->resX-15) { + if (gmenu2x->font->getTextWidth(row)>(int)gmenu2x->resX-15) { vector words; split(words, row, " "); uint numWords = words.size(); //find the maximum number of rows that can be printed on screen - while (gmenu2x->font->getTextWidth(row)>gmenu2x->resX-15 && numWords>0) { + while (gmenu2x->font->getTextWidth(row)>(int)gmenu2x->resX-15 && numWords>0) { numWords--; row = ""; for (uint x=0; x