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33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
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ths authored Mar 21, 2007
22 /* CPU / CPU family specific config register values. */
23
24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
25 uncached coherency */
26 #define MIPS_CONFIG0 \
27 ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
29 (0x2 << CP0C0_K0))
30
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ths authored Apr 17, 2007
31 /* Have config2, 64 sets Icache, 16 bytes Icache line,
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32 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
33 no coprocessor2 attached, no MDMX support attached,
34 no performance counters, watch registers present,
35 no code compression, EJTAG present, no FPU */
36 #define MIPS_CONFIG1 \
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37 ((1 << CP0C1_M) | \
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38 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
39 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
40 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
41 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
42 (0 << CP0C1_FP))
43
44 /* Have config3, no tertiary/secondary caches implemented */
45 #define MIPS_CONFIG2 \
46 ((1 << CP0C2_M))
47
48 /* No config4, no DSP ASE, no large physaddr,
49 no external interrupt controller, no vectored interupts,
50 no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
51 #define MIPS_CONFIG3 \
52 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
53 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
54 (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
55
56 /* Define a implementation number of 1.
57 Define a major version 1, minor version 0. */
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ths authored May 7, 2007
58 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
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ths authored Mar 21, 2007
59
60
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
61 struct mips_def_t {
62 const unsigned char *name;
63 int32_t CP0_PRid;
64 int32_t CP0_Config0;
65 int32_t CP0_Config1;
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66 int32_t CP0_Config2;
67 int32_t CP0_Config3;
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68 int32_t CP0_Config6;
69 int32_t CP0_Config7;
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70 int32_t SYNCI_Step;
71 int32_t CCRes;
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72 int32_t Status_rw_bitmask;
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73 int32_t CP1_fcr0;
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74 };
75
76 /*****************************************************************************/
77 /* MIPS CPU definitions */
78 static mips_def_t mips_defs[] =
79 {
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80 #ifndef TARGET_MIPS64
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
81 {
82 .name = "4Kc",
83 .CP0_PRid = 0x00018000,
84 .CP0_Config0 = MIPS_CONFIG0,
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85 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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86 .CP0_Config2 = MIPS_CONFIG2,
87 .CP0_Config3 = MIPS_CONFIG3,
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88 .SYNCI_Step = 32,
89 .CCRes = 2,
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90 .Status_rw_bitmask = 0x3278FF17,
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
91 },
92 {
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93 .name = "4KEcR1",
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94 .CP0_PRid = 0x00018400,
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95 .CP0_Config0 = MIPS_CONFIG0,
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96 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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97 .CP0_Config2 = MIPS_CONFIG2,
98 .CP0_Config3 = MIPS_CONFIG3,
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99 .SYNCI_Step = 32,
100 .CCRes = 2,
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101 .Status_rw_bitmask = 0x3278FF17,
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102 },
103 {
104 .name = "4KEc",
105 .CP0_PRid = 0x00019000,
106 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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107 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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108 .CP0_Config2 = MIPS_CONFIG2,
109 .CP0_Config3 = MIPS_CONFIG3,
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110 .SYNCI_Step = 32,
111 .CCRes = 2,
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112 .Status_rw_bitmask = 0x3278FF17,
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ths authored Mar 24, 2007
113 },
114 {
115 .name = "24Kc",
116 .CP0_PRid = 0x00019300,
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
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117 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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118 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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119 .CP0_Config2 = MIPS_CONFIG2,
120 .CP0_Config3 = MIPS_CONFIG3,
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121 .SYNCI_Step = 32,
122 .CCRes = 2,
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123 .Status_rw_bitmask = 0x3278FF17,
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124 },
125 {
126 .name = "24Kf",
127 .CP0_PRid = 0x00019300,
128 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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ths authored Apr 17, 2007
129 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU),
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130 .CP0_Config2 = MIPS_CONFIG2,
131 .CP0_Config3 = MIPS_CONFIG3,
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132 .SYNCI_Step = 32,
133 .CCRes = 2,
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134 .Status_rw_bitmask = 0x3678FF17,
135 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
136 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
137 },
138 #else
139 {
140 .name = "R4000",
141 .CP0_PRid = 0x00000400,
142 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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ths authored Apr 17, 2007
143 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
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ths authored Mar 21, 2007
144 .CP0_Config2 = MIPS_CONFIG2,
145 .CP0_Config3 = MIPS_CONFIG3,
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146 .SYNCI_Step = 16,
147 .CCRes = 2,
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ths authored May 7, 2007
148 .Status_rw_bitmask = 0x3678FFFF,
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ths authored Jun 1, 2007
149 /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
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ths authored Jun 1, 2007
150 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
151 },
152 {
153 .name = "5Kc",
154 .CP0_PRid = 0x00018100,
155 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
156 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
157 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
158 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
159 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
160 .CP0_Config2 = MIPS_CONFIG2,
161 .CP0_Config3 = MIPS_CONFIG3,
162 .SYNCI_Step = 32,
163 .CCRes = 2,
164 .Status_rw_bitmask = 0x3278FFFF,
165 },
166 {
167 .name = "5Kf",
168 .CP0_PRid = 0x00018100,
169 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
170 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
171 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
172 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
173 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
174 .CP0_Config2 = MIPS_CONFIG2,
175 .CP0_Config3 = MIPS_CONFIG3,
176 .SYNCI_Step = 32,
177 .CCRes = 2,
178 .Status_rw_bitmask = 0x3678FFFF,
1e3d055 Update some comments, 64bit FPU support is functional regardless of
ths authored Jun 1, 2007
179 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
c9c1a06 Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno.
ths authored Jun 1, 2007
180 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
181 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
182 },
183 {
184 .name = "20Kc",
185 .CP0_PRid = 0x00018200,
186 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
187 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
188 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
189 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
190 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
191 .CP0_Config2 = MIPS_CONFIG2,
192 .CP0_Config3 = MIPS_CONFIG3,
193 .SYNCI_Step = 32,
194 .CCRes = 2,
195 .Status_rw_bitmask = 0x36FBFFFF,
1e3d055 Update some comments, 64bit FPU support is functional regardless of
ths authored Jun 1, 2007
196 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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ths authored Jun 1, 2007
197 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
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ths authored May 7, 2007
198 (1 << FCR0_D) | (1 << FCR0_S) |
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ths authored Jun 1, 2007
199 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
200 },
201 #endif
202 };
203
204 int mips_find_by_name (const unsigned char *name, mips_def_t **def)
205 {
206 int i, ret;
207
208 ret = -1;
209 *def = NULL;
210 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
211 if (strcasecmp(name, mips_defs[i].name) == 0) {
212 *def = &mips_defs[i];
213 ret = 0;
214 break;
215 }
216 }
217
218 return ret;
219 }
220
221 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
222 {
223 int i;
224
225 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
226 (*cpu_fprintf)(f, "MIPS '%s'\n",
227 mips_defs[i].name);
228 }
229 }
230
29929e3 MIPS TLB style selection at runtime, by Herve Poussineau.
ths authored May 13, 2007
231 #ifndef CONFIG_USER_ONLY
232 static void no_mmu_init (CPUMIPSState *env, mips_def_t *def)
233 {
234 env->nb_tlb = 1;
235 env->map_address = &no_mmu_map_address;
236 }
237
238 static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def)
239 {
240 env->nb_tlb = 1;
241 env->map_address = &fixed_mmu_map_address;
242 }
243
244 static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def)
245 {
246 env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
247 env->map_address = &r4k_map_address;
248 env->do_tlbwi = r4k_do_tlbwi;
249 env->do_tlbwr = r4k_do_tlbwr;
250 env->do_tlbp = r4k_do_tlbp;
251 env->do_tlbr = r4k_do_tlbr;
252 }
253 #endif /* CONFIG_USER_ONLY */
254
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
255 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
256 {
257 if (!def)
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258 def = env->cpu_model;
259 if (!def)
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ths authored Mar 18, 2007
260 cpu_abort(env, "Unable to find MIPS CPU definition\n");
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ths authored May 30, 2007
261 env->cpu_model = def;
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ths authored Mar 18, 2007
262 env->CP0_PRid = def->CP0_PRid;
263 env->CP0_Config0 = def->CP0_Config0;
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ths authored May 30, 2007
264 #ifdef TARGET_WORDS_BIGENDIAN
265 env->CP0_Config0 |= (1 << CP0C0_BE);
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ths authored Mar 21, 2007
266 #endif
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ths authored Mar 18, 2007
267 env->CP0_Config1 = def->CP0_Config1;
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ths authored Mar 21, 2007
268 env->CP0_Config2 = def->CP0_Config2;
269 env->CP0_Config3 = def->CP0_Config3;
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ths authored Mar 24, 2007
270 env->CP0_Config6 = def->CP0_Config6;
271 env->CP0_Config7 = def->CP0_Config7;
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ths authored Apr 11, 2007
272 env->SYNCI_Step = def->SYNCI_Step;
273 env->CCRes = def->CCRes;
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ths authored May 7, 2007
274 env->Status_rw_bitmask = def->Status_rw_bitmask;
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ths authored Mar 21, 2007
275 env->fcr0 = def->CP1_fcr0;
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ths authored Jun 1, 2007
276 #ifdef CONFIG_USER_ONLY
277 if (env->CP0_Config1 & (1 << CP0C1_FP))
278 env->hflags |= MIPS_HFLAG_FPU;
279 if (env->fcr0 & (1 << FCR0_F64))
280 env->hflags |= MIPS_HFLAG_F64;
281 #else
1e3d055 Update some comments, 64bit FPU support is functional regardless of
ths authored Jun 1, 2007
282 /* There are more full-featured MMU variants in older MIPS CPUs,
283 R3000, R6000 and R8000 come to mind. If we ever support them,
284 this check will need to look up a different place than those
285 newfangled config registers. */
29929e3 MIPS TLB style selection at runtime, by Herve Poussineau.
ths authored May 13, 2007
286 switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
287 case 0:
288 no_mmu_init(env, def);
289 break;
290 case 1:
291 r4k_mmu_init(env, def);
292 break;
293 case 3:
294 fixed_mmu_init(env, def);
295 break;
296 default:
297 cpu_abort(env, "MMU type not supported\n");
298 }
fcb4a41 Choose number of TLBs at runtime, by Herve Poussineau.
ths authored Apr 17, 2007
299 env->CP0_Random = env->nb_tlb - 1;
300 env->tlb_in_use = env->nb_tlb;
29929e3 MIPS TLB style selection at runtime, by Herve Poussineau.
ths authored May 13, 2007
301 #endif /* CONFIG_USER_ONLY */
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
ths authored Mar 18, 2007
302 return 0;
303 }
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