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33d68b5 MIPS -cpu selection support, by Herve Poussineau.
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1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
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22 /* CPU / CPU family specific config register values. */
23
24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
25 uncached coherency */
26 #define MIPS_CONFIG0 \
27 ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
29 (0x2 << CP0C0_K0))
30
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31 /* Have config2, no coprocessor2 attached, no MDMX support attached,
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32 no performance counters, watch registers present,
33 no code compression, EJTAG present, no FPU */
34 #define MIPS_CONFIG1 \
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35 ((1 << CP0C1_M) | \
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36 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
37 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
38 (0 << CP0C1_FP))
39
40 /* Have config3, no tertiary/secondary caches implemented */
41 #define MIPS_CONFIG2 \
42 ((1 << CP0C2_M))
43
44 /* No config4, no DSP ASE, no large physaddr,
45 no external interrupt controller, no vectored interupts,
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46 no 1kb pages, no SmartMIPS ASE, no trace logic */
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47 #define MIPS_CONFIG3 \
48 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
49 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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50 (0 << CP0C3_SM) | (0 << CP0C3_TL))
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51
52 /* Define a implementation number of 1.
53 Define a major version 1, minor version 0. */
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54 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
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55
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56 struct mips_def_t {
57 const unsigned char *name;
58 int32_t CP0_PRid;
59 int32_t CP0_Config0;
60 int32_t CP0_Config1;
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61 int32_t CP0_Config2;
62 int32_t CP0_Config3;
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63 int32_t CP0_Config6;
64 int32_t CP0_Config7;
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65 int32_t SYNCI_Step;
66 int32_t CCRes;
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67 int32_t CP0_Status_rw_bitmask;
68 int32_t CP0_TCStatus_rw_bitmask;
69 int32_t CP0_SRSCtl;
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70 int32_t CP1_fcr0;
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71 int32_t SEGBITS;
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72 int32_t CP0_SRSConf0_rw_bitmask;
73 int32_t CP0_SRSConf0;
74 int32_t CP0_SRSConf1_rw_bitmask;
75 int32_t CP0_SRSConf1;
76 int32_t CP0_SRSConf2_rw_bitmask;
77 int32_t CP0_SRSConf2;
78 int32_t CP0_SRSConf3_rw_bitmask;
79 int32_t CP0_SRSConf3;
80 int32_t CP0_SRSConf4_rw_bitmask;
81 int32_t CP0_SRSConf4;
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82 int insn_flags;
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83 };
84
85 /*****************************************************************************/
86 /* MIPS CPU definitions */
87 static mips_def_t mips_defs[] =
88 {
89 {
90 .name = "4Kc",
91 .CP0_PRid = 0x00018000,
92 .CP0_Config0 = MIPS_CONFIG0,
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93 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
94 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
95 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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96 .CP0_Config2 = MIPS_CONFIG2,
97 .CP0_Config3 = MIPS_CONFIG3,
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98 .SYNCI_Step = 32,
99 .CCRes = 2,
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100 .CP0_Status_rw_bitmask = 0x1278FF17,
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101 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
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102 },
103 {
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104 .name = "4Km",
105 .CP0_PRid = 0x00018300,
106 /* Config1 implemented, fixed mapping MMU,
107 no virtual icache, uncached coherency. */
108 .CP0_Config0 = (1 << CP0C0_M) |
109 (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
110 .CP0_Config1 = MIPS_CONFIG1 |
111 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
112 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
113 .CP0_Config2 = MIPS_CONFIG2,
114 .CP0_Config3 = MIPS_CONFIG3,
115 .SYNCI_Step = 32,
116 .CCRes = 2,
117 .CP0_Status_rw_bitmask = 0x1258FF17,
118 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
119 },
120 {
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121 .name = "4KEcR1",
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122 .CP0_PRid = 0x00018400,
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123 .CP0_Config0 = MIPS_CONFIG0,
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124 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
125 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
126 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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127 .CP0_Config2 = MIPS_CONFIG2,
128 .CP0_Config3 = MIPS_CONFIG3,
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129 .SYNCI_Step = 32,
130 .CCRes = 2,
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131 .CP0_Status_rw_bitmask = 0x1278FF17,
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132 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
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133 },
134 {
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135 .name = "4KEmR1",
136 .CP0_PRid = 0x00018500,
137 /* Config1 implemented, fixed mapping MMU,
138 no virtual icache, uncached coherency. */
139 .CP0_Config0 = (1 << CP0C0_M) |
140 (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
141 .CP0_Config1 = MIPS_CONFIG1 |
142 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
143 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
144 .CP0_Config2 = MIPS_CONFIG2,
145 .CP0_Config3 = MIPS_CONFIG3,
146 .SYNCI_Step = 32,
147 .CCRes = 2,
148 .CP0_Status_rw_bitmask = 0x1258FF17,
149 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
150 },
151 {
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152 .name = "4KEc",
153 .CP0_PRid = 0x00019000,
154 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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155 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
156 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
157 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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158 .CP0_Config2 = MIPS_CONFIG2,
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159 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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160 .SYNCI_Step = 32,
161 .CCRes = 2,
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162 .CP0_Status_rw_bitmask = 0x1278FF17,
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163 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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164 },
165 {
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166 .name = "4KEm",
167 .CP0_PRid = 0x00019100,
168 /* Config1 implemented, MIPS32R2, fixed mapping MMU,
169 no virtual icache, uncached coherency. */
170 .CP0_Config0 = (1 << CP0C0_M) | (0x1 << CP0C0_AR) |
171 (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
172 .CP0_Config1 = MIPS_CONFIG1 |
173 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
174 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
175 .CP0_Config2 = MIPS_CONFIG2,
176 .CP0_Config3 = MIPS_CONFIG3,
177 .SYNCI_Step = 32,
178 .CCRes = 2,
179 .CP0_Status_rw_bitmask = 0x1258FF17,
180 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
181 },
182 {
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183 .name = "24Kc",
184 .CP0_PRid = 0x00019300,
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185 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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186 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
187 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
188 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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189 .CP0_Config2 = MIPS_CONFIG2,
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190 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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191 .SYNCI_Step = 32,
192 .CCRes = 2,
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193 /* No DSP implemented. */
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194 .CP0_Status_rw_bitmask = 0x1278FF1F,
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195 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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196 },
197 {
198 .name = "24Kf",
199 .CP0_PRid = 0x00019300,
200 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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201 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
202 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
203 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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204 .CP0_Config2 = MIPS_CONFIG2,
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205 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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206 .SYNCI_Step = 32,
207 .CCRes = 2,
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208 /* No DSP implemented. */
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209 .CP0_Status_rw_bitmask = 0x3678FF1F,
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210 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
211 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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212 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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213 },
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214 {
215 .name = "34Kf",
216 .CP0_PRid = 0x00019500,
217 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
218 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
219 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
220 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
221 .CP0_Config2 = MIPS_CONFIG2,
222 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
223 .SYNCI_Step = 32,
224 .CCRes = 2,
225 /* No DSP implemented. */
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226 .CP0_Status_rw_bitmask = 0x3678FF1F,
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227 /* No DSP implemented. */
228 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
229 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
230 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
231 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
232 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
233 (0xff << CP0TCSt_TASID),
234 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
235 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
236 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
237 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
238 .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
239 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
240 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
241 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
242 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
243 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
244 .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
245 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
246 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
247 .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
248 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
249 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
250 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
251 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
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252 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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253 },
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254 #if defined(TARGET_MIPS64)
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255 {
256 .name = "R4000",
257 .CP0_PRid = 0x00000400,
258 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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259 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
260 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
261 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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262 .CP0_Config2 = MIPS_CONFIG2,
263 .CP0_Config3 = MIPS_CONFIG3,
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264 .SYNCI_Step = 16,
265 .CCRes = 2,
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266 .CP0_Status_rw_bitmask = 0x3678FFFF,
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267 /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
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268 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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269 .SEGBITS = 40,
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270 .insn_flags = CPU_MIPS3,
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271 },
272 {
273 .name = "5Kc",
274 .CP0_PRid = 0x00018100,
275 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
276 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
277 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
278 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
279 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
280 .CP0_Config2 = MIPS_CONFIG2,
281 .CP0_Config3 = MIPS_CONFIG3,
282 .SYNCI_Step = 32,
283 .CCRes = 2,
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284 .CP0_Status_rw_bitmask = 0x32F8FFFF,
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285 .SEGBITS = 42,
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286 .insn_flags = CPU_MIPS64,
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287 },
288 {
289 .name = "5Kf",
290 .CP0_PRid = 0x00018100,
291 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
292 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
293 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
294 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
295 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
296 .CP0_Config2 = MIPS_CONFIG2,
297 .CP0_Config3 = MIPS_CONFIG3,
298 .SYNCI_Step = 32,
299 .CCRes = 2,
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300 .CP0_Status_rw_bitmask = 0x36F8FFFF,
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301 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
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302 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
303 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
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304 .SEGBITS = 42,
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305 .insn_flags = CPU_MIPS64,
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306 },
307 {
308 .name = "20Kc",
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309 /* We emulate a later version of the 20Kc, earlier ones had a broken
310 WAIT instruction. */
311 .CP0_PRid = 0x000182a0,
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312 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
313 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
314 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
315 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
316 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
317 .CP0_Config2 = MIPS_CONFIG2,
318 .CP0_Config3 = MIPS_CONFIG3,
319 .SYNCI_Step = 32,
320 .CCRes = 2,
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321 .CP0_Status_rw_bitmask = 0x36FBFFFF,
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322 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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323 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
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324 (1 << FCR0_D) | (1 << FCR0_S) |
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325 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
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326 .SEGBITS = 40,
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327 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
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328 },
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329 {
330 /* A generic CPU providing MIPS64 Release 2 features.
331 FIXME: Eventually this should be replaced by a real CPU model. */
332 .name = "MIPS64R2-generic",
8c89395 Use a valid PRid.
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333 .CP0_PRid = 0x00010000,
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334 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR),
335 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
336 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
337 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
338 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
339 .CP0_Config2 = MIPS_CONFIG2,
340 .CP0_Config3 = MIPS_CONFIG3,
341 .SYNCI_Step = 32,
342 .CCRes = 2,
343 .CP0_Status_rw_bitmask = 0x36FBFFFF,
344 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) |
345 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
346 (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
347 .SEGBITS = 40,
348 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
349 },
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350 #endif
351 };
352
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353 static const mips_def_t *cpu_mips_find_by_name (const unsigned char *name)
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354 {
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355 int i;
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356
357 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
358 if (strcasecmp(name, mips_defs[i].name) == 0) {
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359 return &mips_defs[i];
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360 }
361 }
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362 return NULL;
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363 }
364
365 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
366 {
367 int i;
368
369 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
370 (*cpu_fprintf)(f, "MIPS '%s'\n",
371 mips_defs[i].name);
372 }
373 }
374
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375 #ifndef CONFIG_USER_ONLY
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376 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
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377 {
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378 env->tlb->nb_tlb = 1;
379 env->tlb->map_address = &no_mmu_map_address;
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380 }
381
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382 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
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383 {
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384 env->tlb->nb_tlb = 1;
385 env->tlb->map_address = &fixed_mmu_map_address;
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386 }
387
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388 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
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389 {
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390 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
391 env->tlb->map_address = &r4k_map_address;
392 env->tlb->do_tlbwi = r4k_do_tlbwi;
393 env->tlb->do_tlbwr = r4k_do_tlbwr;
394 env->tlb->do_tlbp = r4k_do_tlbp;
395 env->tlb->do_tlbr = r4k_do_tlbr;
396 }
397
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398 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
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399 {
400 env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
401
402 /* There are more full-featured MMU variants in older MIPS CPUs,
403 R3000, R6000 and R8000 come to mind. If we ever support them,
404 this check will need to look up a different place than those
405 newfangled config registers. */
406 switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
407 case 0:
408 no_mmu_init(env, def);
409 break;
410 case 1:
411 r4k_mmu_init(env, def);
412 break;
413 case 3:
414 fixed_mmu_init(env, def);
415 break;
416 default:
417 cpu_abort(env, "MMU type not supported\n");
418 }
419 env->CP0_Random = env->tlb->nb_tlb - 1;
420 env->tlb->tlb_in_use = env->tlb->nb_tlb;
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421 }
422 #endif /* CONFIG_USER_ONLY */
423
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424 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
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425 {
426 env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
427
428 env->fpu->fcr0 = def->CP1_fcr0;
429 #ifdef CONFIG_USER_ONLY
430 if (env->CP0_Config1 & (1 << CP0C1_FP))
431 env->hflags |= MIPS_HFLAG_FPU;
432 if (env->fpu->fcr0 & (1 << FCR0_F64))
433 env->hflags |= MIPS_HFLAG_F64;
434 #endif
435 }
436
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437 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
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438 {
439 env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
440
441 /* MVPConf1 implemented, TLB sharable, no gating storage support,
442 programmable cache partitioning implemented, number of allocatable
443 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
444 implemented, 5 TCs implemented. */
445 env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
446 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
2337fdc Fix mips usermode emulation.
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447 #ifndef CONFIG_USER_ONLY
448 /* Usermode has no TLB support */
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449 (env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
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450 #endif
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451 // TODO: actually do 2 VPEs.
452 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
453 // (0x04 << CP0MVPC0_PTC);
454 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
455 (0x04 << CP0MVPC0_PTC);
456 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
457 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
458 env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
459 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
460 (0x1 << CP0MVPC1_PCP1);
461 }
462
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463 static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
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464 {
465 env->CP0_PRid = def->CP0_PRid;
466 env->CP0_Config0 = def->CP0_Config0;
51b2772 Fix CPU (re-)selection on reset.
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467 #ifdef TARGET_WORDS_BIGENDIAN
468 env->CP0_Config0 |= (1 << CP0C0_BE);
3953d78 Move mips CPU specific initialization to translate_init.c.
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469 #endif
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470 env->CP0_Config1 = def->CP0_Config1;
3953d78 Move mips CPU specific initialization to translate_init.c.
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471 env->CP0_Config2 = def->CP0_Config2;
472 env->CP0_Config3 = def->CP0_Config3;
34ee2ed One more bit of mips CPU configuration, and support for early 4KEc
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473 env->CP0_Config6 = def->CP0_Config6;
474 env->CP0_Config7 = def->CP0_Config7;
2f64454 Make SYNCI_Step and CCRes CPU-specific.
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475 env->SYNCI_Step = def->SYNCI_Step;
476 env->CCRes = def->CCRes;
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477 env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
478 env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
479 env->CP0_SRSCtl = def->CP0_SRSCtl;
d26bc21 Clean out the N32 macros from target-mips, and introduce MIPS ABI spe…
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480 #if defined(TARGET_MIPS64)
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481 if (def->insn_flags & ISA_MIPS3)
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482 {
483 env->hflags |= MIPS_HFLAG_64;
484 env->SEGBITS = def->SEGBITS;
485 env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
486 } else {
487 env->SEGBITS = 32;
488 env->SEGMask = 0xFFFFFFFF;
489 }
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490 #endif
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491 env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
492 env->CP0_SRSConf0 = def->CP0_SRSConf0;
493 env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
494 env->CP0_SRSConf1 = def->CP0_SRSConf1;
495 env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
496 env->CP0_SRSConf2 = def->CP0_SRSConf2;
497 env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
498 env->CP0_SRSConf3 = def->CP0_SRSConf3;
499 env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
500 env->CP0_SRSConf4 = def->CP0_SRSConf4;
e189e74 Per-CPU instruction decoding implementation, by Aurelien Jarno.
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501 env->insn_flags = def->insn_flags;
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502
503 #ifndef CONFIG_USER_ONLY
504 mmu_init(env, def);
505 #endif
506 fpu_init(env, def);
507 mvp_init(env, def);
33d68b5 MIPS -cpu selection support, by Herve Poussineau.
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508 return 0;
509 }
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