Skip to content
  • UK


@clacktronics @seanjensengrey



Block or Report

Block or report ultraembedded

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse


  1. biriscv Public

    32-bit Superscalar RISC-V CPU

    Verilog 334 69

  2. riscv Public

    RISC-V CPU Core (RV32IM)

    Verilog 441 104

  3. cores Public

    Various HDL (Verilog) IP Cores

    Verilog 343 141

  4. Basic RISC-V Test SoC

    Verilog 30 15

  5. FPGAmp Public

    720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

    C 150 23

  6. Instruction set simulator for RISC-V, MIPS and ARM-v6m

    C++ 37 7

99 contributions in the last year

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Mon Wed Fri

Contribution activity

January 2022

ultraembedded has no activity yet for this period.

Seeing something unexpected? Take a look at the GitHub profile guide.