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Release 11.1 Map L.33 (nt)
Xilinx Map Application Log File for Design 'commodore'

Design Information
------------------
Command Line : map -ise EE314project.ise -intstyle ise -p xc3s1200e-fg320-4
-cm area -ir off -pr off -c 100 -o commodore_map.ncd commodore.ngd commodore.pcf
 
Target Device : xc3s1200e
Target Package : fg320
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.51 $
Mapped Date : Wed Apr 14 18:40:45 2010

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s1200e' is a WebPack part.
WARNING:Security:42 - Your license support version '2010.04' for WebPack expires
in 15 days.
----------------------------------------------------------------------

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
WARNING:LIT:243 - Logical network LPf/rdy has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 23
   more times for the following (max. 5 shown):
   LPf/blk00000003/blk000001a6/LO,
   LPf/blk00000003/blk000001be/LO,
   LPf/blk00000003/blk000001d6/LO,
   LPf/blk00000003/blk000001ee/LO,
   LPf/blk00000003/blk00000223/LO
   To see the details of these warning messages, please use the -detail switch.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal ADCin connected to top level port ADCin has been
   removed.
WARNING:MapLib:701 - Signal frequency<9> connected to top level port
   frequency<9> has been removed.
WARNING:MapLib:701 - Signal frequency<8> connected to top level port
   frequency<8> has been removed.
WARNING:MapLib:701 - Signal frequency<7> connected to top level port
   frequency<7> has been removed.
WARNING:MapLib:701 - Signal frequency<6> connected to top level port
   frequency<6> has been removed.
WARNING:MapLib:701 - Signal frequency<5> connected to top level port
   frequency<5> has been removed.
WARNING:MapLib:701 - Signal frequency<4> connected to top level port
   frequency<4> has been removed.
WARNING:MapLib:701 - Signal frequency<3> connected to top level port
   frequency<3> has been removed.
WARNING:MapLib:701 - Signal frequency<2> connected to top level port
   frequency<2> has been removed.
WARNING:MapLib:701 - Signal frequency<1> connected to top level port
   frequency<1> has been removed.
WARNING:MapLib:701 - Signal frequency<0> connected to top level port
   frequency<0> has been removed.
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors: 0
Number of warnings: 13
Logic Utilization:
  Number of Slice Flip Flops: 40 out of 17,344 1%
  Number of 4 input LUTs: 18 out of 17,344 1%
Logic Distribution:
  Number of occupied Slices: 28 out of 8,672 1%
    Number of Slices containing only related logic: 28 out of 28 100%
    Number of Slices containing unrelated logic: 0 out of 28 0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs: 49 out of 17,344 1%
    Number used as logic: 18
    Number used as a route-thru: 31

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs: 3 out of 250 1%
  Number of BUFGMUXs: 2 out of 24 8%

Average Fanout of Non-Clock Nets: 2.40

Peak Memory Usage: 172 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 3 secs

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs. When assembling slices,
   Map gives priority to combine logic that is related. Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity. Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied. Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "commodore_map.mrp" for details.
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