From 84fe5d175667518a925e181a50c0ebea70eaed5a Mon Sep 17 00:00:00 2001 From: lockbox Date: Thu, 15 Jun 2023 19:19:39 -0400 Subject: [PATCH 1/2] expose ffi in rust bindings --- bindings/rust/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/rust/src/lib.rs b/bindings/rust/src/lib.rs index 5b4e7d3349..c67dd4cf22 100644 --- a/bindings/rust/src/lib.rs +++ b/bindings/rust/src/lib.rs @@ -34,10 +34,10 @@ extern crate std; #[macro_use] pub mod unicorn_const; +pub mod ffi; // lets consumers call ffi if desired mod arm; mod arm64; -mod ffi; mod m68k; mod mips; mod ppc; From 2f2bf8d96f3d610316cd6cddf2a122d9f70ac962 Mon Sep 17 00:00:00 2001 From: lockbox Date: Thu, 13 Jul 2023 13:58:14 -0400 Subject: [PATCH 2/2] add cpu model to architectures for rust bindings --- bindings/rust/src/arm.rs | 50 +++++ bindings/rust/src/arm64.rs | 24 ++- bindings/rust/src/m68k.rs | 28 +++ bindings/rust/src/mips.rs | 33 ++++ bindings/rust/src/ppc.rs | 342 +++++++++++++++++++++++++++++++++++ bindings/rust/src/riscv.rs | 43 ++++- bindings/rust/src/s390x.rs | 57 +++++- bindings/rust/src/sparc.rs | 66 +++++++ bindings/rust/src/tricore.rs | 23 ++- bindings/rust/src/x86.rs | 59 +++++- 10 files changed, 720 insertions(+), 5 deletions(-) diff --git a/bindings/rust/src/arm.rs b/bindings/rust/src/arm.rs index 7b14236b43..df43245d7d 100644 --- a/bindings/rust/src/arm.rs +++ b/bindings/rust/src/arm.rs @@ -171,3 +171,53 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +pub enum ArmCpuModel { + UC_CPU_ARM_926 = 0, + UC_CPU_ARM_946 = 1, + UC_CPU_ARM_1026 = 2, + UC_CPU_ARM_1136_R2 = 3, + UC_CPU_ARM_1136 = 4, + UC_CPU_ARM_1176 = 5, + UC_CPU_ARM_11MPCORE = 6, + UC_CPU_ARM_CORTEX_M0 = 7, + UC_CPU_ARM_CORTEX_M3 = 8, + UC_CPU_ARM_CORTEX_M4 = 9, + UC_CPU_ARM_CORTEX_M7 = 10, + UC_CPU_ARM_CORTEX_M33 = 11, + UC_CPU_ARM_CORTEX_R5 = 12, + UC_CPU_ARM_CORTEX_R5F = 13, + UC_CPU_ARM_CORTEX_A7 = 14, + UC_CPU_ARM_CORTEX_A8 = 15, + UC_CPU_ARM_CORTEX_A9 = 16, + UC_CPU_ARM_CORTEX_A15 = 17, + UC_CPU_ARM_TI925T = 18, + UC_CPU_ARM_SA1100 = 19, + UC_CPU_ARM_SA1110 = 20, + UC_CPU_ARM_PXA250 = 21, + UC_CPU_ARM_PXA255 = 22, + UC_CPU_ARM_PXA260 = 23, + UC_CPU_ARM_PXA261 = 24, + UC_CPU_ARM_PXA262 = 25, + UC_CPU_ARM_PXA270 = 26, + UC_CPU_ARM_PXA270A0 = 27, + UC_CPU_ARM_PXA270A1 = 28, + UC_CPU_ARM_PXA270B0 = 29, + UC_CPU_ARM_PXA270B1 = 30, + UC_CPU_ARM_PXA270C0 = 31, + UC_CPU_ARM_PXA270C5 = 32, +} + +impl From for i32 { + fn from(value: ArmCpuModel) -> Self { + value as i32 + } +} + +impl From<&ArmCpuModel> for i32 { + fn from(value: &ArmCpuModel) -> Self { + *value as i32 + } +} diff --git a/bindings/rust/src/arm64.rs b/bindings/rust/src/arm64.rs index 2d41f37a8b..10f9f25b9c 100644 --- a/bindings/rust/src/arm64.rs +++ b/bindings/rust/src/arm64.rs @@ -1,7 +1,8 @@ +#![allow(non_camel_case_types)] + // ARM64 registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] -#[allow(non_camel_case_types)] pub enum RegisterARM64 { INVALID = 0, X29 = 1, @@ -324,3 +325,24 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Arm64CpuModel { + UC_CPU_ARM64_A57 = 0, + UC_CPU_ARM64_A53 = 1, + UC_CPU_ARM64_A72 = 2, + UC_CPU_ARM64_MAX = 3, +} + +impl From for i32 { + fn from(value: Arm64CpuModel) -> Self { + value as i32 + } +} + +impl From<&Arm64CpuModel> for i32 { + fn from(value: &Arm64CpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/m68k.rs b/bindings/rust/src/m68k.rs index 3c50a10c90..ccc8cfc295 100644 --- a/bindings/rust/src/m68k.rs +++ b/bindings/rust/src/m68k.rs @@ -1,3 +1,5 @@ +#![allow(non_camel_case_types)] + // M68K registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] @@ -29,3 +31,29 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum M68kCpuModel { + UC_CPU_M68K_M5206 = 0, + UC_CPU_M68K_M68000 = 1, + UC_CPU_M68K_M68020 = 2, + UC_CPU_M68K_M68030 = 3, + UC_CPU_M68K_M68040 = 4, + UC_CPU_M68K_M68060 = 5, + UC_CPU_M68K_M5208 = 6, + UC_CPU_M68K_CFV4E = 7, + UC_CPU_M68K_ANY = 8, +} + +impl From for i32 { + fn from(value: M68kCpuModel) -> Self { + value as i32 + } +} + +impl From<&M68kCpuModel> for i32 { + fn from(value: &M68kCpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/mips.rs b/bindings/rust/src/mips.rs index e0de181a22..208c251b2b 100644 --- a/bindings/rust/src/mips.rs +++ b/bindings/rust/src/mips.rs @@ -251,3 +251,36 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Mips32CpuModel { + UC_CPU_MIPS32_4KC = 0, + UC_CPU_MIPS32_4KM = 1, + UC_CPU_MIPS32_4KECR1 = 2, + UC_CPU_MIPS32_4KEMR1 = 3, + UC_CPU_MIPS32_4KEC = 4, + UC_CPU_MIPS32_4KEM = 5, + UC_CPU_MIPS32_24KC = 6, + UC_CPU_MIPS32_24KEC = 7, + UC_CPU_MIPS32_24KF = 8, + UC_CPU_MIPS32_34KF = 9, + UC_CPU_MIPS32_74KF = 10, + UC_CPU_MIPS32_M14K = 11, + UC_CPU_MIPS32_M14KC = 12, + UC_CPU_MIPS32_P5600 = 13, + UC_CPU_MIPS32_MIPS32R6_GENERIC = 14, + UC_CPU_MIPS32_I7200 = 15, +} + +impl From for i32 { + fn from(value: Mips32CpuModel) -> Self { + value as i32 + } +} + +impl From<&Mips32CpuModel> for i32 { + fn from(value: &Mips32CpuModel) -> Self { + *value as i32 + } +} diff --git a/bindings/rust/src/ppc.rs b/bindings/rust/src/ppc.rs index d24d5cb203..63b26e1f33 100644 --- a/bindings/rust/src/ppc.rs +++ b/bindings/rust/src/ppc.rs @@ -93,3 +93,345 @@ impl From for i32 { r as i32 } } + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum PpcCpuModel { + UC_CPU_PPC32_401 = 0, + UC_CPU_PPC32_401A1, + UC_CPU_PPC32_401B2, + UC_CPU_PPC32_401C2, + UC_CPU_PPC32_401D2, + UC_CPU_PPC32_401E2, + UC_CPU_PPC32_401F2, + UC_CPU_PPC32_401G2, + UC_CPU_PPC32_IOP480, + UC_CPU_PPC32_COBRA, + UC_CPU_PPC32_403GA, + UC_CPU_PPC32_403GB, + UC_CPU_PPC32_403GC, + UC_CPU_PPC32_403GCX, + UC_CPU_PPC32_405D2, + UC_CPU_PPC32_405D4, + UC_CPU_PPC32_405CRA, + UC_CPU_PPC32_405CRB, + UC_CPU_PPC32_405CRC, + UC_CPU_PPC32_405EP, + UC_CPU_PPC32_405EZ, + UC_CPU_PPC32_405GPA, + UC_CPU_PPC32_405GPB, + UC_CPU_PPC32_405GPC, + UC_CPU_PPC32_405GPD, + UC_CPU_PPC32_405GPR, + UC_CPU_PPC32_405LP, + UC_CPU_PPC32_NPE405H, + UC_CPU_PPC32_NPE405H2, + UC_CPU_PPC32_NPE405L, + UC_CPU_PPC32_NPE4GS3, + UC_CPU_PPC32_STB03, + UC_CPU_PPC32_STB04, + UC_CPU_PPC32_STB25, + UC_CPU_PPC32_X2VP4, + UC_CPU_PPC32_X2VP20, + UC_CPU_PPC32_440_XILINX, + UC_CPU_PPC32_440_XILINX_W_DFPU, + UC_CPU_PPC32_440EPA, + UC_CPU_PPC32_440EPB, + UC_CPU_PPC32_440EPX, + UC_CPU_PPC32_460EXB, + UC_CPU_PPC32_G2, + UC_CPU_PPC32_G2H4, + UC_CPU_PPC32_G2GP, + UC_CPU_PPC32_G2LS, + UC_CPU_PPC32_G2HIP3, + UC_CPU_PPC32_G2HIP4, + UC_CPU_PPC32_MPC603, + UC_CPU_PPC32_G2LE, + UC_CPU_PPC32_G2LEGP, + UC_CPU_PPC32_G2LELS, + UC_CPU_PPC32_G2LEGP1, + UC_CPU_PPC32_G2LEGP3, + UC_CPU_PPC32_MPC5200_V10, + UC_CPU_PPC32_MPC5200_V11, + UC_CPU_PPC32_MPC5200_V12, + UC_CPU_PPC32_MPC5200B_V20, + UC_CPU_PPC32_MPC5200B_V21, + UC_CPU_PPC32_E200Z5, + UC_CPU_PPC32_E200Z6, + UC_CPU_PPC32_E300C1, + UC_CPU_PPC32_E300C2, + UC_CPU_PPC32_E300C3, + UC_CPU_PPC32_E300C4, + UC_CPU_PPC32_MPC8343, + UC_CPU_PPC32_MPC8343A, + UC_CPU_PPC32_MPC8343E, + UC_CPU_PPC32_MPC8343EA, + UC_CPU_PPC32_MPC8347T, + UC_CPU_PPC32_MPC8347P, + UC_CPU_PPC32_MPC8347AT, + UC_CPU_PPC32_MPC8347AP, + UC_CPU_PPC32_MPC8347ET, + UC_CPU_PPC32_MPC8347EP, + UC_CPU_PPC32_MPC8347EAT, + UC_CPU_PPC32_MPC8347EAP, + UC_CPU_PPC32_MPC8349, + UC_CPU_PPC32_MPC8349A, + UC_CPU_PPC32_MPC8349E, + UC_CPU_PPC32_MPC8349EA, + UC_CPU_PPC32_MPC8377, + UC_CPU_PPC32_MPC8377E, + UC_CPU_PPC32_MPC8378, + UC_CPU_PPC32_MPC8378E, + UC_CPU_PPC32_MPC8379, + UC_CPU_PPC32_MPC8379E, + UC_CPU_PPC32_E500_V10, + UC_CPU_PPC32_E500_V20, + UC_CPU_PPC32_E500V2_V10, + UC_CPU_PPC32_E500V2_V20, + UC_CPU_PPC32_E500V2_V21, + UC_CPU_PPC32_E500V2_V22, + UC_CPU_PPC32_E500V2_V30, + UC_CPU_PPC32_E500MC, + UC_CPU_PPC32_MPC8533_V10, + UC_CPU_PPC32_MPC8533_V11, + UC_CPU_PPC32_MPC8533E_V10, + UC_CPU_PPC32_MPC8533E_V11, + UC_CPU_PPC32_MPC8540_V10, + UC_CPU_PPC32_MPC8540_V20, + UC_CPU_PPC32_MPC8540_V21, + UC_CPU_PPC32_MPC8541_V10, + UC_CPU_PPC32_MPC8541_V11, + UC_CPU_PPC32_MPC8541E_V10, + UC_CPU_PPC32_MPC8541E_V11, + UC_CPU_PPC32_MPC8543_V10, + UC_CPU_PPC32_MPC8543_V11, + UC_CPU_PPC32_MPC8543_V20, + UC_CPU_PPC32_MPC8543_V21, + UC_CPU_PPC32_MPC8543E_V10, + UC_CPU_PPC32_MPC8543E_V11, + UC_CPU_PPC32_MPC8543E_V20, + UC_CPU_PPC32_MPC8543E_V21, + UC_CPU_PPC32_MPC8544_V10, + UC_CPU_PPC32_MPC8544_V11, + UC_CPU_PPC32_MPC8544E_V10, + UC_CPU_PPC32_MPC8544E_V11, + UC_CPU_PPC32_MPC8545_V20, + UC_CPU_PPC32_MPC8545_V21, + UC_CPU_PPC32_MPC8545E_V20, + UC_CPU_PPC32_MPC8545E_V21, + UC_CPU_PPC32_MPC8547E_V20, + UC_CPU_PPC32_MPC8547E_V21, + UC_CPU_PPC32_MPC8548_V10, + UC_CPU_PPC32_MPC8548_V11, + UC_CPU_PPC32_MPC8548_V20, + UC_CPU_PPC32_MPC8548_V21, + UC_CPU_PPC32_MPC8548E_V10, + UC_CPU_PPC32_MPC8548E_V11, + UC_CPU_PPC32_MPC8548E_V20, + UC_CPU_PPC32_MPC8548E_V21, + UC_CPU_PPC32_MPC8555_V10, + UC_CPU_PPC32_MPC8555_V11, + UC_CPU_PPC32_MPC8555E_V10, + UC_CPU_PPC32_MPC8555E_V11, + UC_CPU_PPC32_MPC8560_V10, + UC_CPU_PPC32_MPC8560_V20, + UC_CPU_PPC32_MPC8560_V21, + UC_CPU_PPC32_MPC8567, + UC_CPU_PPC32_MPC8567E, + UC_CPU_PPC32_MPC8568, + UC_CPU_PPC32_MPC8568E, + UC_CPU_PPC32_MPC8572, + UC_CPU_PPC32_MPC8572E, + UC_CPU_PPC32_E600, + UC_CPU_PPC32_MPC8610, + UC_CPU_PPC32_MPC8641, + UC_CPU_PPC32_MPC8641D, + UC_CPU_PPC32_601_V0, + UC_CPU_PPC32_601_V1, + UC_CPU_PPC32_601_V2, + UC_CPU_PPC32_602, + UC_CPU_PPC32_603, + UC_CPU_PPC32_603E_V1_1, + UC_CPU_PPC32_603E_V1_2, + UC_CPU_PPC32_603E_V1_3, + UC_CPU_PPC32_603E_V1_4, + UC_CPU_PPC32_603E_V2_2, + UC_CPU_PPC32_603E_V3, + UC_CPU_PPC32_603E_V4, + UC_CPU_PPC32_603E_V4_1, + UC_CPU_PPC32_603E7, + UC_CPU_PPC32_603E7T, + UC_CPU_PPC32_603E7V, + UC_CPU_PPC32_603E7V1, + UC_CPU_PPC32_603E7V2, + UC_CPU_PPC32_603P, + UC_CPU_PPC32_604, + UC_CPU_PPC32_604E_V1_0, + UC_CPU_PPC32_604E_V2_2, + UC_CPU_PPC32_604E_V2_4, + UC_CPU_PPC32_604R, + UC_CPU_PPC32_740_V1_0, + UC_CPU_PPC32_750_V1_0, + UC_CPU_PPC32_740_V2_0, + UC_CPU_PPC32_750_V2_0, + UC_CPU_PPC32_740_V2_1, + UC_CPU_PPC32_750_V2_1, + UC_CPU_PPC32_740_V2_2, + UC_CPU_PPC32_750_V2_2, + UC_CPU_PPC32_740_V3_0, + UC_CPU_PPC32_750_V3_0, + UC_CPU_PPC32_740_V3_1, + UC_CPU_PPC32_750_V3_1, + UC_CPU_PPC32_740E, + UC_CPU_PPC32_750E, + UC_CPU_PPC32_740P, + UC_CPU_PPC32_750P, + UC_CPU_PPC32_750CL_V1_0, + UC_CPU_PPC32_750CL_V2_0, + UC_CPU_PPC32_750CX_V1_0, + UC_CPU_PPC32_750CX_V2_0, + UC_CPU_PPC32_750CX_V2_1, + UC_CPU_PPC32_750CX_V2_2, + UC_CPU_PPC32_750CXE_V2_1, + UC_CPU_PPC32_750CXE_V2_2, + UC_CPU_PPC32_750CXE_V2_3, + UC_CPU_PPC32_750CXE_V2_4, + UC_CPU_PPC32_750CXE_V2_4B, + UC_CPU_PPC32_750CXE_V3_0, + UC_CPU_PPC32_750CXE_V3_1, + UC_CPU_PPC32_750CXE_V3_1B, + UC_CPU_PPC32_750CXR, + UC_CPU_PPC32_750FL, + UC_CPU_PPC32_750FX_V1_0, + UC_CPU_PPC32_750FX_V2_0, + UC_CPU_PPC32_750FX_V2_1, + UC_CPU_PPC32_750FX_V2_2, + UC_CPU_PPC32_750FX_V2_3, + UC_CPU_PPC32_750GL, + UC_CPU_PPC32_750GX_V1_0, + UC_CPU_PPC32_750GX_V1_1, + UC_CPU_PPC32_750GX_V1_2, + UC_CPU_PPC32_750L_V2_0, + UC_CPU_PPC32_750L_V2_1, + UC_CPU_PPC32_750L_V2_2, + UC_CPU_PPC32_750L_V3_0, + UC_CPU_PPC32_750L_V3_2, + UC_CPU_PPC32_745_V1_0, + UC_CPU_PPC32_755_V1_0, + UC_CPU_PPC32_745_V1_1, + UC_CPU_PPC32_755_V1_1, + UC_CPU_PPC32_745_V2_0, + UC_CPU_PPC32_755_V2_0, + UC_CPU_PPC32_745_V2_1, + UC_CPU_PPC32_755_V2_1, + UC_CPU_PPC32_745_V2_2, + UC_CPU_PPC32_755_V2_2, + UC_CPU_PPC32_745_V2_3, + UC_CPU_PPC32_755_V2_3, + UC_CPU_PPC32_745_V2_4, + UC_CPU_PPC32_755_V2_4, + UC_CPU_PPC32_745_V2_5, + UC_CPU_PPC32_755_V2_5, + UC_CPU_PPC32_745_V2_6, + UC_CPU_PPC32_755_V2_6, + UC_CPU_PPC32_745_V2_7, + UC_CPU_PPC32_755_V2_7, + UC_CPU_PPC32_745_V2_8, + UC_CPU_PPC32_755_V2_8, + UC_CPU_PPC32_7400_V1_0, + UC_CPU_PPC32_7400_V1_1, + UC_CPU_PPC32_7400_V2_0, + UC_CPU_PPC32_7400_V2_1, + UC_CPU_PPC32_7400_V2_2, + UC_CPU_PPC32_7400_V2_6, + UC_CPU_PPC32_7400_V2_7, + UC_CPU_PPC32_7400_V2_8, + UC_CPU_PPC32_7400_V2_9, + UC_CPU_PPC32_7410_V1_0, + UC_CPU_PPC32_7410_V1_1, + UC_CPU_PPC32_7410_V1_2, + UC_CPU_PPC32_7410_V1_3, + UC_CPU_PPC32_7410_V1_4, + UC_CPU_PPC32_7448_V1_0, + UC_CPU_PPC32_7448_V1_1, + UC_CPU_PPC32_7448_V2_0, + UC_CPU_PPC32_7448_V2_1, + UC_CPU_PPC32_7450_V1_0, + UC_CPU_PPC32_7450_V1_1, + UC_CPU_PPC32_7450_V1_2, + UC_CPU_PPC32_7450_V2_0, + UC_CPU_PPC32_7450_V2_1, + UC_CPU_PPC32_7441_V2_1, + UC_CPU_PPC32_7441_V2_3, + UC_CPU_PPC32_7451_V2_3, + UC_CPU_PPC32_7441_V2_10, + UC_CPU_PPC32_7451_V2_10, + UC_CPU_PPC32_7445_V1_0, + UC_CPU_PPC32_7455_V1_0, + UC_CPU_PPC32_7445_V2_1, + UC_CPU_PPC32_7455_V2_1, + UC_CPU_PPC32_7445_V3_2, + UC_CPU_PPC32_7455_V3_2, + UC_CPU_PPC32_7445_V3_3, + UC_CPU_PPC32_7455_V3_3, + UC_CPU_PPC32_7445_V3_4, + UC_CPU_PPC32_7455_V3_4, + UC_CPU_PPC32_7447_V1_0, + UC_CPU_PPC32_7457_V1_0, + UC_CPU_PPC32_7447_V1_1, + UC_CPU_PPC32_7457_V1_1, + UC_CPU_PPC32_7457_V1_2, + UC_CPU_PPC32_7447A_V1_0, + UC_CPU_PPC32_7457A_V1_0, + UC_CPU_PPC32_7447A_V1_1, + UC_CPU_PPC32_7457A_V1_1, + UC_CPU_PPC32_7447A_V1_2, + UC_CPU_PPC32_7457A_V1_2, +} + +impl From for i32 { + fn from(value: PpcCpuModel) -> Self { + value as i32 + } +} + +impl From<&PpcCpuModel> for i32 { + fn from(value: &PpcCpuModel) -> Self { + (*value) as i32 + } +} + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Ppc64CpuModel { + UC_CPU_PPC64_E5500 = 0, + UC_CPU_PPC64_E6500, + UC_CPU_PPC64_970_V2_2, + UC_CPU_PPC64_970FX_V1_0, + UC_CPU_PPC64_970FX_V2_0, + UC_CPU_PPC64_970FX_V2_1, + UC_CPU_PPC64_970FX_V3_0, + UC_CPU_PPC64_970FX_V3_1, + UC_CPU_PPC64_970MP_V1_0, + UC_CPU_PPC64_970MP_V1_1, + UC_CPU_PPC64_POWER5_V2_1, + UC_CPU_PPC64_POWER7_V2_3, + UC_CPU_PPC64_POWER7_V2_1, + UC_CPU_PPC64_POWER8E_V2_1, + UC_CPU_PPC64_POWER8_V2_0, + UC_CPU_PPC64_POWER8NVL_V1_0, + UC_CPU_PPC64_POWER9_V1_0, + UC_CPU_PPC64_POWER9_V2_0, + UC_CPU_PPC64_POWER10_V1_0, +} + +impl From for i32 { + fn from(value: Ppc64CpuModel) -> Self { + value as i32 + } +} + +impl From<&Ppc64CpuModel> for i32 { + fn from(value: &Ppc64CpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/riscv.rs b/bindings/rust/src/riscv.rs index 80d4fe1fbb..073a4c30d0 100644 --- a/bindings/rust/src/riscv.rs +++ b/bindings/rust/src/riscv.rs @@ -1,5 +1,4 @@ #![allow(non_camel_case_types)] -// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT // RISCV registers #[repr(C)] @@ -344,3 +343,45 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Riscv32CpuModel { + UC_CPU_RISCV32_ANY = 0, + UC_CPU_RISCV32_BASE32, + UC_CPU_RISCV32_SIFIVE_E31, + UC_CPU_RISCV32_SIFIVE_U34, +} + +impl From for i32 { + fn from(value: Riscv32CpuModel) -> Self { + value as i32 + } +} + +impl From<&Riscv32CpuModel> for i32 { + fn from(value: &Riscv32CpuModel) -> Self { + (*value) as i32 + } +} + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Riscv64CpuModel { + UC_CPU_RISCV64_ANY = 0, + UC_CPU_RISCV64_BASE64, + UC_CPU_RISCV64_SIFIVE_E51, + UC_CPU_RISCV64_SIFIVE_U54, +} + +impl From for i32 { + fn from(value: Riscv64CpuModel) -> Self { + value as i32 + } +} + +impl From<&Riscv64CpuModel> for i32 { + fn from(value: &Riscv64CpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/s390x.rs b/bindings/rust/src/s390x.rs index b5e2f4a1ed..e158cf3d10 100644 --- a/bindings/rust/src/s390x.rs +++ b/bindings/rust/src/s390x.rs @@ -1,7 +1,8 @@ +#![allow(non_camel_case_types)] + // S390X registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] -#[allow(non_camel_case_types)] pub enum RegisterS390X { INVALID = 0, @@ -84,3 +85,57 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum S390xCpuModel { + UC_CPU_S390X_Z900 = 0, + UC_CPU_S390X_Z900_2, + UC_CPU_S390X_Z900_3, + UC_CPU_S390X_Z800, + UC_CPU_S390X_Z990, + UC_CPU_S390X_Z990_2, + UC_CPU_S390X_Z990_3, + UC_CPU_S390X_Z890, + UC_CPU_S390X_Z990_4, + UC_CPU_S390X_Z890_2, + UC_CPU_S390X_Z990_5, + UC_CPU_S390X_Z890_3, + UC_CPU_S390X_Z9EC, + UC_CPU_S390X_Z9EC_2, + UC_CPU_S390X_Z9BC, + UC_CPU_S390X_Z9EC_3, + UC_CPU_S390X_Z9BC_2, + UC_CPU_S390X_Z10EC, + UC_CPU_S390X_Z10EC_2, + UC_CPU_S390X_Z10BC, + UC_CPU_S390X_Z10EC_3, + UC_CPU_S390X_Z10BC_2, + UC_CPU_S390X_Z196, + UC_CPU_S390X_Z196_2, + UC_CPU_S390X_Z114, + UC_CPU_S390X_ZEC12, + UC_CPU_S390X_ZEC12_2, + UC_CPU_S390X_ZBC12, + UC_CPU_S390X_Z13, + UC_CPU_S390X_Z13_2, + UC_CPU_S390X_Z13S, + UC_CPU_S390X_Z14, + UC_CPU_S390X_Z14_2, + UC_CPU_S390X_Z14ZR1, + UC_CPU_S390X_GEN15A, + UC_CPU_S390X_GEN15B, + UC_CPU_S390X_QEMU, +} + +impl From for i32 { + fn from(value: S390xCpuModel) -> Self { + value as i32 + } +} + +impl From<&S390xCpuModel> for i32 { + fn from(value: &S390xCpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/sparc.rs b/bindings/rust/src/sparc.rs index e65b35892a..c0bd4f2abb 100644 --- a/bindings/rust/src/sparc.rs +++ b/bindings/rust/src/sparc.rs @@ -1,3 +1,5 @@ +#![allow(non_camel_case_types)] + // SPARC registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] @@ -108,3 +110,67 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Sparc32CpuModel { + UC_CPU_SPARC32_FUJITSU_MB86904 = 0, + UC_CPU_SPARC32_FUJITSU_MB86907, + UC_CPU_SPARC32_TI_MICROSPARC_I, + UC_CPU_SPARC32_TI_MICROSPARC_II, + UC_CPU_SPARC32_TI_MICROSPARC_IIEP, + UC_CPU_SPARC32_TI_SUPERSPARC_40, + UC_CPU_SPARC32_TI_SUPERSPARC_50, + UC_CPU_SPARC32_TI_SUPERSPARC_51, + UC_CPU_SPARC32_TI_SUPERSPARC_60, + UC_CPU_SPARC32_TI_SUPERSPARC_61, + UC_CPU_SPARC32_TI_SUPERSPARC_II, + UC_CPU_SPARC32_LEON2, + UC_CPU_SPARC32_LEON3, +} + +impl From for i32 { + fn from(value: Sparc32CpuModel) -> Self { + value as i32 + } +} + +impl From<&Sparc32CpuModel> for i32 { + fn from(value: &Sparc32CpuModel) -> Self { + (*value) as i32 + } +} + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Sparc64CpuModel { + UC_CPU_SPARC64_FUJITSU = 0, + UC_CPU_SPARC64_FUJITSU_III, + UC_CPU_SPARC64_FUJITSU_IV, + UC_CPU_SPARC64_FUJITSU_V, + UC_CPU_SPARC64_TI_ULTRASPARC_I, + UC_CPU_SPARC64_TI_ULTRASPARC_II, + UC_CPU_SPARC64_TI_ULTRASPARC_III, + UC_CPU_SPARC64_TI_ULTRASPARC_IIE, + UC_CPU_SPARC64_SUN_ULTRASPARC_III, + UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU, + UC_CPU_SPARC64_SUN_ULTRASPARC_IIII, + UC_CPU_SPARC64_SUN_ULTRASPARC_IV, + UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS, + UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS, + UC_CPU_SPARC64_SUN_ULTRASPARC_T1, + UC_CPU_SPARC64_SUN_ULTRASPARC_T2, + UC_CPU_SPARC64_NEC_ULTRASPARC_I, +} + +impl From for i32 { + fn from(value: Sparc64CpuModel) -> Self { + value as i32 + } +} + +impl From<&Sparc64CpuModel> for i32 { + fn from(value: &Sparc64CpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/tricore.rs b/bindings/rust/src/tricore.rs index 652108f3e2..3d03a21050 100644 --- a/bindings/rust/src/tricore.rs +++ b/bindings/rust/src/tricore.rs @@ -1,7 +1,8 @@ +#![allow(non_camel_case_types)] + // TRICORE registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] -#[allow(non_camel_case_types)] pub enum RegisterTRICORE { INVALID = 0, A0 = 1, @@ -135,3 +136,23 @@ impl From for i32 { r as i32 } } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum TricoreCpuModel { + UC_CPU_TRICORE_TC1796, + UC_CPU_TRICORE_TC1797, + UC_CPU_TRICORE_TC27X, +} + +impl From for i32 { + fn from(value: TricoreCpuModel) -> Self { + value as i32 + } +} + +impl From<&TricoreCpuModel> for i32 { + fn from(value: &TricoreCpuModel) -> Self { + (*value) as i32 + } +} diff --git a/bindings/rust/src/x86.rs b/bindings/rust/src/x86.rs index 1ce3adfcd4..111a395b0e 100644 --- a/bindings/rust/src/x86.rs +++ b/bindings/rust/src/x86.rs @@ -1,7 +1,9 @@ +#![allow(non_camel_case_types)] + // X86 registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] -#[allow(clippy::upper_case_acronyms, non_camel_case_types)] +#[allow(clippy::upper_case_acronyms)] pub enum RegisterX86 { INVALID = 0, AH = 1, @@ -278,3 +280,58 @@ pub struct X86Mmr { pub limit: u32, pub flags: u32, } + +#[repr(i32)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum X86CpuModel { + UC_CPU_X86_QEMU64 = 0, + UC_CPU_X86_PHENOM, + UC_CPU_X86_CORE2DUO, + UC_CPU_X86_KVM64, + UC_CPU_X86_QEMU32, + UC_CPU_X86_KVM32, + UC_CPU_X86_COREDUO, + UC_CPU_X86_486, + UC_CPU_X86_PENTIUM, + UC_CPU_X86_PENTIUM2, + UC_CPU_X86_PENTIUM3, + UC_CPU_X86_ATHLON, + UC_CPU_X86_N270, + UC_CPU_X86_CONROE, + UC_CPU_X86_PENRYN, + UC_CPU_X86_NEHALEM, + UC_CPU_X86_WESTMERE, + UC_CPU_X86_SANDYBRIDGE, + UC_CPU_X86_IVYBRIDGE, + UC_CPU_X86_HASWELL, + UC_CPU_X86_BROADWELL, + UC_CPU_X86_SKYLAKE_CLIENT, + UC_CPU_X86_SKYLAKE_SERVER, + UC_CPU_X86_CASCADELAKE_SERVER, + UC_CPU_X86_COOPERLAKE, + UC_CPU_X86_ICELAKE_CLIENT, + UC_CPU_X86_ICELAKE_SERVER, + UC_CPU_X86_DENVERTON, + UC_CPU_X86_SNOWRIDGE, + UC_CPU_X86_KNIGHTSMILL, + UC_CPU_X86_OPTERON_G1, + UC_CPU_X86_OPTERON_G2, + UC_CPU_X86_OPTERON_G3, + UC_CPU_X86_OPTERON_G4, + UC_CPU_X86_OPTERON_G5, + UC_CPU_X86_EPYC, + UC_CPU_X86_DHYANA, + UC_CPU_X86_EPYC_ROME, +} + +impl From for i32 { + fn from(value: X86CpuModel) -> Self { + value as i32 + } +} + +impl From<&X86CpuModel> for i32 { + fn from(value: &X86CpuModel) -> Self { + (*value) as i32 + } +}