• When method chaining syntax for updating registers Aug 2
  • Add a notion of enum Aug 7
  • Support AugAssign in m.circuit.combinational Aug 21
  • Add options to generate verilog as separate files per module or modules organized by original source file Aug 22
  • m.Bits vs m.bits is confusing - should make clear error messages for this case Aug 22
  • Clarify the difference between interface and IO Aug 23
  • Add FSM example as notebook Aug 2
  • Add a set of notebooks to introduces concepts specifically oriented towards Verilog designers Aug 2
  • When method chaining syntax for updating registers Aug 2
  • Register should work with the _type parameter Aug 22
  • [Design Proposal] Two separate modes for using tester: Fast compiled mode and interactive/debug mode Aug 10
  • Semantics mismatch between generate_function_test_vectors and backends Aug 16
  • Add a Bit type Aug 15
  • Validate module/generator arguments and throw exceptions Aug 15
  • Inline verilog primitives like `&` and `+` Aug 16