Permalink
Browse files

Land the Fan (disabled)

R=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/426233002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
  • Loading branch information...
danno@chromium.org
danno@chromium.org committed Jul 30, 2014
1 parent 50869d7 commit a1383e2250dc5b56b777f2057f1600537f02023e
Showing 323 changed files with 71,289 additions and 1,719 deletions.
View
@@ -452,6 +452,9 @@
'defines': [
'WIN32',
],
# 4351: VS 2005 and later are warning us that they've fixed a bug
# present in VS 2003 and earlier.
'msvs_disabled_warnings': [4351],
'msvs_configuration_attributes': {
'OutputDirectory': '<(DEPTH)\\build\\$(ConfigurationName)',
'IntermediateDirectory': '$(OutDir)\\obj\\$(ProjectName)',
View
@@ -5596,7 +5596,7 @@ class Internals {
static const int kJSObjectHeaderSize = 3 * kApiPointerSize;
static const int kFixedArrayHeaderSize = 2 * kApiPointerSize;
static const int kContextHeaderSize = 2 * kApiPointerSize;
static const int kContextEmbedderDataIndex = 76;
static const int kContextEmbedderDataIndex = 95;
static const int kFullStringRepresentationMask = 0x07;
static const int kStringEncodingMask = 0x4;
static const int kExternalTwoByteRepresentationTag = 0x02;
View
@@ -1544,6 +1544,15 @@ void Assembler::sdiv(Register dst, Register src1, Register src2,
}
void Assembler::udiv(Register dst, Register src1, Register src2,
Condition cond) {
ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
ASSERT(IsEnabled(SUDIV));
emit(cond | B26 | B25 | B24 | B21 | B20 | dst.code() * B16 | 0xf * B12 |
src2.code() * B8 | B4 | src1.code());
}
void Assembler::mul(Register dst, Register src1, Register src2,
SBit s, Condition cond) {
ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
@@ -2156,9 +2165,14 @@ void Assembler::vldr(const DwVfpRegister dst,
void Assembler::vldr(const DwVfpRegister dst,
const MemOperand& operand,
const Condition cond) {
ASSERT(!operand.rm().is_valid());
ASSERT(operand.am_ == Offset);
vldr(dst, operand.rn(), operand.offset(), cond);
if (operand.rm().is_valid()) {
add(ip, operand.rn(),
Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
vldr(dst, ip, 0, cond);
} else {
vldr(dst, operand.rn(), operand.offset(), cond);
}
}
@@ -2199,9 +2213,14 @@ void Assembler::vldr(const SwVfpRegister dst,
void Assembler::vldr(const SwVfpRegister dst,
const MemOperand& operand,
const Condition cond) {
ASSERT(!operand.rm().is_valid());
ASSERT(operand.am_ == Offset);
vldr(dst, operand.rn(), operand.offset(), cond);
if (operand.rm().is_valid()) {
add(ip, operand.rn(),
Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
vldr(dst, ip, 0, cond);
} else {
vldr(dst, operand.rn(), operand.offset(), cond);
}
}
@@ -2242,9 +2261,14 @@ void Assembler::vstr(const DwVfpRegister src,
void Assembler::vstr(const DwVfpRegister src,
const MemOperand& operand,
const Condition cond) {
ASSERT(!operand.rm().is_valid());
ASSERT(operand.am_ == Offset);
vstr(src, operand.rn(), operand.offset(), cond);
if (operand.rm().is_valid()) {
add(ip, operand.rn(),
Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
vstr(src, ip, 0, cond);
} else {
vstr(src, operand.rn(), operand.offset(), cond);
}
}
@@ -2284,9 +2308,14 @@ void Assembler::vstr(const SwVfpRegister src,
void Assembler::vstr(const SwVfpRegister src,
const MemOperand& operand,
const Condition cond) {
ASSERT(!operand.rm().is_valid());
ASSERT(operand.am_ == Offset);
vstr(src, operand.rn(), operand.offset(), cond);
if (operand.rm().is_valid()) {
add(ip, operand.rn(),
Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
vstr(src, ip, 0, cond);
} else {
vstr(src, operand.rn(), operand.offset(), cond);
}
}
@@ -3125,6 +3154,7 @@ bool Assembler::IsNop(Instr instr, int type) {
}
// static
bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
uint32_t dummy1;
uint32_t dummy2;
View
@@ -922,6 +922,35 @@ class Assembler : public AssemblerBase {
void mvn(Register dst, const Operand& src,
SBit s = LeaveCC, Condition cond = al);
// Shift instructions
void asr(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
Condition cond = al) {
if (src2.is_reg()) {
mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
} else {
mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
}
}
void lsl(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
Condition cond = al) {
if (src2.is_reg()) {
mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
} else {
mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
}
}
void lsr(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
Condition cond = al) {
if (src2.is_reg()) {
mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
} else {
mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
}
}
// Multiply instructions
void mla(Register dst, Register src1, Register src2, Register srcA,
@@ -933,6 +962,8 @@ class Assembler : public AssemblerBase {
void sdiv(Register dst, Register src1, Register src2,
Condition cond = al);
void udiv(Register dst, Register src1, Register src2, Condition cond = al);
void mul(Register dst, Register src1, Register src2,
SBit s = LeaveCC, Condition cond = al);
@@ -1290,7 +1321,7 @@ class Assembler : public AssemblerBase {
}
// Check whether an immediate fits an addressing mode 1 instruction.
bool ImmediateFitsAddrMode1Instruction(int32_t imm32);
static bool ImmediateFitsAddrMode1Instruction(int32_t imm32);
// Check whether an immediate fits an addressing mode 2 instruction.
bool ImmediateFitsAddrMode2Instruction(int32_t imm32);
Oops, something went wrong.

0 comments on commit a1383e2

Please sign in to comment.