From ecc22efdbdf491fc94252bb6d760a5864709849f Mon Sep 17 00:00:00 2001
From: Prateek Gupta <64007722+Prateek219@users.noreply.github.com>
Date: Fri, 10 Jul 2020 14:24:30 +0530
Subject: [PATCH] Update and rename ripple_carry_adder.v to
 ripple_carry_adder_tb.v

---
 memory/testbenches/ripple_carry_adder.v    |  1 -
 memory/testbenches/ripple_carry_adder_tb.v | 35 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 delete mode 100644 memory/testbenches/ripple_carry_adder.v
 create mode 100644 memory/testbenches/ripple_carry_adder_tb.v

diff --git a/memory/testbenches/ripple_carry_adder.v b/memory/testbenches/ripple_carry_adder.v
deleted file mode 100644
index f2ad6c7..0000000
--- a/memory/testbenches/ripple_carry_adder.v
+++ /dev/null
@@ -1 +0,0 @@
-c
diff --git a/memory/testbenches/ripple_carry_adder_tb.v b/memory/testbenches/ripple_carry_adder_tb.v
new file mode 100644
index 0000000..1b6999a
--- /dev/null
+++ b/memory/testbenches/ripple_carry_adder_tb.v
@@ -0,0 +1,35 @@
+module tb();
+  
+  reg[5:0] X,Y; //reg X,Y,C_in are register to store information
+  reg C_in;
+  wire C_out ;
+  wire [5:0] S;  //wire is used to pass on information from c_out of one full adder to other full adder's C_in
+  
+  ripple_adder dut(
+    .X(X),                       //preparing X,Y,C_in,C_out for test cases
+    .Y(Y),
+    .C_in(C_in),
+    .S(S),
+    .C_out(C_out)
+  );
+  initial begin
+    $dumpvars(1,tb);         //dumping variable to conduct simulation
+    #5;
+    X=0;
+    Y=0;
+    C_in=0;
+    #5;
+    X=4;
+    Y=5;
+    C_in=1;
+    #5
+    X=4'b1000;
+    Y=4'b0100;
+    #5
+    C_in=1;
+    
+  end
+  
+endmodule
+    
+