From 962454d69acabc977d91b30cb71f8681853ac059 Mon Sep 17 00:00:00 2001 From: Arjan van Vught Date: Sun, 14 Jan 2024 15:42:45 +0100 Subject: [PATCH] Sync with local development --- firmware-template-gd32/Includes.mk | 3 +- firmware-template-gd32/Rules.mk | 2 +- firmware-template-gd32/lib/Rules.mk | 4 +- .../firmware/main.cpp | 13 - .../include/sofware_version_id.h | 2 +- .../firmware/main.cpp | 11 - .../include/sofware_version_id.h | 2 +- .../firmware/main.cpp | 11 - .../include/sofware_version_id.h | 2 +- gd32_emac_ddp_pixel_multi/firmware/main.cpp | 11 - .../include/sofware_version_id.h | 2 +- gd32_emac_debug/firmware/main.cpp | 11 - .../firmware/main.cpp | 11 - .../include/sofware_version_id.h | 3 +- gd32_emac_e131_pixel_multi/firmware/main.cpp | 11 - .../include/sofware_version_id.h | 3 +- lib-artnet/Rules.mk | 2 +- lib-artnet/include/artnetpolltable.h | 21 +- lib-artnet/src/artnetconst.cpp | 4 +- .../src/controller/artnetcontroller.cpp | 19 +- lib-artnet/src/controller/artnetpolltable.cpp | 30 +- lib-artnet/src/node/artnetnode.cpp | 12 +- lib-c++/src/delete.cpp | 10 +- lib-c++/src/dso_handle.cpp | 2 +- lib-c++/src/new.cpp | 4 +- lib-c++/src/purecall.cpp | 2 +- lib-configstore/Rules.mk | 2 - lib-ddp/Rules.mk | 3 +- lib-displayudf/Rules.mk | 2 - lib-dmx/src/gd32/dmx.cpp | 25 +- .../{e131bridgeconst.h => e131const.h} | 12 +- .../e131bridgeconst.cpp => e131const.cpp} | 8 +- lib-e131/src/node/e131bridgeprint.cpp | 7 +- lib-flash/src/spi/gd32/spi_flash.cpp | 12 +- lib-flash/src/spi/gigadevice.cpp | 8 +- .../CMSIS/GD/GD32F4xx/Include/gd32f4xx.h | 25 +- .../GD/GD32F4xx/Source/system_gd32f4xx.c | 279 ++- .../Include/gd32f4xx_adc.h | 580 ++++--- .../Include/gd32f4xx_can.h | 468 +++--- .../Include/gd32f4xx_crc.h | 14 +- .../Include/gd32f4xx_ctc.h | 14 +- .../Include/gd32f4xx_dac.h | 224 ++- .../Include/gd32f4xx_dbg.h | 25 +- .../Include/gd32f4xx_dci.h | 6 +- .../Include/gd32f4xx_dma.h | 151 +- .../Include/gd32f4xx_enet.h | 18 +- .../Include/gd32f4xx_exmc.h | 84 +- .../Include/gd32f4xx_exti.h | 84 +- .../Include/gd32f4xx_fmc.h | 155 +- .../Include/gd32f4xx_fwdgt.h | 17 +- .../Include/gd32f4xx_gpio.h | 46 +- .../Include/gd32f4xx_i2c.h | 471 +++--- .../Include/gd32f4xx_ipa.h | 116 +- .../Include/gd32f4xx_iref.h | 8 +- .../Include/gd32f4xx_misc.h | 31 +- .../Include/gd32f4xx_pmu.h | 216 +-- .../Include/gd32f4xx_rcu.h | 63 +- .../Include/gd32f4xx_rtc.h | 8 +- .../Include/gd32f4xx_sdio.h | 74 +- .../Include/gd32f4xx_spi.h | 156 +- .../Include/gd32f4xx_syscfg.h | 6 +- .../Include/gd32f4xx_timer.h | 69 +- .../Include/gd32f4xx_tli.h | 151 +- .../Include/gd32f4xx_trng.h | 48 +- .../Include/gd32f4xx_usart.h | 254 ++- .../Include/gd32f4xx_wwdgt.h | 15 +- .../Source/gd32f4xx_adc.c | 1020 ++++++----- .../Source/gd32f4xx_can.c | 652 +++---- .../Source/gd32f4xx_crc.c | 53 +- .../Source/gd32f4xx_ctc.c | 111 +- .../Source/gd32f4xx_dac.c | 256 ++- .../Source/gd32f4xx_dbg.c | 142 +- .../Source/gd32f4xx_dci.c | 88 +- .../Source/gd32f4xx_dma.c | 540 +++--- .../Source/gd32f4xx_enet.c | 1495 ++++++++--------- .../Source/gd32f4xx_exmc.c | 561 ++++--- .../Source/gd32f4xx_exti.c | 91 +- .../Source/gd32f4xx_fmc.c | 488 +++--- .../Source/gd32f4xx_fwdgt.c | 78 +- .../Source/gd32f4xx_gpio.c | 150 +- .../Source/gd32f4xx_i2c.c | 409 ++--- .../Source/gd32f4xx_ipa.c | 196 ++- .../Source/gd32f4xx_iref.c | 48 +- .../Source/gd32f4xx_misc.c | 90 +- .../Source/gd32f4xx_pmu.c | 327 ++-- .../Source/gd32f4xx_rcu.c | 730 ++++---- .../Source/gd32f4xx_rtc.c | 396 +++-- .../Source/gd32f4xx_sdio.c | 50 +- .../Source/gd32f4xx_spi.c | 409 ++--- .../Source/gd32f4xx_syscfg.c | 54 +- .../Source/gd32f4xx_timer.c | 750 +++++---- .../Source/gd32f4xx_tli.c | 247 ++- .../Source/gd32f4xx_trng.c | 86 +- .../Source/gd32f4xx_usart.c | 247 ++- .../Source/gd32f4xx_wwdgt.c | 36 +- .../device/class/audio/Include/audio_core.h | 5 +- .../class/audio/Include/audio_out_itf.h | 5 +- .../device/class/audio/Source/audio_core.c | 5 +- .../device/class/audio/Source/audio_out_itf.c | 5 +- .../device/class/cdc/Include/cdc_acm_core.h | 10 +- .../device/class/cdc/Source/cdc_acm_core.c | 197 +-- .../device/class/dfu/Include/dfu_core.h | 18 +- .../device/class/dfu/Include/dfu_mem.h | 8 +- .../device/class/dfu/Source/dfu_core.c | 170 +- .../device/class/dfu/Source/dfu_mem.c | 19 +- .../class/hid/Include/custom_hid_core.h | 5 +- .../class/hid/Include/standard_hid_core.h | 5 +- .../device/class/hid/Source/custom_hid_core.c | 119 +- .../class/hid/Source/standard_hid_core.c | 137 +- .../device/class/iap/Include/usb_iap_core.h | 5 +- .../device/class/iap/Source/usb_iap_core.c | 151 +- .../device/class/msc/Include/usbd_msc_bbb.h | 9 +- .../device/class/msc/Include/usbd_msc_core.h | 5 +- .../device/class/msc/Include/usbd_msc_mem.h | 7 +- .../device/class/msc/Include/usbd_msc_scsi.h | 5 +- .../device/class/msc/Source/usbd_msc_bbb.c | 37 +- .../device/class/msc/Source/usbd_msc_core.c | 80 +- .../device/class/msc/Source/usbd_msc_scsi.c | 13 +- .../class/printer/Include/printer_core.h | 5 +- .../class/printer/Source/printer_core.c | 121 +- .../device/core/Include/usbd_core.h | 7 +- .../device/core/Include/usbd_enum.h | 7 +- .../device/core/Include/usbd_transc.h | 5 +- .../device/core/Source/usbd_core.c | 7 +- .../device/core/Source/usbd_enum.c | 7 +- .../device/core/Source/usbd_transc.c | 5 +- .../driver/Include/drv_usb_core.h | 21 +- .../driver/Include/drv_usb_dev.h | 5 +- .../driver/Include/drv_usb_host.h | 7 +- .../driver/Include/drv_usb_hw.h | 22 +- .../driver/Include/drv_usb_regs.h | 27 +- .../driver/Include/drv_usbd_int.h | 5 +- .../driver/Include/drv_usbh_int.h | 5 +- .../driver/Source/drv_usb_core.c | 38 +- .../driver/Source/drv_usb_dev.c | 25 +- .../driver/Source/drv_usb_host.c | 17 +- .../driver/Source/drv_usbd_int.c | 34 +- .../driver/Source/drv_usbh_int.c | 57 +- .../host/class/hid/Include/usbh_hid_core.h | 7 +- .../class/hid/Include/usbh_standard_hid.h | 5 +- .../host/class/hid/Source/usbh_hid_core.c | 14 +- .../host/class/hid/Source/usbh_standard_hid.c | 55 +- .../host/class/msc/Include/usbh_msc_bbb.h | 17 +- .../host/class/msc/Include/usbh_msc_core.h | 13 +- .../host/class/msc/Include/usbh_msc_scsi.h | 7 +- .../host/class/msc/Source/usbh_msc_bbb.c | 129 +- .../host/class/msc/Source/usbh_msc_core.c | 201 ++- .../host/class/msc/Source/usbh_msc_fatfs.c | 23 +- .../host/class/msc/Source/usbh_msc_scsi.c | 195 ++- .../host/core/Include/usbh_core.h | 23 +- .../host/core/Include/usbh_enum.h | 5 +- .../host/core/Include/usbh_pipe.h | 5 +- .../host/core/Include/usbh_transc.h | 5 +- .../host/core/Source/usbh_core.c | 62 +- .../host/core/Source/usbh_enum.c | 15 +- .../host/core/Source/usbh_pipe.c | 9 +- .../host/core/Source/usbh_transc.c | 21 +- .../ustd/class/cdc/usb_cdc.h | 5 +- .../ustd/class/hid/usb_hid.h | 7 +- .../ustd/class/msc/msc_bbb.h | 9 +- .../ustd/class/msc/msc_scsi.h | 5 +- .../ustd/class/msc/usb_msc.h | 5 +- .../ustd/common/usb_ch9_std.h | 7 +- lib-gd32/include/board/gd32f470z_eval.h | 194 +++ lib-gd32/include/gd32.h | 12 +- lib-gd32/include/gd32_board.h | 4 +- lib-gd32/include/gd32_gpio.h | 4 +- lib-gd32/include/mcu/gd32f4xx_mcu.h | 21 +- lib-hal/debug/emac/gd32/emac_debug.cpp | 0 lib-hal/debug/i2c/i2cdetect.cpp | 2 +- lib-hal/debug/i2c/i2cdetect.h | 2 +- lib-hal/debug/stack/stack_debug.cpp | 3 +- lib-hal/device/usb/host/gd32/usb_host.cpp | 11 +- lib-hal/posix/file.c | 1 + lib-network/config/net_config.h | 5 +- lib-network/src/apps/tftp/tftpdaemon.cpp | 2 +- lib-network/src/emac/gd32/emac.cpp | 29 +- lib-properties/include/devicesparamsconst.h | 4 +- lib-properties/src/devicesparamsconst.cpp | 4 +- lib-rdm/Rules.mk | 2 +- lib-rdmnet/Rules.mk | 3 +- lib-remoteconfig/Rules.mk | 4 +- lib-remoteconfig/include/httpd/http.h | 52 + lib-remoteconfig/include/httpd/httpd.h | 66 +- .../include/httpd/httpdhandlerequest.h | 76 + lib-remoteconfig/include/remoteconfig.h | 31 +- lib-remoteconfig/src/httpd/httpd.cpp | 500 +----- .../src/httpd/httpdhandlerequest.cpp | 536 ++++++ lib-remoteconfig/src/remoteconfig.cpp | 54 +- lib-ws28xx/Makefile.GD32 | 2 +- 190 files changed, 9276 insertions(+), 8607 deletions(-) mode change 100644 => 100755 lib-c++/src/dso_handle.cpp rename lib-e131/include/{e131bridgeconst.h => e131const.h} (84%) rename lib-e131/src/{node/e131bridgeconst.cpp => e131const.cpp} (86%) mode change 100644 => 100755 mode change 100644 => 100755 lib-flash/src/spi/gigadevice.cpp create mode 100644 lib-gd32/include/board/gd32f470z_eval.h mode change 100644 => 100755 lib-hal/debug/emac/gd32/emac_debug.cpp mode change 100644 => 100755 lib-hal/debug/i2c/i2cdetect.cpp mode change 100644 => 100755 lib-hal/debug/i2c/i2cdetect.h mode change 100644 => 100755 lib-hal/debug/stack/stack_debug.cpp mode change 100644 => 100755 lib-hal/posix/file.c create mode 100755 lib-remoteconfig/include/httpd/http.h create mode 100755 lib-remoteconfig/include/httpd/httpdhandlerequest.h create mode 100755 lib-remoteconfig/src/httpd/httpdhandlerequest.cpp diff --git a/firmware-template-gd32/Includes.mk b/firmware-template-gd32/Includes.mk index 95b8d6f..7826240 100644 --- a/firmware-template-gd32/Includes.mk +++ b/firmware-template-gd32/Includes.mk @@ -1,6 +1,7 @@ $(info "Includes.mk") -INCLUDES:=-I./include -I../include -I../lib-configstore/include -I../lib-flash/include -I../lib-flashcode/include -I../lib-hal/include -I../lib-debug/include +INCLUDES:=-I./include -I../include +INCLUDES+=-I../lib-debug/include INCLUDES+=$(addprefix -I,$(EXTRA_INCLUDES)) INCLUDES+=-I../firmware-template-gd32/include INCLUDES+=-I../firmware-template-gd32/template diff --git a/firmware-template-gd32/Rules.mk b/firmware-template-gd32/Rules.mk index a379d77..b34cda2 100644 --- a/firmware-template-gd32/Rules.mk +++ b/firmware-template-gd32/Rules.mk @@ -62,7 +62,7 @@ COPS+=-ffunction-sections -fdata-sections COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion COPS+=-Wduplicated-cond -Wlogical-op -CPPOPS=-std=c++11 +CPPOPS=-std=c++20 CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables CPPOPS+=-Wuseless-cast -Wold-style-cast CPPOPS+=-fno-threadsafe-statics diff --git a/firmware-template-gd32/lib/Rules.mk b/firmware-template-gd32/lib/Rules.mk index 75d5ad2..0bfd3fd 100644 --- a/firmware-template-gd32/lib/Rules.mk +++ b/firmware-template-gd32/lib/Rules.mk @@ -26,6 +26,8 @@ SRCDIR=src src/gd32 $(EXTRA_SRCDIR) include ../firmware-template-gd32/Includes.mk +INCLUDES+=-I../lib-configstore/include -I../lib-device/include -I../lib-display/include -I../lib-flash/include -I../lib-flashcode/include -I../lib-hal/include -I../lib-lightset/include -I../lib-network/include + DEFINES:=$(addprefix -D,$(DEFINES)) DEFINES+=-D_TIME_STAMP_YEAR_=$(shell date +"%Y") -D_TIME_STAMP_MONTH_=$(shell date +"%-m") -D_TIME_STAMP_DAY_=$(shell date +"%-d") @@ -39,7 +41,7 @@ COPS+=-ffunction-sections -fdata-sections COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion COPS+=-Wduplicated-cond -Wlogical-op -CPPOPS=-std=c++11 +CPPOPS=-std=c++20 CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables CPPOPS+=-Wuseless-cast -Wold-style-cast CPPOPS+=-fno-threadsafe-statics diff --git a/gd32_emac_artnet_pixel_dmx_multi/firmware/main.cpp b/gd32_emac_artnet_pixel_dmx_multi/firmware/main.cpp index 7356d2c..35d0f04 100644 --- a/gd32_emac_artnet_pixel_dmx_multi/firmware/main.cpp +++ b/gd32_emac_artnet_pixel_dmx_multi/firmware/main.cpp @@ -32,10 +32,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -101,12 +97,6 @@ void main() { fw.Print("Art-Net 4 Pixel controller {16x 4 Universes} / 2x DMX"); nw.Print(); - display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW); - -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - display.TextStatus(ArtNetMsgConst::PARAMS, Display7SegmentMessage::INFO_NODE_PARMAMS, CONSOLE_YELLOW); ArtNetNode node; @@ -280,9 +270,6 @@ void main() { mDns.Run(); #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_artnet_pixel_dmx_multi/include/sofware_version_id.h b/gd32_emac_artnet_pixel_dmx_multi/include/sofware_version_id.h index 9b0e87b..b0e2e07 100644 --- a/gd32_emac_artnet_pixel_dmx_multi/include/sofware_version_id.h +++ b/gd32_emac_artnet_pixel_dmx_multi/include/sofware_version_id.h @@ -1 +1 @@ -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704222230; +constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704725179; diff --git a/gd32_emac_artnet_pixel_multi/firmware/main.cpp b/gd32_emac_artnet_pixel_multi/firmware/main.cpp index 8718351..17e69ff 100644 --- a/gd32_emac_artnet_pixel_multi/firmware/main.cpp +++ b/gd32_emac_artnet_pixel_multi/firmware/main.cpp @@ -32,10 +32,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -94,10 +90,6 @@ void main() { fw.Print("Art-Net 4 Pixel controller {8x 4 Universes}"); nw.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - display.TextStatus(ArtNetMsgConst::PARAMS, Display7SegmentMessage::INFO_NODE_PARMAMS, CONSOLE_YELLOW); ArtNetNode node; @@ -230,9 +222,6 @@ void main() { mDns.Run(); #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h b/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h index e92809a..68b52b5 100644 --- a/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h +++ b/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h @@ -1 +1 @@ -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704222259; +constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1702811908; diff --git a/gd32_emac_ddp_pixel_dmx_multi/firmware/main.cpp b/gd32_emac_ddp_pixel_dmx_multi/firmware/main.cpp index 74b6a35..6a3aab7 100644 --- a/gd32_emac_ddp_pixel_dmx_multi/firmware/main.cpp +++ b/gd32_emac_ddp_pixel_dmx_multi/firmware/main.cpp @@ -33,10 +33,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -98,10 +94,6 @@ void main() { mDns.ServiceRecordAdd(nullptr, mdns::Services::DDP, "type=display"); mDns.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - // LightSet A - Pixel - 64 Universes PixelDmxConfiguration pixelDmxConfiguration; @@ -223,9 +215,6 @@ void main() { mDns.Run(); #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_ddp_pixel_dmx_multi/include/sofware_version_id.h b/gd32_emac_ddp_pixel_dmx_multi/include/sofware_version_id.h index 735cbc0..081a99f 100644 --- a/gd32_emac_ddp_pixel_dmx_multi/include/sofware_version_id.h +++ b/gd32_emac_ddp_pixel_dmx_multi/include/sofware_version_id.h @@ -1 +1 @@ -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704222269; +constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1702811913; diff --git a/gd32_emac_ddp_pixel_multi/firmware/main.cpp b/gd32_emac_ddp_pixel_multi/firmware/main.cpp index 5dc6729..6a8f18e 100644 --- a/gd32_emac_ddp_pixel_multi/firmware/main.cpp +++ b/gd32_emac_ddp_pixel_multi/firmware/main.cpp @@ -33,10 +33,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -92,10 +88,6 @@ void main() { mDns.ServiceRecordAdd(nullptr, mdns::Services::DDP, "type=display"); mDns.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - PixelDmxConfiguration pixelDmxConfiguration; PixelDmxParams pixelDmxParams; @@ -196,9 +188,6 @@ void main() { mDns.Run(); #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h b/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h index ecb17bc..22af23d 100644 --- a/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h +++ b/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h @@ -1 +1 @@ -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704222278; +constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1702811915; diff --git a/gd32_emac_debug/firmware/main.cpp b/gd32_emac_debug/firmware/main.cpp index 0ec954f..fa6b9d2 100644 --- a/gd32_emac_debug/firmware/main.cpp +++ b/gd32_emac_debug/firmware/main.cpp @@ -38,10 +38,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -115,10 +111,6 @@ void main() { fw.Print("Debug"); nw.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - display.SetTitle("Debug"); display.Set(2, displayudf::Labels::HOSTNAME); display.Set(3, displayudf::Labels::IP); @@ -164,9 +156,6 @@ void main() { remoteConfig.Run(); configStore.Flash(); mDns.Run(); -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); -#endif display.Run(); hw.Run(); diff --git a/gd32_emac_e131_pixel_dmx_multi/firmware/main.cpp b/gd32_emac_e131_pixel_dmx_multi/firmware/main.cpp index 8099c50..e0aa5c3 100644 --- a/gd32_emac_e131_pixel_dmx_multi/firmware/main.cpp +++ b/gd32_emac_e131_pixel_dmx_multi/firmware/main.cpp @@ -31,10 +31,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -100,10 +96,6 @@ void main() { fw.Print("sACN E1.31 Pixel controller {8x 4 Universes} / 2x DMX"); nw.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - display.TextStatus(E131MsgConst::PARAMS, Display7SegmentMessage::INFO_BRIDGE_PARMAMS, CONSOLE_YELLOW); E131Bridge bridge; @@ -277,9 +269,6 @@ void main() { mDns.Run(); #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_e131_pixel_dmx_multi/include/sofware_version_id.h b/gd32_emac_e131_pixel_dmx_multi/include/sofware_version_id.h index 8bb33dd..c08f99c 100644 --- a/gd32_emac_e131_pixel_dmx_multi/include/sofware_version_id.h +++ b/gd32_emac_e131_pixel_dmx_multi/include/sofware_version_id.h @@ -1 +1,2 @@ -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704222298; +// Generated do 14 sep 2023 12:39:45 CEST +constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1694687985; diff --git a/gd32_emac_e131_pixel_multi/firmware/main.cpp b/gd32_emac_e131_pixel_multi/firmware/main.cpp index 5058373..da444cd 100644 --- a/gd32_emac_e131_pixel_multi/firmware/main.cpp +++ b/gd32_emac_e131_pixel_multi/firmware/main.cpp @@ -31,10 +31,6 @@ #include "mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" -#endif - #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" @@ -94,10 +90,6 @@ void main() { fw.Print("sACN E1.31 Pixel controller {8x 4 Universes}"); nw.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - display.TextStatus(E131MsgConst::PARAMS, Display7SegmentMessage::INFO_BRIDGE_PARMAMS, CONSOLE_YELLOW); E131Bridge bridge; @@ -225,9 +217,6 @@ void main() { mDns.Run(); #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_e131_pixel_multi/include/sofware_version_id.h b/gd32_emac_e131_pixel_multi/include/sofware_version_id.h index bad0d6c..f678b71 100644 --- a/gd32_emac_e131_pixel_multi/include/sofware_version_id.h +++ b/gd32_emac_e131_pixel_multi/include/sofware_version_id.h @@ -1 +1,2 @@ -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1704222308; +// Generated do 14 sep 2023 12:39:46 CEST +constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1694687986; diff --git a/lib-artnet/Rules.mk b/lib-artnet/Rules.mk index f256058..d788e0e 100644 --- a/lib-artnet/Rules.mk +++ b/lib-artnet/Rules.mk @@ -1,4 +1,4 @@ -EXTRA_INCLUDES+=../lib-lightset/include ../lib-properties/include ../lib-hal/include ../lib-network/include ../lib-configstore/include +EXTRA_INCLUDES+=../lib-lightset/include ../lib-properties/include ../lib-network/include ifneq ($(MAKE_FLAGS),) ifeq ($(findstring NODE_ARTNET,$(MAKE_FLAGS)), NODE_ARTNET) diff --git a/lib-artnet/include/artnetpolltable.h b/lib-artnet/include/artnetpolltable.h index 5e38eeb..7e4a361 100644 --- a/lib-artnet/include/artnetpolltable.h +++ b/lib-artnet/include/artnetpolltable.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,16 +33,13 @@ #include "artnet.h" -enum TArtNetPollInterval { - ARTNET_POLL_INTERVAL_SECONDS = 8, - ARTNET_POLL_INTERVAL_MILLIS = (ARTNET_POLL_INTERVAL_SECONDS * 1000) -}; - -enum TArtNetPollTableSizes { - ARTNET_POLL_TABLE_SIZE_ENRIES = 255, - ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES = 64, - ARTNET_POLL_TABLE_SIZE_UNIVERSES = 512 -}; +namespace artnet { +static constexpr uint32_t POLL_INTERVAL_SECONDS = 8; +static constexpr uint32_t POLL_INTERVAL_MILLIS = (POLL_INTERVAL_SECONDS * 1000U); +static constexpr uint32_t POLL_TABLE_SIZE_ENRIES = 255; +static constexpr uint32_t POLL_TABLE_SIZE_NODE_UNIVERSES = 64; +static constexpr uint32_t POLL_TABLE_SIZE_UNIVERSES = 512; +} // namespace artnet struct TArtNetNodeEntryUniverse { uint32_t nLastUpdateMillis; @@ -55,7 +52,7 @@ struct TArtNetNodeEntry { uint8_t ShortName[artnet::SHORT_NAME_LENGTH]; uint8_t LongName[artnet::LONG_NAME_LENGTH]; uint16_t nUniversesCount; - struct TArtNetNodeEntryUniverse Universe[ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES]; + struct TArtNetNodeEntryUniverse Universe[artnet::POLL_TABLE_SIZE_NODE_UNIVERSES]; }; struct TArtNetPollTableUniverses { diff --git a/lib-artnet/src/artnetconst.cpp b/lib-artnet/src/artnetconst.cpp index ba6b021..29258bb 100644 --- a/lib-artnet/src/artnetconst.cpp +++ b/lib-artnet/src/artnetconst.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,7 +31,7 @@ #include "artnetconst.h" #include "artnet.h" -const uint8_t ArtNetConst::VERSION[] = { 1, 58 }; +const uint8_t ArtNetConst::VERSION[] = { 1, 59 }; const uint8_t ArtNetConst::ESTA_ID[artnet::ESTA_SIZE] = { 0x50, 0x00 }; ///< https://tsp.esta.org/tsp/working_groups/CP/mfctrIDs.php const uint8_t ArtNetConst::OEM_ID[] = { 0xff, 0xff }; ///< Waiting OEM from Artistic Licence Holdings Ltd. diff --git a/lib-artnet/src/controller/artnetcontroller.cpp b/lib-artnet/src/controller/artnetcontroller.cpp index df9ee0f..84a4786 100644 --- a/lib-artnet/src/controller/artnetcontroller.cpp +++ b/lib-artnet/src/controller/artnetcontroller.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,14 +41,13 @@ #include "debug.h" -#define ARTNET_MIN_HEADER_SIZE 12 - -static uint16_t s_ActiveUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES] __attribute__ ((aligned (4))); - ArtNetController *ArtNetController::s_pThis; using namespace artnet; +static constexpr uint32_t ARTNET_MIN_HEADER_SIZE = 12; +static uint16_t s_ActiveUniverses[POLL_TABLE_SIZE_UNIVERSES] __attribute__ ((aligned (4))); + ArtNetController::ArtNetController() { DEBUG_ENTRY @@ -258,7 +257,7 @@ void ArtNetController::HandleTrigger() { void ArtNetController::HandlePoll() { const auto nCurrentMillis = Hardware::Get()->Millis(); - if (__builtin_expect((nCurrentMillis - m_nLastPollMillis > ARTNET_POLL_INTERVAL_MILLIS), 0)) { + if (__builtin_expect((nCurrentMillis - m_nLastPollMillis > POLL_INTERVAL_MILLIS), 0)) { Network::Get()->SendTo(m_nHandle, &m_ArtNetPoll, sizeof(struct ArtPoll), m_tArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); m_nLastPollMillis= nCurrentMillis; @@ -268,7 +267,7 @@ void ArtNetController::HandlePoll() { #endif } - if (m_bDoTableCleanup && (__builtin_expect((nCurrentMillis - m_nLastPollMillis > ARTNET_POLL_INTERVAL_MILLIS/4), 0))) { + if (m_bDoTableCleanup && (__builtin_expect((nCurrentMillis - m_nLastPollMillis > POLL_INTERVAL_MILLIS/4), 0))) { Clean(); } } @@ -289,7 +288,7 @@ void ArtNetController::Run() { HandlePoll(); } - const int nBytesReceived = Network::Get()->RecvFrom(m_nHandle, pArtPacket, sizeof(struct TArtNetPacket), &m_pArtNetPacket->IPAddressFrom, &nForeignPort) ; + const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, pArtPacket, sizeof(struct TArtNetPacket), &m_pArtNetPacket->IPAddressFrom, &nForeignPort) ; if (__builtin_expect((nBytesReceived < ARTNET_MIN_HEADER_SIZE), 1)) { return; @@ -377,8 +376,8 @@ void ArtNetController::ActiveUniversesAdd(uint16_t nUniverse) { void ArtNetController::Print() { printf("Art-Net Controller\n"); - printf(" Max Node's : %u\n", ARTNET_POLL_TABLE_SIZE_ENRIES); - printf(" Max Universes : %u\n", ARTNET_POLL_TABLE_SIZE_UNIVERSES); + printf(" Max Node's : %u\n", POLL_TABLE_SIZE_ENRIES); + printf(" Max Universes : %u\n", POLL_TABLE_SIZE_UNIVERSES); if (!m_bUnicast) { puts(" Unicast is disabled"); } diff --git a/lib-artnet/src/controller/artnetpolltable.cpp b/lib-artnet/src/controller/artnetpolltable.cpp index 73c48d4..c7ee818 100644 --- a/lib-artnet/src/controller/artnetpolltable.cpp +++ b/lib-artnet/src/controller/artnetpolltable.cpp @@ -53,18 +53,18 @@ union uip { } static ip; ArtNetPollTable::ArtNetPollTable() { - m_pPollTable = new TArtNetNodeEntry[ARTNET_POLL_TABLE_SIZE_ENRIES]; + m_pPollTable = new TArtNetNodeEntry[POLL_TABLE_SIZE_ENRIES]; assert(m_pPollTable != nullptr); - memset(m_pPollTable, 0, sizeof(TArtNetNodeEntry[ARTNET_POLL_TABLE_SIZE_ENRIES])); + memset(m_pPollTable, 0, sizeof(TArtNetNodeEntry[POLL_TABLE_SIZE_ENRIES])); - m_pTableUniverses = new TArtNetPollTableUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES]; + m_pTableUniverses = new TArtNetPollTableUniverses[POLL_TABLE_SIZE_UNIVERSES]; assert(m_pTableUniverses != nullptr); - memset(m_pTableUniverses, 0, sizeof(TArtNetPollTableUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES])); + memset(m_pTableUniverses, 0, sizeof(TArtNetPollTableUniverses[POLL_TABLE_SIZE_UNIVERSES])); - for (uint32_t nIndex = 0; nIndex < ARTNET_POLL_TABLE_SIZE_UNIVERSES; nIndex++) { - m_pTableUniverses[nIndex].pIpAddresses = new uint32_t[ARTNET_POLL_TABLE_SIZE_ENRIES]; + for (uint32_t nIndex = 0; nIndex < POLL_TABLE_SIZE_UNIVERSES; nIndex++) { + m_pTableUniverses[nIndex].pIpAddresses = new uint32_t[POLL_TABLE_SIZE_ENRIES]; assert(m_pTableUniverses[nIndex].pIpAddresses != nullptr); } @@ -77,7 +77,7 @@ ArtNetPollTable::ArtNetPollTable() { } ArtNetPollTable::~ArtNetPollTable() { - for (uint32_t nIndex = 0; nIndex < ARTNET_POLL_TABLE_SIZE_UNIVERSES; nIndex++) { + for (uint32_t nIndex = 0; nIndex < POLL_TABLE_SIZE_UNIVERSES; nIndex++) { delete[] m_pTableUniverses[nIndex].pIpAddresses; m_pTableUniverses[nIndex].pIpAddresses = nullptr; } @@ -174,7 +174,7 @@ void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { void ArtNetPollTable::ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse) { DEBUG_ENTRY - if (ARTNET_POLL_TABLE_SIZE_UNIVERSES == m_nTableUniversesEntries) { + if (POLL_TABLE_SIZE_UNIVERSES == m_nTableUniversesEntries) { DEBUG_PUTS("m_pTableUniverses is full"); DEBUG_EXIT return; @@ -217,7 +217,7 @@ void ArtNetPollTable::ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse) { } if (!bFoundIp) { - if (pTableUniverses->nCount < ARTNET_POLL_TABLE_SIZE_ENRIES) { + if (pTableUniverses->nCount < POLL_TABLE_SIZE_ENRIES) { pTableUniverses->pIpAddresses[pTableUniverses->nCount] = nIpAddress; pTableUniverses->nCount++; DEBUG_PUTS("It is a new IP for the Universe"); @@ -259,7 +259,7 @@ void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { } if (!bFound) { - if (m_nPollTableEntries == ARTNET_POLL_TABLE_SIZE_ENRIES) { + if (m_nPollTableEntries == POLL_TABLE_SIZE_ENRIES) { DEBUG_PUTS("Full"); return; } @@ -319,7 +319,7 @@ void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { if (nIndexUniverse == m_pPollTable[i].nUniversesCount) { // Not found - if (m_pPollTable[i].nUniversesCount < ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES) { + if (m_pPollTable[i].nUniversesCount < POLL_TABLE_SIZE_NODE_UNIVERSES) { m_pPollTable[i].nUniversesCount++; m_pPollTable[i].Universe[nIndexUniverse].nUniverse = nUniverse; ProcessUniverse(ip.u32, nUniverse); @@ -342,7 +342,7 @@ void ArtNetPollTable::Clean() { } assert(m_tTableClean.nTableIndex < m_nPollTableEntries); - assert(m_tTableClean.nUniverseIndex < ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES); + assert(m_tTableClean.nUniverseIndex < POLL_TABLE_SIZE_NODE_UNIVERSES); if (m_tTableClean.nUniverseIndex == 0) { m_tTableClean.bOffLine = true; @@ -351,7 +351,7 @@ void ArtNetPollTable::Clean() { struct TArtNetNodeEntryUniverse *pArtNetNodeEntryBind = &m_pPollTable[m_tTableClean.nTableIndex].Universe[m_tTableClean.nUniverseIndex]; if (pArtNetNodeEntryBind->nLastUpdateMillis != 0) { - if ((Hardware::Get()->Millis() - pArtNetNodeEntryBind->nLastUpdateMillis) > (1.5 * ARTNET_POLL_INTERVAL_MILLIS)) { + if ((Hardware::Get()->Millis() - pArtNetNodeEntryBind->nLastUpdateMillis) > (1.5 * POLL_INTERVAL_MILLIS)) { pArtNetNodeEntryBind->nLastUpdateMillis = 0; RemoveIpAddress(pArtNetNodeEntryBind->nUniverse, m_pPollTable[m_tTableClean.nTableIndex].IPAddress); } else { @@ -361,7 +361,7 @@ void ArtNetPollTable::Clean() { m_tTableClean.nUniverseIndex++; - if (m_tTableClean.nUniverseIndex == ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES) { + if (m_tTableClean.nUniverseIndex == POLL_TABLE_SIZE_NODE_UNIVERSES) { if (m_tTableClean.bOffLine) { DEBUG_PUTS("Node is off-line"); @@ -379,7 +379,7 @@ void ArtNetPollTable::Clean() { struct TArtNetNodeEntry *pDst = &pArtNetNodeEntry[m_nPollTableEntries]; pDst->IPAddress = 0; pDst->nUniversesCount = 0; - memset(pDst->Universe, 0, sizeof(struct TArtNetNodeEntryUniverse[ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES])); + memset(pDst->Universe, 0, sizeof(struct TArtNetNodeEntryUniverse[POLL_TABLE_SIZE_NODE_UNIVERSES])); #ifndef NDEBUG memset(pDst->Mac, 0, artnet::MAC_SIZE + artnet::SHORT_NAME_LENGTH + artnet::LONG_NAME_LENGTH); #endif diff --git a/lib-artnet/src/node/artnetnode.cpp b/lib-artnet/src/node/artnetnode.cpp index ab472c6..0882a7a 100644 --- a/lib-artnet/src/node/artnetnode.cpp +++ b/lib-artnet/src/node/artnetnode.cpp @@ -83,6 +83,12 @@ ArtNetNode::ArtNetNode() { m_ArtPollReply.AcnPriority = e131::priority::DEFAULT; #endif + memset(&m_State, 0, sizeof(struct artnetnode::State)); + m_State.reportCode = artnetnode::ReportCode::RCPOWEROK; + m_State.status = artnetnode::Status::STANDBY; + // The device should wait for a random delay of up to 1s before sending the reply. + m_State.ArtPollReplyDelayMillis = (m_ArtPollReply.MAC[5] | (static_cast(m_ArtPollReply.MAC[4]) << 8)) % 1000; + SetLongName(nullptr); // Set default long name memset(&m_Node, 0, sizeof(struct artnetnode::Node)); @@ -96,12 +102,6 @@ ArtNetNode::ArtNetNode() { SetShortName(nPortIndex, nullptr); // Set default port label } - memset(&m_State, 0, sizeof(struct artnetnode::State)); - m_State.reportCode = artnetnode::ReportCode::RCPOWEROK; - m_State.status = artnetnode::Status::STANDBY; - // The device should wait for a random delay of up to 1s before sending the reply. - m_State.ArtPollReplyDelayMillis = (m_ArtPollReply.MAC[5] | (static_cast(m_ArtPollReply.MAC[4]) << 8)) % 1000; - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { memset(&m_OutputPort[nPortIndex], 0, sizeof(struct artnetnode::OutputPort)); m_OutputPort[nPortIndex].SourceA.nPhysical = 0x100; diff --git a/lib-c++/src/delete.cpp b/lib-c++/src/delete.cpp index f1e1e28..9b81792 100644 --- a/lib-c++/src/delete.cpp +++ b/lib-c++/src/delete.cpp @@ -2,7 +2,7 @@ * @file delete.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,10 +34,14 @@ void operator delete[](void *p) { free(p); } -void operator delete(void* p, __attribute__((unused)) std::size_t size) noexcept { +/* + * C++14 and above + */ + +void operator delete(void *p, __attribute__((unused)) std::size_t size) noexcept { free(p); } -void operator delete[](void* p, __attribute__((unused))std::size_t size) noexcept { +void operator delete[](void *p, __attribute__((unused))std::size_t size) noexcept { free(p); } diff --git a/lib-c++/src/dso_handle.cpp b/lib-c++/src/dso_handle.cpp old mode 100644 new mode 100755 index ad96021..e2d04a8 --- a/lib-c++/src/dso_handle.cpp +++ b/lib-c++/src/dso_handle.cpp @@ -2,7 +2,7 @@ * @file dso_handle.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023 by Arjan van Vught mailto:info@info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-c++/src/new.cpp b/lib-c++/src/new.cpp index d067e4b..64b61cc 100644 --- a/lib-c++/src/new.cpp +++ b/lib-c++/src/new.cpp @@ -2,7 +2,7 @@ * @file new.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,7 +23,7 @@ * THE SOFTWARE. */ -#include +#include void *operator new(unsigned size) { return malloc(size); diff --git a/lib-c++/src/purecall.cpp b/lib-c++/src/purecall.cpp index 5f94c75..d4ff1c3 100644 --- a/lib-c++/src/purecall.cpp +++ b/lib-c++/src/purecall.cpp @@ -2,7 +2,7 @@ * @file purecall.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-configstore/Rules.mk b/lib-configstore/Rules.mk index 8c8fc20..5e60c36 100755 --- a/lib-configstore/Rules.mk +++ b/lib-configstore/Rules.mk @@ -1,7 +1,5 @@ $(info $$MAKE_FLAGS [${MAKE_FLAGS}]) -EXTRA_INCLUDES=../lib-flashcode/include ../lib-hal/include - ifneq ($(MAKE_FLAGS),) ifneq (,$(findstring CONFIG_STORE_USE_FILE,$(MAKE_FLAGS))) EXTRA_SRCDIR+=device/file diff --git a/lib-ddp/Rules.mk b/lib-ddp/Rules.mk index 801e1e3..aa2f9f5 100644 --- a/lib-ddp/Rules.mk +++ b/lib-ddp/Rules.mk @@ -4,5 +4,4 @@ else DEFINES+=LIGHTSET_PORTS=32 endif -EXTRA_INCLUDES =../lib-properties/include ../lib-hal/include ../lib-network/include -EXTRA_INCLUDES+=../lib-lightset/include +EXTRA_INCLUDES =../lib-properties/include ../lib-network/include ../lib-lightset/include diff --git a/lib-displayudf/Rules.mk b/lib-displayudf/Rules.mk index 6797728..830222d 100644 --- a/lib-displayudf/Rules.mk +++ b/lib-displayudf/Rules.mk @@ -1,5 +1,3 @@ -EXTRA_INCLUDES+=../lib-configstore/include - ifneq ($(MAKE_FLAGS),) ifneq (,$(findstring NODE_NODE,$(MAKE_FLAGS))) EXTRA_INCLUDES+=../lib-node/include diff --git a/lib-dmx/src/gd32/dmx.cpp b/lib-dmx/src/gd32/dmx.cpp index f43ca24..e02b78f 100644 --- a/lib-dmx/src/gd32/dmx.cpp +++ b/lib-dmx/src/gd32/dmx.cpp @@ -2,7 +2,7 @@ * @file dmx.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -62,6 +62,13 @@ void console_error(const char *); # define UNUSED __attribute__((unused)) #endif +/** + * Needed for older GD32F firmware + */ +#if !defined(USART_TRANSMIT_DMA_ENABLE) +# define USART_TRANSMIT_DMA_ENABLE USART_DENT_ENABLE +#endif + /** * https://www.gd32-dmx.org/memory.html */ @@ -923,7 +930,7 @@ void TIMER1_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(USART0_DMA, USART0_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART0, USART_DENT_ENABLE); + usart_dma_transmit_config(USART0, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -962,7 +969,7 @@ void TIMER1_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(USART1_DMA, USART1_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART1, USART_DENT_ENABLE); + usart_dma_transmit_config(USART1, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -1001,7 +1008,7 @@ void TIMER1_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(USART2_DMA, USART2_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART2, USART_DENT_ENABLE); + usart_dma_transmit_config(USART2, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -1040,7 +1047,7 @@ void TIMER1_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(UART3_DMA, UART3_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(UART3, USART_DENT_ENABLE); + usart_dma_transmit_config(UART3, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -1081,7 +1088,7 @@ void TIMER4_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(UART4_DMA, UART4_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(UART4, USART_DENT_ENABLE); + usart_dma_transmit_config(UART4, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -1119,7 +1126,7 @@ void TIMER4_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(USART5_DMA, USART5_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART5, USART_DENT_ENABLE); + usart_dma_transmit_config(USART5, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -1158,7 +1165,7 @@ void TIMER4_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(UART6_DMA, UART6_TX_DMA_CH)= dmaCHCTL; - usart_dma_transmit_config(UART6, USART_DENT_ENABLE); + usart_dma_transmit_config(UART6, USART_TRANSMIT_DMA_ENABLE); } break; default: @@ -1197,7 +1204,7 @@ void TIMER4_IRQHandler() { dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; DMA_CHCTL(UART7_DMA, UART7_TX_DMA_CH)= dmaCHCTL; - usart_dma_transmit_config(UART7, USART_DENT_ENABLE); + usart_dma_transmit_config(UART7, USART_TRANSMIT_DMA_ENABLE); } break; default: diff --git a/lib-e131/include/e131bridgeconst.h b/lib-e131/include/e131const.h similarity index 84% rename from lib-e131/include/e131bridgeconst.h rename to lib-e131/include/e131const.h index 79ea324..a23212e 100644 --- a/lib-e131/include/e131bridgeconst.h +++ b/lib-e131/include/e131const.h @@ -1,8 +1,8 @@ /** - * @file e131bridgeconst.h + * @file e131const.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,13 +23,13 @@ * THE SOFTWARE. */ -#ifndef E131BRIDGECONST_H_ -#define E131BRIDGECONST_H_ +#ifndef E131CONST_H_ +#define E131CONST_H_ #include -struct E131BridgeConst { +struct E131Const { static const uint8_t VERSION[]; }; -#endif /* E131BRIDGECONST_H_ */ +#endif /* E131CONST_H_ */ diff --git a/lib-e131/src/node/e131bridgeconst.cpp b/lib-e131/src/e131const.cpp old mode 100644 new mode 100755 similarity index 86% rename from lib-e131/src/node/e131bridgeconst.cpp rename to lib-e131/src/e131const.cpp index eb5ad36..2369640 --- a/lib-e131/src/node/e131bridgeconst.cpp +++ b/lib-e131/src/e131const.cpp @@ -1,8 +1,8 @@ /** - * @file e131bridgeconst.cpp + * @file e131const.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,6 +25,6 @@ #include -#include "e131bridgeconst.h" +#include "e131const.h" -const uint8_t E131BridgeConst::VERSION[] = { 1, 27 }; +const uint8_t E131Const::VERSION[] = { 1, 27 }; diff --git a/lib-e131/src/node/e131bridgeprint.cpp b/lib-e131/src/node/e131bridgeprint.cpp index 8450877..745c0f6 100644 --- a/lib-e131/src/node/e131bridgeprint.cpp +++ b/lib-e131/src/node/e131bridgeprint.cpp @@ -2,7 +2,7 @@ * @file e131bridgeprint.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ #include #include "e131bridge.h" -#include "e131bridgeconst.h" +#include "e131const.h" #include "e131.h" #if defined (E131_HAVE_DMXIN) @@ -46,8 +46,7 @@ void E131Bridge::Print() { uuid_str[UUID_STRING_LENGTH] = '\0'; uuid_unparse(m_Cid, uuid_str); #endif - printf("Bridge\n"); - printf(" Firmware : %d.%d\n", E131BridgeConst::VERSION[0], E131BridgeConst::VERSION[1]); + printf("sACN E1.31 V%d.%d\n", E131Const::VERSION[0], E131Const::VERSION[1]); #if defined (E131_HAVE_DMXIN) printf(" CID : %s\n", uuid_str); #endif diff --git a/lib-flash/src/spi/gd32/spi_flash.cpp b/lib-flash/src/spi/gd32/spi_flash.cpp index c9b499a..2318a38 100644 --- a/lib-flash/src/spi/gd32/spi_flash.cpp +++ b/lib-flash/src/spi/gd32/spi_flash.cpp @@ -2,7 +2,7 @@ * @file spi_flash.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,6 +41,16 @@ int spi_init() { gpio_fsel(SPI_FLASH_CS_GPIOx, SPI_FLASH_CS_GPIO_PINx, GPIO_FSEL_OUTPUT); gpio_bit_set(SPI_FLASH_CS_GPIOx, SPI_FLASH_CS_GPIO_PINx); +#if defined (SPI_FLASH_WP_GPIO_PINx) + gpio_fsel(SPI_GPIOx, SPI_FLASH_WP_GPIO_PINx, GPIO_FSEL_OUTPUT); + gpio_bit_set(SPI_GPIOx, SPI_FLASH_WP_GPIO_PINx); +#endif + +#if defined (SPI_FLASH_HOLD_GPIO_PINx) + gpio_fsel(SPI_GPIOx, SPI_FLASH_HOLD_GPIO_PINx, GPIO_FSEL_OUTPUT); + gpio_bit_set(SPI_GPIOx, SPI_FLASH_HOLD_GPIO_PINx); +#endif + return 0; } diff --git a/lib-flash/src/spi/gigadevice.cpp b/lib-flash/src/spi/gigadevice.cpp old mode 100644 new mode 100755 index 9a28f91..9c72f30 --- a/lib-flash/src/spi/gigadevice.cpp +++ b/lib-flash/src/spi/gigadevice.cpp @@ -50,6 +50,11 @@ static constexpr struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] 64, "GD25LQ", }, + { + 0x4015, + 8, + "GD25Q40", + }, { 0x4017, 128, @@ -68,10 +73,11 @@ int spi_flash_probe_gigadevice(struct spi_flash *flash, uint8_t *idcode) { } if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) { - DEBUG_PRINTF("SF: Unsupported Gigadevice ID %02x%02x", idcode[1], idcode[2]); + DEBUG_PRINTF("SF: Unsupported GigaDevice ID %02x%02x", idcode[1], idcode[2]); return -1; } + flash->name = params->name; flash->page_size = 256; flash->sector_size = flash->page_size * 16; flash->size = flash->sector_size * 16 * params->nr_blocks; diff --git a/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h b/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h index 8c13d35..051290a 100644 --- a/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h +++ b/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h @@ -2,13 +2,11 @@ \file gd32f4xx.h \brief general definitions for GD32F4xx - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -51,13 +49,16 @@ OF SUCH DAMAGE. #endif /* define GD32F4xx */ -#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) /* #define GD32F450 */ /* #define GD32F405 */ /* #define GD32F407 */ + /* #define GD32F470 */ + /* #define GD32F425 */ + /* #define GD32F427 */ #endif /* define GD32F4xx */ -#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) #error "Please select the target GD32F4xx device in gd32f4xx.h file" #endif /* undefine GD32F4xx tip */ @@ -172,7 +173,7 @@ typedef enum IRQn TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ -#if defined (GD32F450) +#if defined (GD32F450) || defined (GD32F470) EXMC_IRQn = 48, /*!< EXMC interrupt */ SDIO_IRQn = 49, /*!< SDIO interrupt */ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ @@ -214,9 +215,9 @@ typedef enum IRQn TLI_IRQn = 88, /*!< TLI interrupt */ TLI_ER_IRQn = 89, /*!< TLI error interrupt */ IPA_IRQn = 90, /*!< IPA interrupt */ -#endif /* GD32F450 */ +#endif /* GD32F450 and GD32F470 */ -#if defined (GD32F405) +#if defined (GD32F405) || defined (GD32F425) SDIO_IRQn = 49, /*!< SDIO interrupt */ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ SPI2_IRQn = 51, /*!< SPI2 interrupt */ @@ -247,9 +248,9 @@ typedef enum IRQn DCI_IRQn = 78, /*!< DCI interrupt */ TRNG_IRQn = 80, /*!< TRNG interrupt */ FPU_IRQn = 81, /*!< FPU interrupt */ -#endif /* GD32F405 */ +#endif /* GD32F405 and GD32F425 */ -#if defined (GD32F407) +#if defined (GD32F407) || defined (GD32F427) EXMC_IRQn = 48, /*!< EXMC interrupt */ SDIO_IRQn = 49, /*!< SDIO interrupt */ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ @@ -283,7 +284,7 @@ typedef enum IRQn DCI_IRQn = 78, /*!< DCI interrupt */ TRNG_IRQn = 80, /*!< TRNG interrupt */ FPU_IRQn = 81, /*!< FPU interrupt */ -#endif /* GD32F407 */ +#endif /* GD32F407 and GD32F427 */ } IRQn_Type; diff --git a/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c b/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c index 689ce2c..208489e 100644 --- a/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c +++ b/lib-gd32/gd32f4xx/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c @@ -48,23 +48,36 @@ //#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000) //#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000) //#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000) -#if defined (GD32F407) -# define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000) -#endif +//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000) //#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000) //#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000) -#if defined (GD32F450) -# define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000) +#if defined (GD32F450) || defined (GD32F405) || defined (GD32F407) || defined (GD32F425) || defined (GD32F427) +#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000) +#endif + +#if defined (GD32F470) +#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000) #endif +#define __SYSTEM_CLOCK_240M_PLL_IRC16M (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000) + +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i; \ + if(0 != __delay){ \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0; i<__delay; i++){ \ + } \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) + #define SEL_IRC16M 0x00U #define SEL_HXTAL 0x01U #define SEL_PLLP 0x02U -#define RCU_MODIFY {volatile uint32_t i; \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ - for(i=0;i<50000;i++); \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ - for(i=0;i<50000;i++);} /* set the system clock frequency and declare the system clock configuration function */ #ifdef __SYSTEM_CLOCK_IRC16M @@ -100,6 +113,15 @@ static void system_clock_200m_8m_hxtal(void); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL; static void system_clock_200m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_IRC16M; +static void system_clock_240m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_8M_HXTAL; +static void system_clock_240m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_25M_HXTAL; +static void system_clock_240m_25m_hxtal(void); #endif /* __SYSTEM_CLOCK_IRC16M */ @@ -121,8 +143,9 @@ void SystemInit (void) /* Reset the RCU clock configuration to the default reset state */ /* Set IRC16MEN bit */ RCU_CTL |= RCU_CTL_IRC16MEN; - - RCU_MODIFY + while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + } + RCU_MODIFY(0x50); RCU_CFG0 &= ~RCU_CFG0_SCS; @@ -179,6 +202,12 @@ static void system_clock_config(void) system_clock_200m_8m_hxtal(); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) system_clock_200m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) + system_clock_240m_irc16m(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) + system_clock_240m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) + system_clock_240m_25m_hxtal(); #endif /* __SYSTEM_CLOCK_IRC16M */ } @@ -248,7 +277,8 @@ static void system_clock_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -359,7 +389,8 @@ static void system_clock_120m_8m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -427,7 +458,8 @@ static void system_clock_120m_25m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -560,7 +592,8 @@ static void system_clock_168m_8m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -627,7 +660,8 @@ static void system_clock_168m_25m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -763,7 +797,8 @@ static void system_clock_200m_8m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -831,7 +866,8 @@ static void system_clock_200m_25m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { } } @@ -876,6 +912,211 @@ static void system_clock_200m_25m_hxtal(void) } } +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +/*! + \brief configure the system clock to 240M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (8U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) + { + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (25U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} #endif /* __SYSTEM_CLOCK_IRC16M */ /*! \brief update the SystemCoreClock with current core clock retrieved from cpu registers diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h index 2fbd49b..5dbd094 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h @@ -2,13 +2,11 @@ \file gd32f4xx_adc.h \brief definitions for the ADC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -45,365 +43,365 @@ OF SUCH DAMAGE. #define ADC2 (ADC_BASE + 0x200U) /* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ -#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ -#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ -#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ +#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ +#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ +#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */ /* bits definitions */ /* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ -#define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */ +#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */ /* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ /* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ -#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */ -#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ -#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */ -#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */ -#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ +#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */ +#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ +#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */ +#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */ +#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */ /* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ /* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ /* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ /* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ /* ADC_RSQx */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */ /* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ /* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ /* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */ /* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ /* ADC_SSTAT */ -#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ -#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ -#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ -#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ -#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ -#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ -#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ -#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ -#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ -#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ -#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ -#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ -#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ -#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ -#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ -#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ -#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ -#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ +#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ +#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ +#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ +#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ +#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ +#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ +#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ +#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ +#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ +#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ +#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ +#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ +#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ +#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ +#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ +#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ +#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ +#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ /* ADC_SYNCCTL */ -#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ -#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ -#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ -#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ -#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ -#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ -#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ +#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ +#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ +#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ +#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ +#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ +#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ +#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ /* ADC_SYNCDATA */ -#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */ -#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */ /* constants definitions */ /* ADC status flag */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ -#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */ +#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ /* adc_ctl0 register value */ #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ /* ADC special function definitions */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ /* temperature sensor channel, internal reference voltage channel, VBAT channel */ #define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ #define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ /* ADC synchronization mode */ -#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ +#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */ #define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */ -#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */ +#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ #define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ /* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ -/* external trigger mode for regular and inserted channel */ -#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ -#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ -#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ -#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ +/* external trigger mode for routine and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ -/* ADC external trigger select for regular channel */ +/* ADC external trigger select for routine channel */ #define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ /* ADC external trigger select for inserted channel */ #define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ /* ADC channel sample time */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ -#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ -#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ -#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ -#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ -#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ -#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ -#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ /* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ /* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ /* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ /* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ /* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ /* adc_ovsampctl register value */ /* ADC resolution */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ /* oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ /* oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* triggered Oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel sequence definitions */ +#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */ +#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */ /* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ /* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ /* ADC interrupt flag */ -#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */ -#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */ /* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ -#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ /* configure the ADC clock for all the ADCs */ #define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ -#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ -#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ -#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ -#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ -#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ -#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ -#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ +#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ +#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ +#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ +#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ +#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ +#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ +#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ +#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ /* ADC synchronization delay */ -#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ -#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ -#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ -#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ -#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ -#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ -#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ -#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ -#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ -#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ -#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ -#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ -#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ -#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ -#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ -#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ +#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ +#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ +#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ +#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ +#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ +#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ +#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ +#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ +#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ +#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ +#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ +#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ +#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ +#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ +#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ +#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ /* ADC synchronization DMA mode selection */ -#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ -#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ -#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ +#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ +#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ +#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ /* end of conversion mode */ -#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */ -#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */ +#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */ +#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */ /* function declarations */ /* initialization config */ @@ -437,35 +435,35 @@ void adc_oversample_mode_disable(uint32_t adc_periph); void adc_dma_mode_enable(uint32_t adc_periph); /* disable DMA request */ void adc_dma_mode_disable(uint32_t adc_periph); -/* when DMA=1, the DMA engine issues a request at end of each regular conversion */ +/* when DMA=1, the DMA engine issues a request at end of each routine conversion */ void adc_dma_request_after_last_enable(uint32_t adc_periph); /* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ void adc_dma_request_after_last_disable(uint32_t adc_periph); -/* regular group and inserted group config */ +/* routine sequence and inserted sequence config */ /* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length); +/* configure the length of routine sequence or inserted sequence */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length); +/* configure ADC routine channel */ +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel */ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel offset */ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); /* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source); /* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode); /* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence); /* configure end of conversion mode */ void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); /* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ +/* read ADC routine data register */ +uint16_t adc_routine_data_read(uint32_t adc_periph); +/* read ADC inserted data register */ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); /* watchdog config */ @@ -473,10 +471,10 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); void adc_watchdog_single_channel_disable(uint32_t adc_periph ); /* enable ADC analog watchdog single channel */ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure ADC analog watchdog sequence */ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence); /* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence); /* configure ADC analog watchdog threshold */ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); @@ -486,7 +484,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); /* clear the ADC flag bits */ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); /* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph); /* get the bit state of ADCx software inserted channel start conversion */ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); /* get the ADC interrupt bits */ @@ -509,7 +507,7 @@ void adc_sync_dma_config(uint32_t dma_mode ); void adc_sync_dma_request_after_last_enable(void); /* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ void adc_sync_dma_request_after_last_disable(void); -/* read ADC sync regular data register */ -uint32_t adc_sync_regular_data_read(void); +/* read ADC sync routine data register */ +uint32_t adc_sync_routine_data_read(void); #endif /* GD32F4XX_ADC_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h index ac96a3c..a9fbc5f 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h @@ -2,36 +2,33 @@ \file gd32f4xx_can.h \brief definitions for the CAN - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-11-27, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,99 +39,99 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ /* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ +#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ /* CAN transmit mailbox bank */ #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ @@ -146,7 +143,7 @@ OF SUCH DAMAGE. #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ -/* CAN receive fifo mailbox bank */ +/* CAN receive FIFO mailbox bank */ #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ @@ -296,10 +293,10 @@ OF SUCH DAMAGE. #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ /* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */ /* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */ /* CAN_FAFIFO */ #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ @@ -310,7 +307,7 @@ OF SUCH DAMAGE. /* CAN_FxDATAy */ #define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ -/* consts definitions */ +/* constants definitions */ /* define the CAN bit position and its register index offset */ #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) @@ -329,56 +326,54 @@ OF SUCH DAMAGE. #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ /* CAN flags */ -typedef enum -{ +typedef enum { /* flags in STAT register */ - CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ - CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ - CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ - CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ - CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ - CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ - CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ - CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ - CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ /* flags in TSTAT register */ - CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ - CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ - CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ - CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ - CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ - CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ - CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ - CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ - CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ - CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ - CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +} can_flag_enum; /* CAN interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ /* interrupt flags in TSTAT register */ CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ @@ -390,44 +385,41 @@ typedef enum /* interrupt flags in RFIFO0 register */ CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ - CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ /* interrupt flags in ERR register */ - CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ - CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ - CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ - CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ -}can_interrupt_flag_enum; - -/* CAN initiliaze parameters struct */ -typedef struct -{ - uint8_t working_mode; /*!< CAN working mode */ + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +} can_interrupt_flag_enum; + +/* CAN initiliaze parameters structure */ +typedef struct { + uint8_t working_mode; /*!< CAN working mode */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t time_segment_1; /*!< time segment 1 */ uint8_t time_segment_2; /*!< time segment 2 */ ControlStatus time_triggered; /*!< time triggered communication mode */ ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus auto_retrans; /*!< automatic retransmission mode */ ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */ uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; +} can_parameter_struct; -/* CAN transmit message struct */ -typedef struct -{ +/* CAN transmit message structure */ +typedef struct { uint32_t tx_sfid; /*!< standard format frame identifier */ uint32_t tx_efid; /*!< extended format frame identifier */ uint8_t tx_ff; /*!< format of frame, standard or extended format */ uint8_t tx_ft; /*!< type of frame, data or remote */ uint8_t tx_dlen; /*!< data length */ uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; +} can_trasnmit_message_struct; -/* CAN receive message struct */ -typedef struct -{ +/* CAN receive message structure */ +typedef struct { uint32_t rx_sfid; /*!< standard format frame identifier */ uint32_t rx_efid; /*!< extended format frame identifier */ uint8_t rx_ff; /*!< format of frame, standard or extended format */ @@ -437,10 +429,9 @@ typedef struct uint8_t rx_fi; /*!< filtering index */ } can_receive_message_struct; -/* CAN filter parameters struct */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ +/* CAN filter parameters structure */ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits */ uint16_t filter_list_low; /*!< filter list number low bits */ uint16_t filter_mask_high; /*!< filter mask number high bits */ uint16_t filter_mask_low; /*!< filter mask number low bits */ @@ -449,11 +440,10 @@ typedef struct uint16_t filter_mode; /*!< filter mode, list or mask */ uint16_t filter_bits; /*!< filter scale */ ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; +} can_filter_parameter_struct; /* CAN errors */ -typedef enum -{ +typedef enum { CAN_ERROR_NONE = 0, /*!< no error */ CAN_ERROR_FILL, /*!< fill error */ CAN_ERROR_FORMATE, /*!< format error */ @@ -462,38 +452,36 @@ typedef enum CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ CAN_ERROR_CRC, /*!< CRC error */ CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; +} can_error_enum; /* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; - -typedef enum -{ +typedef enum { + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; + +typedef enum { CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ CAN_FILTER_STRUCT, /* CAN filter parameters struct */ CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -}can_struct_type_enum; +} can_struct_type_enum; -/* CAN baudrate prescaler*/ +/* CAN baudrate prescaler */ #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) -/* CAN bit segment 1*/ +/* CAN bit segment 1 */ #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -/* CAN bit segment 2*/ +/* CAN bit segment 2 */ #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) -/* CAN resynchronization jump width*/ +/* CAN resynchronization jump width */ #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -/* CAN communication mode*/ +/* CAN communication mode */ #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) /* CAN FDATA high 16 bits */ @@ -502,13 +490,13 @@ typedef enum /* CAN FDATA low 16 bits */ #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* CAN1 filter start bank_number*/ +/* CAN1 filter start bank_number */ #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -/* CAN transmit mailbox extended identifier*/ +/* CAN transmit mailbox extended identifier */ #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) -/* CAN transmit mailbox standard identifier*/ +/* CAN transmit mailbox standard identifier */ #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) /* transmit data byte 0 */ @@ -520,25 +508,25 @@ typedef enum /* transmit data byte 2 */ #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 3 */ +/* transmit data byte 3 */ #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* transmit data byte 4 */ +/* transmit data byte 4 */ #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -/* transmit data byte 5 */ +/* transmit data byte 5 */ #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -/* transmit data byte 6 */ +/* transmit data byte 6 */ #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 7 */ +/* transmit data byte 7 */ #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* receive mailbox extended identifier*/ +/* receive mailbox extended identifier */ #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) -/* receive mailbox standrad identifier*/ +/* receive mailbox standard identifier */ #define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) /* receive data length */ @@ -571,25 +559,25 @@ typedef enum /* receive data byte 7 */ #define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) -/* error number */ +/* error number */ #define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) -/* transmit error count */ +/* transmit error count */ #define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) -/* receive error count */ +/* receive error count */ #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* CAN errors */ #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ +#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ @@ -643,11 +631,11 @@ typedef enum #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ -/* CAN receive fifo */ +/* CAN receive FIFO */ #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ -/* frame number of receive fifo */ +/* frame number of receive FIFO */ #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ @@ -693,15 +681,18 @@ typedef enum #define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ /* function declarations */ +/* initialization functions */ /* deinitialize CAN */ void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN structure */ +void can_struct_para_init(can_struct_type_enum type, void *p_struct); /* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); -/* set can1 fliter start bank number */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +/* CAN filter initialization */ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); + +/* function configuration */ +/* set can1 filter start bank number */ void can1_filter_start_bank(uint8_t start_bank); /* enable functions */ /* CAN debug freeze enable */ @@ -715,14 +706,14 @@ void can_time_trigger_mode_disable(uint32_t can_periph); /* transmit functions */ /* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); /* get CAN transmit state */ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); /* stop CAN transmission */ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); /* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); +/* CAN release FIFO */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); /* CAN receive message length */ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); @@ -731,21 +722,22 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); /* CAN wakeup from sleep mode */ ErrStatus can_wakeup(uint32_t can_periph); -/* CAN get error */ +/* CAN get error type */ can_error_enum can_error_get(uint32_t can_periph); /* get CAN receive error number */ uint8_t can_receive_error_number_get(uint32_t can_periph); /* get CAN transmit error number */ uint8_t can_transmit_error_number_get(uint32_t can_periph); -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* interrupt & flag functions */ /* CAN get flag state */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); /* CAN clear flag state */ void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); /* CAN get interrupt flag state */ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); /* CAN clear interrupt flag state */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h index e14df03..da5bad5 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h @@ -2,13 +2,11 @@ \file gd32f4xx_crc.h \brief definitions for the CRC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,12 +38,12 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* CRC definitions */ -#define CRC CRC_BASE +#define CRC CRC_BASE /*!< CRC base address */ /* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ /* bits definitions */ /* CRC_DATA */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h index 2eafebb..e1179a2 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h @@ -2,13 +2,11 @@ \file gd32f4xx_ctc.h \brief definitions for the CTC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -64,7 +62,6 @@ OF SUCH DAMAGE. #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ #define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ #define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */ #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ /* CTC_STAT */ @@ -93,15 +90,10 @@ OF SUCH DAMAGE. #define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ -/* USBFS or USBHS SOF signal selection definitions */ -#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/ -#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/ - /* reference signal source selection definitions */ #define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */ /* reference signal source prescaler definitions */ #define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) @@ -155,8 +147,6 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode); /* configure reference signal source polarity */ void ctc_refsource_polarity_config(uint32_t polarity); -/* select USBFS or USBHS SOF signal */ -void ctc_usbsof_signal_select(uint32_t usbsof); /* select reference signal source */ void ctc_refsource_signal_select(uint32_t refs); /* configure reference signal source prescaler */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h index 482f2bb..2f18508 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h @@ -2,13 +2,11 @@ \file gd32f4xx_dac.h \brief definitions for the DAC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,155 +38,155 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U /* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ -#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ /* bits definitions */ /* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ -#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ /* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ /* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ /* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ /* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ /* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ /* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ /* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ /* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ /* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ /* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ /* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ /* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ /* DAC_STAT */ -#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ -#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ +#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ +#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ /* constants definitions */ /* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ /* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ /* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ /* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ /* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ /* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ /* function declarations */ /* initialization functions */ @@ -254,14 +252,14 @@ void dac_concurrent_interrupt_enable(void); void dac_concurrent_interrupt_disable(void); /* DAC interrupt configuration */ -/* enable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_enable(uint32_t dac_periph); -/* disable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_disable(uint32_t dac_periph); /* get the specified DAC flag(DAC DMA underrun flag) */ FlagStatus dac_flag_get(uint32_t dac_periph); /* clear the specified DAC flag(DAC DMA underrun flag) */ void dac_flag_clear(uint32_t dac_periph); +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(uint32_t dac_periph); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(uint32_t dac_periph); /* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph); /* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h index aeb31b5..315a420 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h @@ -2,13 +2,11 @@ \file gd32f4xx_dbg.h \brief definitions for the DBG - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,7 +55,6 @@ OF SUCH DAMAGE. #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ #define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ /* DBG_CTL1 */ #define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */ @@ -122,19 +119,13 @@ typedef enum DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ - DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ }dbg_periph_enum; -#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) -#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - /* function declarations */ /* deinitialize the DBG */ void dbg_deinit(void); @@ -155,7 +146,5 @@ void dbg_periph_disable(dbg_periph_enum dbg_periph); void dbg_trace_pin_enable(void); /* disable trace pin assignment */ void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); #endif /* GD32F4XX_DBG_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h index 3fa215a..ac32060 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h @@ -2,13 +2,11 @@ \file gd32f4xx_dci.h \brief definitions for the DCI - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h index 04c0c53..06b864a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h @@ -1,14 +1,11 @@ /*! - \file gd32f4xx_dma.c + \file gd32f4xx_dma.h \brief definitions for the DMA - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,73 +34,77 @@ OF SUCH DAMAGE. #ifndef GD32F4XX_DMA_H #define GD32F4XX_DMA_H +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ #include "gd32f4xx.h" + /* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ /* registers definitions */ -#define DMA_INTF0(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register 0 */ -#define DMA_INTF1(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag register 1 */ -#define DMA_INTC0(dmax) REG32((dmax) + 0x08U) /*!< DMA interrupt flag clear register 0 */ -#define DMA_INTC1(dmax) REG32((dmax) + 0x0CU) /*!< DMA interrupt flag clear register 1 */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x18U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 0 memory 0 base address register */ -#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 0 memory 1 base address register */ -#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 0 FIFO control register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x2CU) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 1 memory 0 base address register */ -#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 1 memory 1 base address register */ -#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 1 FIFO control register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x40U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 2 memory 0 base address register */ -#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 2 memory 1 base address register */ -#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x54U) /*!< DMA channel 2 FIFO control register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 3 memory 0 base address register */ -#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x68U) /*!< DMA channel 3 memory 1 base address register */ -#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 3 FIFO control register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x7CU) /*!< DMA channel 4 memory 0 base address register */ -#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 4 memory 1 base address register */ -#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 4 FIFO control register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x90U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x94U) /*!< DMA channel 5 memory 0 base address register */ -#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x98U) /*!< DMA channel 5 memory 1 base address register */ -#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x9CU) /*!< DMA channel 5 FIFO control register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0xA0U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0xA4U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0xA8U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0xACU) /*!< DMA channel 6 memory 0 base address register */ -#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0xB0U) /*!< DMA channel 6 memory 1 base address register */ -#define DMA_CH6FCTL(dmax) REG32((dmax) + 0xB4U) /*!< DMA channel 6 FIFO control register */ - -#define DMA_CH7CTL(dmax) REG32((dmax) + 0xB8U) /*!< DMA channel 7 control register */ -#define DMA_CH7CNT(dmax) REG32((dmax) + 0xBCU) /*!< DMA channel 7 counter register */ -#define DMA_CH7PADDR(dmax) REG32((dmax) + 0xC0U) /*!< DMA channel 7 peripheral base address register */ -#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0xC4U) /*!< DMA channel 7 memory 0 base address register */ -#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0xC8U) /*!< DMA channel 7 memory 1 base address register */ -#define DMA_CH7FCTL(dmax) REG32((dmax) + 0xCCU) /*!< DMA channel 7 FIFO control register */ +#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */ +#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */ +#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */ +#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */ +#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */ +#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */ +#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */ +#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */ +#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */ +#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */ +#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */ +#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */ +#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */ +#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */ +#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */ +#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */ +#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */ +#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */ + +#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */ +#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */ +#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */ +#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */ +#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */ +#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */ /* bits definitions */ /* DMA_INTF */ @@ -326,7 +327,7 @@ typedef struct #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ #define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ -#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ +#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000021U) /*!< the reset value of DMA channel CHXFCTL register */ /* DMA_INTF register */ /* interrupt flag bits */ @@ -416,13 +417,17 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear DMA a channel flag */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); /* enable DMA interrupt */ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); /* disable DMA interrupt */ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* check DMA flag is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ #endif /* GD32F4XX_DMA_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h index 6cd948f..225294c 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h @@ -2,13 +2,11 @@ \file gd32f4xx_enet.h \brief definitions for the ENET - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -46,11 +44,11 @@ OF SUCH DAMAGE. #endif #ifndef ENET_RXBUF_NUM -#define ENET_RXBUF_NUM 2U /*!< ethernet Rx DMA descriptor number */ +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ #endif #ifndef ENET_TXBUF_NUM -#define ENET_TXBUF_NUM 1U /*!< ethernet Tx DMA descriptor number */ +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ #endif #ifndef ENET_RXBUF_SIZE @@ -129,7 +127,7 @@ OF SUCH DAMAGE. #define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ #define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ #define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */ #define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ #define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ #define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ @@ -891,8 +889,8 @@ typedef enum { ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ - ENET_CUSTOM = BIT(4), - ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_CUSTOM = BIT(4), /** AvV **/ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ }enet_frmrecept_enum; @@ -1119,7 +1117,7 @@ typedef struct #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */ +#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */ #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h index 39c5abc..6abedbc 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h @@ -2,13 +2,11 @@ \file gd32f4xx_exmc.h \brief definitions for the EXMC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -113,13 +111,13 @@ OF SUCH DAMAGE. #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ #define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ #define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */ #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ +#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */ #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ -#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */ +#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */ /* EXMC_SNTCFGx,x=0..3 */ #define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ @@ -207,7 +205,7 @@ OF SUCH DAMAGE. /* EXMC_SDARI */ #define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ #define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ -#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ +#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */ /* EXMC_SDSTAT */ #define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ @@ -278,7 +276,7 @@ typedef struct exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ }exmc_norsram_parameter_struct; -/* EXMC NAND/PC card timing initialize struct */ +/* EXMC NAND/PC card timing initialize structure */ typedef struct { uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ @@ -287,7 +285,7 @@ typedef struct uint32_t setuptime; /*!< configure the address setup time */ }exmc_nand_pccard_timing_parameter_struct; -/* EXMC NAND initialize struct */ +/* EXMC NAND initialize structure */ typedef struct { uint32_t nand_bank; /*!< select the bank of NAND */ @@ -301,7 +299,7 @@ typedef struct exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ }exmc_nand_parameter_struct; -/* EXMC PC card initialize struct */ +/* EXMC PC card initialize structure */ typedef struct { uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ @@ -312,7 +310,7 @@ typedef struct exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ }exmc_pccard_parameter_struct; -/* EXMC SDRAM timing initialize struct */ +/* EXMC SDRAM timing initialize structure */ typedef struct { uint32_t row_to_column_delay; /*!< configure the row to column delay */ @@ -324,12 +322,12 @@ typedef struct uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ }exmc_sdram_timing_parameter_struct; -/* EXMC SDRAM initialize struct */ +/* EXMC SDRAM initialize structure */ typedef struct { uint32_t sdram_device; /*!< device of SDRAM */ uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ - uint32_t brust_read_switch; /*!< enable or disable the burst read */ + uint32_t burst_read_switch; /*!< enable or disable the burst read */ uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ @@ -340,7 +338,7 @@ typedef struct exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ }exmc_sdram_parameter_struct; -/* EXMC SDRAM command initialize struct */ +/* EXMC SDRAM command initialize structure */ typedef struct { uint32_t mode_register_content; /*!< the SDRAM mode register content */ @@ -349,7 +347,7 @@ typedef struct uint32_t command; /*!< the commands that will be sent to SDRAM */ }exmc_sdram_command_parameter_struct; -/* EXMC SQPISRAM initialize struct */ +/* EXMC SQPISRAM initialize structure */ typedef struct{ uint32_t sample_polarity; /*!< read data sample polarity */ uint32_t id_length; /*!< SPI PSRAM ID length */ @@ -357,7 +355,7 @@ typedef struct{ uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ }exmc_sqpipsram_parameter_struct; -/* EXMC_register address */ +/* EXMC register address */ #define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ #define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ @@ -419,21 +417,21 @@ typedef struct{ /* synchronous clock divide ratio */ #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = HCLK/2 */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = HCLK/3 */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = HCLK/4 */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = HCLK/5 */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = HCLK/6 */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = HCLK/7 */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = HCLK/8 */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = HCLK/9 */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = HCLK/10 */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = HCLK/11 */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = HCLK/12 */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = HCLK/13 */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = HCLK/14 */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = HCLK/15 */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = HCLK/16 */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ /* ECC size */ #define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) @@ -542,7 +540,7 @@ typedef struct{ #define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ #define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ -/* SDRAM command select */ +/* SDRAM command selection */ #define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) #define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ #define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ @@ -662,13 +660,13 @@ typedef struct{ #define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ #define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ -/* SDRAM device0 select */ -#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */ -#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */ +/* SDRAM device0 selection */ +#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */ +#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */ -/* SDRAM device1 select */ -#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */ -#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */ +/* SDRAM device1 selection */ +#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */ +#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */ /* SDRAM device status */ #define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ @@ -717,7 +715,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region); /* NAND */ /* deinitialize EXMC NAND bank */ void exmc_nand_deinit(uint32_t exmc_nand_bank); -/* initialize exmc_norsram_parameter_struct with the default values */ +/* initialize exmc_nand_parameter_struct with the default values */ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); /* initialize EXMC NAND bank */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); @@ -743,6 +741,8 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device); void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); /* initialize EXMC SDRAM device */ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize exmc_sdram_command_parameter_struct with the default values */ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); /* SQPIPSRAM */ /* deinitialize EXMC SQPIPSRAM */ void exmc_sqpipsram_deinit(void); @@ -773,7 +773,7 @@ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_c void exmc_sdram_refresh_count_set(uint32_t exmc_count); /* set the number of successive auto-refresh command */ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); -/* config the write protection function */ +/* configure the write protection function */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); /* get the status of SDRAM device0 or device1 */ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h index 70d941a..055af41 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h @@ -1,14 +1,11 @@ /*! \file gd32f4xx_exti.h \brief definitions for the EXTI - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -177,34 +174,33 @@ OF SUCH DAMAGE. #define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ /* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ -#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ -#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt pending status from line 20 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt pending status from line 22 */ /* constants definitions */ /* EXTI line number */ -typedef enum -{ +typedef enum { EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ @@ -227,29 +223,27 @@ typedef enum EXTI_19 = BIT(19), /*!< EXTI line 19 */ EXTI_20 = BIT(20), /*!< EXTI line 20 */ EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ -}exti_line_enum; + EXTI_22 = BIT(22) /*!< EXTI line 22 */ +} exti_line_enum; /* external interrupt and event */ -typedef enum -{ +typedef enum { EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; +} exti_mode_enum; /* interrupt trigger mode */ -typedef enum -{ +typedef enum { EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ EXTI_TRIG_NONE /*!< none EXTI edge trigger */ -}exti_trig_type_enum; +} exti_trig_type_enum; /* function declarations */ /* deinitialize the EXTI */ void exti_deinit(void); -/* enable the configuration of EXTI initialize */ +/* initialize the EXTI line x */ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); @@ -259,19 +253,19 @@ void exti_interrupt_disable(exti_line_enum linex); void exti_event_enable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); -/* EXTI software interrupt event enable */ +/* enable the software interrupt event from EXTI line x */ void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ +/* disable the software interrupt event from EXTI line x */ void exti_software_interrupt_disable(exti_line_enum linex); /* interrupt & flag functions */ -/* get EXTI lines pending flag */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); #endif /* GD32F4XX_EXTI_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h index ac62970..192048d 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h @@ -2,36 +2,33 @@ \file gd32f4xx_fmc.h \brief definitions for the FMC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx - \version 2020-12-20, V2.1.1, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -46,15 +43,17 @@ OF SUCH DAMAGE. #define OB OB_BASE /*!< option byte base address */ /* registers definitions */ -#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */ -#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */ -#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */ -#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */ -#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */ +#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */ +#define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control register 0 */ +#define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control register 1 */ +#define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration register */ +#define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key register */ +#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */ #define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ #define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ @@ -108,6 +107,13 @@ OF SUCH DAMAGE. /* FMC_OBCTL1 */ #define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ +/* FMC_PECFG */ +#define FMC_PE_EN BIT(31) /*!< the enable bit of page erase function */ +#define FMC_PE_ADDR BITS(0,28) /*!< page erase address */ + +/* FMC_PEKEY */ +#define FMC_PE_KEY BITS(0,31) /*!< FMC_PECFG unlock key value */ + /* FMC_WSEN */ #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ @@ -116,22 +122,21 @@ OF SUCH DAMAGE. /* constants definitions */ /* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ +typedef enum { + FMC_READY = 0, /*!< the operation has been completed */ FMC_BUSY, /*!< the operation is in progress */ FMC_RDDERR, /*!< read D-bus protection error */ FMC_PGSERR, /*!< program sequence error */ FMC_PGMERR, /*!< program size not match error */ FMC_WPERR, /*!< erase/program protection error */ FMC_OPERR, /*!< operation error */ - FMC_PGERR, /*!< program error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; + FMC_TOERR /*!< timeout error */ +} fmc_state_enum; /* unlock key */ #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ +#define UNLOCK_PE_KEY ((uint32_t)0xA9B8C7D6U) /*!< unlock page erase function key */ #define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ #define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ @@ -171,7 +176,7 @@ typedef enum #define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ #define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ -/* option byte software/hardware free watch dog timer */ +/* option byte software/hardware free watch dog timer */ #define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) #define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ #define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ @@ -243,14 +248,15 @@ typedef enum #define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ #define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ #define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ +#define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */ -/* double banks or single bank selection when flash size is 1M bytes */ -#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30)) +/* double banks or single bank selection when flash size is 1M bytes */ +#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U)) #define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ #define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ -/* option bytes D-bus read protection mode */ -#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31)) +/* option bytes D-bus read protection mode */ +#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U)) #define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ #define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ @@ -286,8 +292,8 @@ typedef enum #define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ -/* FMC program size */ -#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8) +/* FMC program size */ +#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U) #define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ #define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ #define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ @@ -297,16 +303,25 @@ typedef enum #define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ /* FMC flags */ -#define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */ -#define FMC_FLAG_OPERR ((uint32_t)0x00000002U) /*!< FMC operation error flag bit */ -#define FMC_FLAG_WPERR ((uint32_t)0x00000010U) /*!< FMC erase/program protection error flag bit */ -#define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */ -#define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */ -#define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */ -#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ +#define FMC_FLAG_END FMC_STAT_END /*!< FMC end of operation flag bit */ +#define FMC_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error flag bit */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag bit */ +#define FMC_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error flag bit */ +#define FMC_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error flag bit */ +#define FMC_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error flag bit */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ + +/* FMC interrupt flags */ +#define FMC_INT_FLAG_END FMC_STAT_END /*!< FMC end of operation interrupt flag */ +#define FMC_INT_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error interrupt flag */ +#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */ +#define FMC_INT_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error interrupt flag */ +#define FMC_INT_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error interrupt flag */ +#define FMC_INT_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error interrupt flag */ + /* FMC time out */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0xFFFFFFFFU) /*!< count to judge of FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x4FFFFFFFU) /*!< count to judge of FMC timeout */ /* function declarations */ /* FMC main memory programming functions */ @@ -316,6 +331,10 @@ void fmc_wscnt_set(uint32_t wscnt); void fmc_unlock(void); /* lock the main FMC operation */ void fmc_lock(void); +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_addr); +#endif /* FMC erase sector */ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector); /* FMC erase whole chip */ @@ -341,22 +360,26 @@ void ob_start(void); /* erase option byte */ void ob_erase(void); /* enable write protect */ -void ob_write_protection_enable(uint32_t ob_wp); +ErrStatus ob_write_protection_enable(uint32_t ob_wp); /* disable write protect */ -void ob_write_protection_disable(uint32_t ob_wp); +ErrStatus ob_write_protection_disable(uint32_t ob_wp); /* enable erase/program protection and D-bus read protection */ void ob_drp_enable(uint32_t ob_drp); /* disable erase/program protection and D-bus read protection */ -void ob_drp_disable(uint32_t ob_drp); -/* set the option byte security protection level */ +void ob_drp_disable(void); +/* configure security protection level */ void ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte user */ +/* program the FMC user option byte */ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); -/* option byte BOR threshold value */ +/* program the option byte BOR threshold value */ void ob_user_bor_threshold(uint32_t ob_bor_th); /* configure the boot mode */ void ob_boot_mode_config(uint32_t boot_mode); -/* get the FMC option byte user */ +#if defined (GD32F450) || defined (GD32F470) +/* configure the double bank select */ +void ob_double_bank_select(uint32_t double_bank); +#endif +/* get the FMC user option byte */ uint8_t ob_user_get(void); /* get the FMC option byte write protection */ uint16_t ob_write_protection0_get(void); @@ -368,21 +391,25 @@ uint16_t ob_drp0_get(void); uint16_t ob_drp1_get(void); /* get option byte security protection code value */ FlagStatus ob_spc_get(void); -/* get the FMC threshold value */ +/* get the FMC option byte BOR threshold value */ uint8_t ob_user_bor_threshold_get(void); /* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t fmc_int); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t fmc_int); /* get flag set or reset */ FlagStatus fmc_flag_get(uint32_t fmc_flag); /* clear the FMC pending flag */ void fmc_flag_clear(uint32_t fmc_flag); -/* return the FMC state */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t fmc_int); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t fmc_int); +/* get FMC interrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag); +/* clear the FMC interrupt flag */ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag); +/* get the FMC state */ fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ +/* check whether FMC is ready or not */ fmc_state_enum fmc_ready_wait(uint32_t timeout); #endif /* GD32F4XX_FMC_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h index 3896b98..39a8df6 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h @@ -1,14 +1,12 @@ /*! \file gd32f4xx_fwdgt.h \brief definitions for the FWDGT - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* FWDGT definitions */ -#define FWDGT FWDGT_BASE +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ /* registers definitions */ #define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ @@ -87,6 +85,9 @@ OF SUCH DAMAGE. #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* enable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_enable(void); @@ -95,6 +96,10 @@ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ void fwdgt_enable(void); +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); /* reload the counter of FWDGT */ void fwdgt_counter_reload(void); /* configure counter reload value, and prescaler divider value */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h index 6a363da..2d883b7 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h @@ -1,14 +1,12 @@ /*! \file gd32f4xx_gpio.h \brief definitions for the GPIO - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,7 +55,7 @@ OF SUCH DAMAGE. #define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operate register */ #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ #define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ #define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ @@ -156,22 +154,22 @@ OF SUCH DAMAGE. #define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ /* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output control bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output control bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output control bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output control bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output control bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output control bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output control bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output control bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output control bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output control bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output control bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output control bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output control bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output control bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output control bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output control bit */ /* GPIO_BOP */ #define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ @@ -224,7 +222,7 @@ OF SUCH DAMAGE. #define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ #define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ #define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin lock sequence key */ /* GPIO_AFSEL0 */ #define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ @@ -344,7 +342,7 @@ typedef FlagStatus bit_status; #define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ #define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ #define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ -#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */ +#define GPIO_OSPEED_MAX GPIO_OSPEED_LEVEL3 /*!< GPIO very high output speed, max speed more than 50MHz */ /* GPIO alternate function values */ #define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h index bcb6843..8803e9a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h @@ -1,326 +1,313 @@ /*! \file gd32f4xx_i2c.h \brief definitions for the I2C - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-04-16, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - #ifndef GD32F4XX_I2C_H #define GD32F4XX_I2C_H #include "gd32f4xx.h" /* I2Cx(x=0,1,2) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ -#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE + 0x00000800U) /*!< I2C2 base address */ /* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ -#define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */ -#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control register */ +#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ /* bits definitions */ /* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ /* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ /* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ /* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ /* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ /* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ /* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ /* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ /* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ /* I2Cx_FCTL */ -#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ -#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ +#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ +#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ /* I2Cx_SAMCS */ -#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ -#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ -#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ -#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ -#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ -#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ -#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ -#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ - -/* constants definitions */ - -/* the digital noise filter can filter spikes's length */ -typedef enum { - I2C_DF_DISABLE, /*!< disable digital noise filter */ - I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ - I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ - I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ - I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ - I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ - I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ - I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ - I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ - I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ - I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ - I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ - I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ - I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ - I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ - I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ -}i2c_digital_filter_enum; +#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ +#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ +#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ +#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ +#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ +#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ +#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ +#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ +#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ +#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ +#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ +#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ /* constants definitions */ /* define the I2C bit position and its register index offset */ #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) /* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ +#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ /* I2C flags */ -typedef enum -{ +typedef enum { /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ /* flags in SAMCS register */ - I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ - I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ - I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ - I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ -}i2c_flag_enum; + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +} i2c_flag_enum; /* I2C interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in CTL1 register */ I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ /* interrupt flags in SAMCS register */ - I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ - I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ - I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ -}i2c_interrupt_flag_enum; + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +} i2c_interrupt_flag_enum; -/* I2C interrupt enable or disable */ -typedef enum -{ +/* I2C interrupt */ +typedef enum { /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ /* interrupt in SAMCS register */ - I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ - I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ - I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ - I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ -}i2c_interrupt_enum; + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */ +} i2c_interrupt_enum; + +/* the digital noise filter can filter spikes's length */ +typedef enum { + I2C_DF_DISABLE = 0, /*!< disable digital noise filter */ + I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ + I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ + I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ + I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ + I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ + I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ + I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ + I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ + I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ + I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ + I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ + I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ + I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ + I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ + I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ +} i2c_digital_filter_enum; /* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ /* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ /* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ /* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ /* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ +#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ /* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ /* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ /* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ /* I2C DMA mode configure */ /* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ /* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ /* I2C PEC configure */ /* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ /* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ /* I2C SMBus configure */ /* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ /* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ /* transmit I2C data */ #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) @@ -329,21 +316,24 @@ typedef enum #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) /* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */ /* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ /* function declarations */ +/* initialization functions */ /* reset I2C */ void i2c_deinit(uint32_t i2c_periph); /* configure I2C clock */ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); /* configure I2C address */ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ + +/* application function declarations */ +/* select SMBus type */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); /* whether or not to send an ACK */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); @@ -359,7 +349,6 @@ void i2c_dualaddr_disable(uint32_t i2c_periph); void i2c_enable(uint32_t i2c_periph); /* disable I2C */ void i2c_disable(uint32_t i2c_periph); - /* generate a START condition on I2C bus */ void i2c_start_on_bus(uint32_t i2c_periph); /* generate a STOP condition on I2C bus */ @@ -368,35 +357,32 @@ void i2c_stop_on_bus(uint32_t i2c_periph); void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); /* I2C receive data function */ uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure I2C DMA mode */ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); /* configure whether next DMA EOT is DMA last transfer or not */ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); /* whether to stretch SCL low when data is not ready in slave mode */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); /* whether or not to response to a general call */ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ +/* configure software reset of I2C */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ +/* configure I2C PEC calculation */ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); +/* configure whether to transfer PEC value */ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); +/* get packet error checking value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* I2C analog noise filter disable */ +/* configure I2C alert through SMBA pin */ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); +/* configure I2C ARP protocol in SMBus */ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); +/* disable analog noise filter */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph); -/* I2C analog noise filter enable */ +/* enable analog noise filter */ void i2c_analog_noise_filter_enable(uint32_t i2c_periph); -/* digital noise filter */ -void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara); - +/* configure digital noise filter */ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara); /* enable SAM_V interface */ void i2c_sam_enable(uint32_t i2c_periph); /* disable SAM_V interface */ @@ -406,17 +392,18 @@ void i2c_sam_timeout_enable(uint32_t i2c_periph); /* disable SAM_V interface timeout detect */ void i2c_sam_timeout_disable(uint32_t i2c_periph); -/* check I2C flag is set or not */ +/* interrupt & flag functions */ +/* get I2C flag status */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ +/* clear I2C flag status */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); /* enable I2C interrupt */ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); /* disable I2C interrupt */ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ +/* get I2C interrupt flag status */ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ +/* clear I2C interrupt flag status */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); #endif /* GD32F4XX_I2C_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h index 84cceeb..8641378 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h @@ -1,36 +1,34 @@ /*! \file gd32f4xx_ipa.h \brief definitions for the IPA - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,30 +38,30 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* TLI definitions */ -#define IPA IPA_BASE /*!< IPA base address */ +#define IPA IPA_BASE /*!< IPA base address */ /* bits definitions */ /* registers definitions */ -#define IPA_CTL REG32(IPA + 0x00U) /*!< IPA control register */ -#define IPA_INTF REG32(IPA + 0x04U) /*!< IPA interrupt flag register */ -#define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */ -#define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */ -#define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */ -#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ -#define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */ -#define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */ -#define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */ -#define IPA_BPCTL REG32(IPA + 0x24U) /*!< IPA background pixel control register */ -#define IPA_BPV REG32(IPA + 0x28U) /*!< IPA background pixel value register */ -#define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */ -#define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */ -#define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */ -#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ -#define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */ -#define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */ -#define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */ -#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ -#define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */ +#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */ +#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */ +#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */ +#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */ +#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */ +#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */ +#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */ +#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */ +#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */ +#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */ +#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */ +#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */ +#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */ +#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */ +#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */ +#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */ +#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */ +#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */ +#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */ +#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */ /* IPA_CTL */ #define IPA_CTL_TEN BIT(0) /*!< transfer enable */ @@ -189,8 +187,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* IPA foreground parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t foreground_memaddr; /*!< foreground memory base address */ uint32_t foreground_lineoff; /*!< foreground line offset */ uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ @@ -199,11 +196,10 @@ typedef struct uint32_t foreground_prered; /*!< foreground pre-defined red value */ uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ -}ipa_foreground_parameter_struct; +} ipa_foreground_parameter_struct; /* IPA background parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t background_memaddr; /*!< background memory base address */ uint32_t background_lineoff; /*!< background line offset */ uint32_t background_prealpha; /*!< background pre-defined alpha value */ @@ -212,11 +208,10 @@ typedef struct uint32_t background_prered; /*!< background pre-defined red value */ uint32_t background_pregreen; /*!< background pre-defined green value */ uint32_t background_preblue; /*!< background pre-defined blue value */ -}ipa_background_parameter_struct; +} ipa_background_parameter_struct; /* IPA destination parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t destination_memaddr; /*!< destination memory base address */ uint32_t destination_lineoff; /*!< destination line offset */ uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ @@ -226,11 +221,10 @@ typedef struct uint32_t destination_preblue; /*!< destination pre-defined blue value */ uint32_t image_width; /*!< width of the image to be processed */ uint32_t image_height; /*!< height of the image to be processed */ -}ipa_destination_parameter_struct; +} ipa_destination_parameter_struct; /* destination pixel format */ -typedef enum -{ +typedef enum { IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ @@ -339,21 +333,21 @@ void ipa_background_lut_loading_enable(void); void ipa_pixel_format_convert_mode_set(uint32_t pfcm); /* structure initialization, foreground, background, destination and LUT initialization */ -/* initialize the structure of IPA foreground parameter struct with the default values, it is +/* initialize the structure of IPA foreground parameter struct with the default values, it is suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ -void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct); +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct); /* initialize foreground parameters */ -void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct); -/* initialize the structure of IPA background parameter struct with the default values, it is +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct); +/* initialize the structure of IPA background parameter struct with the default values, it is suggested that call this function after an ipa_background_parameter_struct structure is defined */ -void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct); +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct); /* initialize background parameters */ -void ipa_background_init(ipa_background_parameter_struct* background_struct); -/* initialize the structure of IPA destination parameter struct with the default values, it is +void ipa_background_init(ipa_background_parameter_struct *background_struct); +/* initialize the structure of IPA destination parameter struct with the default values, it is suggested that call this function after an ipa_destination_parameter_struct structure is defined */ -void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct); +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct); /* initialize destination parameters */ -void ipa_destination_init(ipa_destination_parameter_struct* destination_struct); +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct); /* initialize IPA foreground LUT parameters */ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); /* initialize IPA background LUT parameters */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h index 44897a2..4189fa4 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h @@ -2,13 +2,11 @@ \file gd32f4xx_iref.h \brief definitions for the IREF - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -167,7 +165,7 @@ OF SUCH DAMAGE. #define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ /* function declarations */ -/* deinit IREF */ +/* deinitialize IREF */ void iref_deinit(void); /* enable IREF */ void iref_enable(void); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h index e618af4..1a672d5 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h @@ -1,14 +1,11 @@ /*! \file gd32f4xx_misc.h \brief definitions for the MISC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -41,8 +38,8 @@ OF SUCH DAMAGE. /* constants definitions */ /* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ /* set the NVIC vector table offset mask */ #define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) @@ -51,24 +48,24 @@ OF SUCH DAMAGE. #define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ #define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT #define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP #define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ /* function declarations */ /* set the priority group */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h index b80748c..4f5bf28 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h @@ -2,13 +2,11 @@ \file gd32f4xx_pmu.h \brief definitions for the PMU - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -41,159 +39,165 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ +#define PMU PMU_BASE /*!< PMU base address */ /* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ +#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ /* bits definitions */ /* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ -#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ -#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ -#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ /* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ -#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ -#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ -#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ -#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ +#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ /* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */ + /* PMU low voltage detector threshold definitions */ #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU low-driver mode when use low power LDO */ +#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) +#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU low-driver mode when use normal power LDO */ +#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) +#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ /* PMU LDO output voltage select definitions */ #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ -#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ -#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ -/* PMU low-driver mode enable in deep-sleep mode */ -#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ -#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ /* PMU high-driver mode switch */ #define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) -#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ -#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ -/* PMU low-driver mode when use low power LDO */ -#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) -#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ -#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ +/* PMU low-driver mode enable in deep-sleep mode */ +#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ -/* PMU low-driver mode when use normal power LDO */ -#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) -#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ -#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ +/* PMU backup SRAM LDO on or off */ +#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) +#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ +#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ /* PMU low power mode ready flag definitions */ #define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ -#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ - -/* PMU backup SRAM LDO on or off */ -#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) -#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ -#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ /* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ -#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ -#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ -#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ -#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ -#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ +#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ /* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ /* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ /* function declarations */ -/* reset PMU register */ +/* reset PMU registers */ void pmu_deinit(void); +/* LVD functions */ /* select low voltage detector threshold */ void pmu_lvd_select(uint32_t lvdt_n); -/* LDO output voltage select */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* PMU lvd disable */ +/* disable PMU lvd */ void pmu_lvd_disable(void); -/* functions of low-driver mode and high-driver mode in deep-sleep mode */ -/* high-driver mode switch */ -void pmu_highdriver_switch_select(uint32_t highdr_switch); -/* high-driver mode enable */ +/* LDO functions */ +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); + +/* functions of low-driver mode and high-driver mode */ +/* enable high-driver mode */ void pmu_highdriver_mode_enable(void); -/* high-driver mode disable */ +/* disable high-driver mode */ void pmu_highdriver_mode_disable(void); -/* low-driver mode enable in deep-sleep mode */ -void pmu_low_driver_mode_enable(uint32_t lowdr_mode); -/* in deep-sleep mode, low-driver mode when use low power LDO */ -void pmu_lowdriver_lowpower_config(uint32_t mode); -/* in deep-sleep mode, low-driver mode when use normal power LDO */ -void pmu_lowdriver_normalpower_config(uint32_t mode); +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* enable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_disable(void); +/* in deep-sleep mode, driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); /* set PMU mode */ -/* PMU work at sleep mode */ +/* PMU work in sleep mode */ void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* PMU wakeup pin enable */ +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); +/* enable PMU wakeup pin */ void pmu_wakeup_pin_enable(void); -/* PMU wakeup pin disable */ +/* disable PMU wakeup pin */ void pmu_wakeup_pin_disable(void); /* backup related functions */ /* backup SRAM LDO on */ void pmu_backup_ldo_config(uint32_t bkp_ldo); -/* backup domain write enable */ +/* enable write access to the registers in backup domain */ void pmu_backup_write_enable(void); -/* backup domain write disable */ +/* disable write access to the registers in backup domain */ void pmu_backup_write_disable(void); /* flag functions */ -/* reset flag bit */ -void pmu_flag_reset(uint32_t flag_reset); -/* get flag status */ -FlagStatus pmu_flag_get(uint32_t pmu_flag); +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); #endif /* GD32F4XX_PMU_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h index 8aea0fc..dfea500 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h @@ -2,13 +2,11 @@ \file gd32f4xx_rcu.h \brief definitions for the RCU - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -397,13 +395,11 @@ OF SUCH DAMAGE. /* RCU_PLLI2S */ #define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ -#define RCU_PLLI2S_PLLI2SQ BITS(24,27) /*!< the PLLI2S Q output frequency division factor from PLLI2S VCO clock */ #define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ /* RCU_PLLSAI */ #define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ #define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAI_PLLSAIQ BITS(24,27) /*!< the PLLSAI Q output frequency division factor from PLLSAI VCO clock */ #define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ /* RCU_CFG1 */ @@ -1068,13 +1064,14 @@ typedef enum /* Deep-sleep mode voltage */ #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode(customers are not recommended to use it)*/ /* function declarations */ +/* peripherals clock configure functions */ /* deinitialize the RCU */ void rcu_deinit(void); /* enable the peripherals clock */ @@ -1094,6 +1091,7 @@ void rcu_bkp_reset_enable(void); /* disable the BKP reset */ void rcu_bkp_reset_disable(void); +/* system and peripherals clock source, system reset configure functions */ /* configure the system clock source */ void rcu_system_clock_source_config(uint32_t ck_sys); /* get the system clock source */ @@ -1129,20 +1127,7 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); /* configure the TLI clock division selection */ void rcu_tli_clock_div_config(uint32_t pllsai_r_div); - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum interrupt); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum interrupt); - +/* LXTAL, IRC8M, PLL and other oscillator configure functions */ /* configure the LXTAL drive capability */ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ @@ -1155,11 +1140,6 @@ void rcu_osci_off(rcu_osci_type_enum osci); void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - /* set the IRC16M adjust value */ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); /* configure the spread spectrum modulation for the main PLL clock */ @@ -1167,13 +1147,34 @@ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, /* enable the spread spectrum modulation for the main PLL clock */ void rcu_spread_spectrum_enable(void); /* disable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_disable(void); +void rcu_spread_spectrum_disable(void); + +/* clock monitor configure functions */ +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* voltage configure and clock frequency get functions */ /* unlock the voltage key */ void rcu_voltage_key_unlock(void); /* set the deep sleep mode voltage */ void rcu_deepsleep_voltage_set(uint32_t dsvol); - /* get the system clock, bus and peripheral clock frequency */ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); +/* flag & interrupt functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum interrupt); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum interrupt); + #endif /* GD32F4XX_RCU_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h index 2cc9461..3bf1f64 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h @@ -2,13 +2,11 @@ \file gd32f4xx_rtc.c \brief definitions for the RTC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -524,7 +522,7 @@ typedef struct #define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ /* RTC flags */ -#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ +#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ #define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ #define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ #define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h index d6ee114..ea0ec88 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h @@ -1,36 +1,34 @@ /*! \file gd32f4xx_sdio.h \brief definitions for the SDIO - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -43,24 +41,24 @@ OF SUCH DAMAGE. #define SDIO SDIO_BASE /* registers definitions */ -#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ -#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ -#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ -#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ -#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ -#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ -#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ -#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ -#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ -#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ -#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ -#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ -#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ -#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ -#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ -#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ -#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ -#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ +#define SDIO_PWRCTL REG32(SDIO + 0x00000000U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x00000004U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x00000008U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0000000CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x00000010U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x00000014U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x00000018U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x0000001CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x00000020U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x00000024U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x00000028U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x0000002CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x00000030U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x00000034U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x00000038U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x0000003CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x00000048U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x00000080U) /*!< SDIO FIFO data register */ /* bits definitions */ /* SDIO_PWRCTL */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h index 5eb3803..1c2ccdf 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h @@ -2,35 +2,33 @@ \file gd32f4xx_spi.h \brief definitions for the SPI - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -53,27 +51,27 @@ OF SUCH DAMAGE. #define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U) /* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register */ /* I2S_ADD registers definitions */ -#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */ -#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/ -#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */ -#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */ -#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */ -#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */ -#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */ -#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */ -#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ +#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */ +#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/ +#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */ +#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */ +#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */ +#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */ +#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */ +#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */ +#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */ /* bits definitions */ /* SPI_CTL0 */ @@ -146,8 +144,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* SPI and I2S parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t device_mode; /*!< SPI master or slave */ uint32_t trans_mode; /*!< SPI transtype */ uint32_t frame_size; /*!< SPI frame size */ @@ -155,7 +152,7 @@ typedef struct uint32_t endian; /*!< SPI big endian or little endian */ uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; +} spi_parameter_struct; /* SPI mode definitions */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ @@ -241,7 +238,7 @@ typedef struct #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ -/* SPI DMA constants definitions */ +/* SPI DMA constants definitions */ #define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ #define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ @@ -263,7 +260,7 @@ typedef struct #define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ #define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ -/* SPI/I2S flag definitions */ +/* SPI/I2S flag definitions */ #define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ #define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ @@ -283,19 +280,19 @@ typedef struct /* initialization functions */ /* deinitialize SPI and I2S */ void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize the parameters of SPI struct with default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); /* initialize SPI parameter */ -void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct); +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); /* enable SPI */ void spi_enable(uint32_t spi_periph); /* disable SPI */ void spi_disable(uint32_t spi_periph); /* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl); +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl); /* configure I2S prescale */ -void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout); +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout); /* enable I2S */ void i2s_enable(uint32_t spi_periph); /* disable I2S */ @@ -312,24 +309,28 @@ void spi_nss_internal_high(uint32_t spi_periph); void spi_nss_internal_low(uint32_t spi_periph); /* SPI DMA functions */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma); +/* enable SPI DMA send or receive */ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma); +/* diable SPI DMA send or receive */ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma); /* SPI/I2S transfer configure functions */ /* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format); +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); /* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data); +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); /* SPI receive data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph); /* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction); +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); +/* configure i2s full duplex mode */ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat); +/* clear TI Mode Format Error flag status */ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag); /* SPI CRC functions */ /* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly); +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); /* get SPI CRC polynomial */ uint16_t spi_crc_polynomial_get(uint32_t spi_periph); /* turn on SPI CRC function */ @@ -339,7 +340,9 @@ void spi_crc_off(uint32_t spi_periph); /* SPI next data is CRC value */ void spi_crc_next(uint32_t spi_periph); /* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc); +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); /* SPI TI mode functions */ /* enable SPI TI mode */ @@ -347,33 +350,28 @@ void spi_ti_mode_enable(uint32_t spi_periph); /* disable SPI TI mode */ void spi_ti_mode_disable(uint32_t spi_periph); -/* configure i2s full duplex mode */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat); - /* quad wire SPI functions */ /* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); +void spi_quad_enable(uint32_t spi_periph); /* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); +void spi_quad_disable(uint32_t spi_periph); /* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); +void spi_quad_write_enable(uint32_t spi_periph); /* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); - -/* flag & interrupt functions */ -/* enable SPI interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* disable SPI interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* get SPI and I2S interrupt status*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int); +void spi_quad_read_enable(uint32_t spi_periph); +/* enable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); + +/* flag and interrupt functions */ /* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); #endif /* GD32F4XX_SPI_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h index 749517f..ae32ff8 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h @@ -2,13 +2,11 @@ \file gd32f4xx_syscfg.h \brief definitions for the SYSCFG - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h index bc38efa..6e5fc52 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h @@ -2,14 +2,11 @@ \file gd32f4xx_timer.h \brief definitions for the TIMER - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - All rights reserved. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -341,8 +338,6 @@ typedef struct #define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ #define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF - - /* TIMER DMA source enable */ #define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ #define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ @@ -418,8 +413,8 @@ typedef struct #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ /* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ /* count direction */ #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ @@ -432,12 +427,12 @@ typedef struct #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ /* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ /* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ /* run mode off-state configure */ #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ @@ -539,7 +534,7 @@ typedef struct #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ /* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ @@ -563,17 +558,17 @@ typedef struct /* slave mode control */ #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ +#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ +#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */ #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ /* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ /* external trigger prescaler */ #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) @@ -587,8 +582,8 @@ typedef struct #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ /* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ /* timer1 internal trigger input1 remap */ #define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) @@ -610,8 +605,8 @@ typedef struct #define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ /* timerx(x=0,1,2,13,14,15,16) write cc register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ /* the output value selection */ #define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ @@ -660,20 +655,6 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); /* configure TIMER update source */ void timer_update_source_config(uint32_t timer_periph, uint32_t update); -/* TIMER interrupt and flag*/ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - /* timer DMA and event*/ /* enable the TIMER DMA */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma); @@ -778,4 +759,18 @@ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); /* configure TIMER output value selection */ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); +/* TIMER interrupt and flag*/ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); + #endif /* GD32F4XX_TIMER_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h index c3078b7..1413790 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h @@ -1,36 +1,34 @@ /*! \file gd32f4xx_tli.h \brief definitions for the TLI - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,37 +38,37 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* TLI definitions */ -#define TLI TLI_BASE /*!< TLI base address */ +#define TLI TLI_BASE /*!< TLI base address */ /* TLI layer definitions */ -#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ -#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */ +#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ +#define LAYER1 (TLI_BASE + 0x00000080U) /*!< TLI layer1 base address */ /* registers definitions */ -#define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */ -#define TLI_BPSZ REG32(TLI + 0x0CU) /*!< TLI back-porch size register */ -#define TLI_ASZ REG32(TLI + 0x10U) /*!< TLI active size register */ -#define TLI_TSZ REG32(TLI + 0x14U) /*!< TLI total size register */ -#define TLI_CTL REG32(TLI + 0x18U) /*!< TLI control register */ -#define TLI_RL REG32(TLI + 0x24U) /*!< TLI reload Layer register */ -#define TLI_BGC REG32(TLI + 0x2CU) /*!< TLI background color register */ -#define TLI_INTEN REG32(TLI + 0x34U) /*!< TLI interrupt enable register */ -#define TLI_INTF REG32(TLI + 0x38U) /*!< TLI interrupt flag register */ -#define TLI_INTC REG32(TLI + 0x3CU) /*!< TLI interrupt flag clear register */ -#define TLI_LM REG32(TLI + 0x40U) /*!< TLI line mark register */ -#define TLI_CPPOS REG32(TLI + 0x44U) /*!< TLI current pixel position register */ -#define TLI_STAT REG32(TLI + 0x48U) /*!< TLI status register */ -#define TLI_LxCTL(layerx) REG32((layerx) + 0x84U) /*!< TLI layer x control register */ -#define TLI_LxHPOS(layerx) REG32((layerx) + 0x88U) /*!< TLI layer x horizontal position parameters register */ -#define TLI_LxVPOS(layerx) REG32((layerx) + 0x8CU) /*!< TLI layer x vertical position parameters register */ -#define TLI_LxCKEY(layerx) REG32((layerx) + 0x90U) /*!< TLI layer x color key register */ -#define TLI_LxPPF(layerx) REG32((layerx) + 0x94U) /*!< TLI layer x packeted pixel format register */ -#define TLI_LxSA(layerx) REG32((layerx) + 0x98U) /*!< TLI layer x specified alpha register */ -#define TLI_LxDC(layerx) REG32((layerx) + 0x9CU) /*!< TLI layer x default color register */ -#define TLI_LxBLEND(layerx) REG32((layerx) + 0xA0U) /*!< TLI layer x blending register */ -#define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */ -#define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */ -#define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */ -#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */ +#define TLI_SPSZ REG32(TLI + 0x00000008U) /*!< TLI synchronous pulse size register */ +#define TLI_BPSZ REG32(TLI + 0x0000000CU) /*!< TLI back-porch size register */ +#define TLI_ASZ REG32(TLI + 0x00000010U) /*!< TLI active size register */ +#define TLI_TSZ REG32(TLI + 0x00000014U) /*!< TLI total size register */ +#define TLI_CTL REG32(TLI + 0x00000018U) /*!< TLI control register */ +#define TLI_RL REG32(TLI + 0x00000024U) /*!< TLI reload Layer register */ +#define TLI_BGC REG32(TLI + 0x0000002CU) /*!< TLI background color register */ +#define TLI_INTEN REG32(TLI + 0x00000034U) /*!< TLI interrupt enable register */ +#define TLI_INTF REG32(TLI + 0x00000038U) /*!< TLI interrupt flag register */ +#define TLI_INTC REG32(TLI + 0x0000003CU) /*!< TLI interrupt flag clear register */ +#define TLI_LM REG32(TLI + 0x00000040U) /*!< TLI line mark register */ +#define TLI_CPPOS REG32(TLI + 0x00000044U) /*!< TLI current pixel position register */ +#define TLI_STAT REG32(TLI + 0x00000048U) /*!< TLI status register */ +#define TLI_LxCTL(layerx) REG32((layerx) + 0x00000084U) /*!< TLI layer x control register */ +#define TLI_LxHPOS(layerx) REG32((layerx) + 0x00000088U) /*!< TLI layer x horizontal position parameters register */ +#define TLI_LxVPOS(layerx) REG32((layerx) + 0x0000008CU) /*!< TLI layer x vertical position parameters register */ +#define TLI_LxCKEY(layerx) REG32((layerx) + 0x00000090U) /*!< TLI layer x color key register */ +#define TLI_LxPPF(layerx) REG32((layerx) + 0x00000094U) /*!< TLI layer x packeted pixel format register */ +#define TLI_LxSA(layerx) REG32((layerx) + 0x00000098U) /*!< TLI layer x specified alpha register */ +#define TLI_LxDC(layerx) REG32((layerx) + 0x0000009CU) /*!< TLI layer x default color register */ +#define TLI_LxBLEND(layerx) REG32((layerx) + 0x000000A0U) /*!< TLI layer x blending register */ +#define TLI_LxFBADDR(layerx) REG32((layerx) + 0x000000ACU) /*!< TLI layer x frame base address register */ +#define TLI_LxFLLEN(layerx) REG32((layerx) + 0x000000B0U) /*!< TLI layer x frame line length register */ +#define TLI_LxFTLN(layerx) REG32((layerx) + 0x000000B4U) /*!< TLI layer x frame total line number register */ +#define TLI_LxLUT(layerx) REG32((layerx) + 0x000000C4U) /*!< TLI layer x look up table register */ /* bits definitions */ /* TLI_SPSZ */ @@ -85,7 +83,7 @@ OF SUCH DAMAGE. #define TLI_ASZ_VASZ BITS(0,11) /*!< size of the vertical active area width plus back porch and synchronous pulse */ #define TLI_ASZ_HASZ BITS(16,27) /*!< size of the horizontal active area width plus back porch and synchronous pulse */ -/* TLI_SPSZ */ +/* TLI_TSZ */ #define TLI_TSZ_VTSZ BITS(0,11) /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */ #define TLI_TSZ_HTSZ BITS(16,27) /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */ @@ -138,7 +136,7 @@ OF SUCH DAMAGE. #define TLI_STAT_VDE BIT(0) /*!< current VDE status */ #define TLI_STAT_HDE BIT(1) /*!< current HDE status */ #define TLI_STAT_VS BIT(2) /*!< current VS status of the TLI */ -#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */ +#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */ /* TLI_LxCTL */ #define TLI_LxCTL_LEN BIT(0) /*!< layer enable */ @@ -192,8 +190,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* TLI parameter struct definitions */ -typedef struct -{ +typedef struct { uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ @@ -209,11 +206,10 @@ typedef struct uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ uint32_t signalpolarity_de; /*!< data enable polarity selection */ uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ -}tli_parameter_struct; +} tli_parameter_struct; /* TLI layer parameter struct definitions */ -typedef struct -{ +typedef struct { uint16_t layer_window_rightpos; /*!< window right position */ uint16_t layer_window_leftpos; /*!< window left position */ uint16_t layer_window_bottompos; /*!< window bottom position */ @@ -230,29 +226,27 @@ typedef struct uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ uint16_t layer_frame_line_length; /*!< frame line length */ uint16_t layer_frame_total_line_number; /*!< frame total line number */ -}tli_layer_parameter_struct; +} tli_layer_parameter_struct; /* TLI layer LUT parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t layer_table_addr; /*!< look up table write address */ uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ -}tli_layer_lut_parameter_struct; +} tli_layer_lut_parameter_struct; /* packeted pixel format */ -typedef enum -{ - LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ - LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ - LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ - LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ - LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ - LAYER_PPF_L8, /*!< layerx pixel format L8 */ - LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ - LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ -}tli_layer_ppf_enum; +typedef enum { + LAYER_PPF_ARGB8888 = 0U, /*!< layerx pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ +} tli_layer_ppf_enum; /* TLI flags */ #define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ @@ -287,10 +281,12 @@ typedef enum /* horizontal pulse polarity selection */ #define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ #define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ +#define TLI_HSYN_ACTLIVE_HIGH TLI_HSYN_ACTLIVE_HIGHT /*!< horizontal synchronous pulse active high */ /* vertical pulse polarity selection */ #define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ #define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ +#define TLI_VSYN_ACTLIVE_HIGH TLI_VSYN_ACTLIVE_HIGHT /*!< vertical synchronous pulse active high */ /* pixel clock polarity selection */ #define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ @@ -299,6 +295,7 @@ typedef enum /* data enable polarity selection */ #define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ #define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ +#define TLI_DE_ACTLIVE_HIGH TLI_DE_ACTLIVE_HIGHT /*!< data enable active high */ /* alpha calculation factor 1 of blending method */ #define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) @@ -314,7 +311,7 @@ typedef enum /* initialization functions, TLI enable or disable, TLI reload mode configuration */ /* deinitialize TLI registers */ void tli_deinit(void); -/* initialize the parameters of TLI parameter structure with the default values, it is suggested +/* initialize the parameters of TLI parameter structure with the default values, it is suggested that call this function after a tli_parameter_struct structure is defined */ void tli_struct_para_init(tli_parameter_struct *tli_struct); /* initialize TLI */ @@ -329,20 +326,20 @@ void tli_disable(void); void tli_reload_config(uint8_t reload_mod); /* TLI layer configuration functions */ -/* initialize the parameters of TLI layer structure with the default values, it is suggested +/* initialize the parameters of TLI layer structure with the default values, it is suggested that call this function after a tli_layer_parameter_struct structure is defined */ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); /* initialize TLI layer */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct); /* reconfigure window position */ -void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y); -/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y); +/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested that call this function after a tli_layer_lut_parameter_struct structure is defined */ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); /* initialize TLI layer LUT */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct); /* initialize TLI layer color key */ -void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey); +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey); /* enable TLI layer */ void tli_layer_enable(uint32_t layerx); /* disable TLI layer */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h index 5bdcb2f..ff78ab5 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h @@ -2,13 +2,11 @@ \file gd32f4xx_trng.h \brief definitions for the TRNG - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -43,14 +41,14 @@ OF SUCH DAMAGE. #define TRNG TRNG_BASE /* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ +#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */ /* bits definitions */ /* TRNG_CTL */ #define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ -#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */ +#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */ /* TRNG_STAT */ #define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ @@ -60,45 +58,43 @@ OF SUCH DAMAGE. #define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ /* TRNG_DATA */ -#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */ +#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */ /* constants definitions */ -/* trng status flag */ -typedef enum -{ +/* TRNG status flag */ +typedef enum { TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ -}trng_flag_enum; +} trng_flag_enum; -/* trng inerrupt flag */ -typedef enum -{ +/* TRNG inerrupt flag */ +typedef enum { TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */ -}trng_int_flag_enum; +} trng_int_flag_enum; /* function declarations */ /* initialization functions */ -/* deinitialize the TRNG */ +/* reset TRNG */ void trng_deinit(void); -/* enable the TRNG interface */ +/* enable TRNG */ void trng_enable(void); -/* disable the TRNG interface */ +/* disable TRNG */ void trng_disable(void); /* get the true random data */ uint32_t trng_get_true_random_data(void); -/* flag & interrupt functions */ -/* trng interrupt enable */ +/* interrupt & flag functions */ +/* enable TRNG interrupt */ void trng_interrupt_enable(void); -/* trng interrupt disable */ +/* disable TRNG interrupt */ void trng_interrupt_disable(void); -/* get the trng status flags */ +/* get TRNG flag status */ FlagStatus trng_flag_get(trng_flag_enum flag); -/* get the trng interrupt flags */ +/* get TRNG interrupt flag status */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); -/* clear the trng interrupt flags */ +/* clear TRNG interrupt flag status */ void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); #endif /* GD32F4XX_TRNG_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h index d8bf598..fb3152b 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h @@ -1,36 +1,34 @@ /*! \file gd32f4xx_usart.h \brief definitions for the USART - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -64,94 +62,94 @@ OF SUCH DAMAGE. /* bits definitions */ /* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ /* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ /* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ /* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< enable receiver */ +#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */ +#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */ +#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */ +#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */ +#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */ +#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< enable USART */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ /* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< enable CK pin */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */ /* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ +#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */ +#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */ +#define USART_CTL2_DENR BIT(6) /*!< enable DMA request for reception */ +#define USART_CTL2_DENT BIT(7) /*!< enable DMA request for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */ +#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */ +#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ /* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + /* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ +#define USART_CTL3_RTEN BIT(0) /*!< enable receiver timeout */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ /* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ /* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ /* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ -#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ +#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ /* constants definitions */ /* define the USART bit position and its register index offset */ @@ -164,17 +162,16 @@ OF SUCH DAMAGE. #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) /* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ -#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ /* USART flags */ -typedef enum -{ +typedef enum { /* flags in STAT0 register */ USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ @@ -192,11 +189,10 @@ typedef enum USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ /* flags in CHC register */ USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ -}usart_flag_enum; +} usart_flag_enum; /* USART interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in CTL0 register */ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ @@ -214,11 +210,10 @@ typedef enum /* interrupt flags in CTL3 register */ USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ -}usart_interrupt_flag_enum; +} usart_interrupt_flag_enum; /* USART interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt in CTL0 register */ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ @@ -233,11 +228,10 @@ typedef enum /* interrupt in CTL3 register */ USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ -}usart_interrupt_enum; +} usart_interrupt_enum; -/* USART invert configure */ -typedef enum -{ +/* configure USART invert */ +typedef enum { /* data bit level inversion */ USART_DINV_ENABLE, /*!< data bit level inversion */ USART_DINV_DISABLE, /*!< data bit level not inversion */ @@ -247,14 +241,14 @@ typedef enum /* RX pin level inversion */ USART_RXPIN_ENABLE, /*!< RX pin level inversion */ USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ -}usart_invert_enum; +} usart_invert_enum; -/* USART receiver configure */ +/* configure USART receiver */ #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ -/* USART transmitter configure */ +/* configure USART transmitter */ #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ @@ -307,32 +301,32 @@ typedef enum #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ -/* USART DMA request for receive configure */ +/* configure USART DMA request for receive */ #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ +#define USART_RECEIVE_DMA_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_RECEIVE_DMA_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ -/* USART DMA request for transmission configure */ +/* configure USART DMA request for transmission */ #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ +#define USART_TRANSMIT_DMA_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_TRANSMIT_DMA_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ -/* USART RTS configure */ +/* configure USART RTS */ #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */ -/* USART CTS configure */ +/* configure USART CTS */ #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */ -/* USART one sample bit method configure */ +/* configure USART one sample bit method */ #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) #define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ #define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ -/* USART IrDA low-power enable */ +/* enable USART IrDA low-power */ #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ @@ -394,7 +388,7 @@ void usart_receiver_timeout_disable(uint32_t usart_periph); /* configure receiver timeout threshold */ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); /* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); +void usart_data_transmit(uint32_t usart_periph, uint16_t data); /* USART receive data function */ uint16_t usart_data_receive(uint32_t usart_periph); @@ -434,7 +428,7 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32 /* smartcard communication */ /* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat); /* enable smartcard mode */ void usart_smartcard_mode_enable(uint32_t usart_periph); /* disable smartcard mode */ @@ -444,9 +438,9 @@ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); /* disable NACK in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); /* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum); /* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); +void usart_block_length_config(uint32_t usart_periph, uint8_t bl); /* IrDA communication */ /* enable IrDA mode */ @@ -492,4 +486,4 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_ /* clear interrupt flag in STAT0/STAT1 register */ void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -#endif /* GD32F4XX_USART_H */ +#endif /* GD32F4XX_USART_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h index fa9a5aa..47ca81a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h @@ -1,14 +1,12 @@ /*! \file gd32f4xx_wwdgt.h \brief definitions for the WWDGT - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* WWDGT definitions */ -#define WWDGT WWDGT_BASE +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ /* registers definitions */ #define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ @@ -67,6 +65,11 @@ OF SUCH DAMAGE. #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ #define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* reset the window watchdog timer configuration */ void wwdgt_deinit(void); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c index abc2a50..19267e5 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c @@ -1,64 +1,62 @@ /*! \file gd32f4xx_adc.c \brief ADC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_adc.h" -#define REGULAR_TRIGGER_MODE ((uint32_t)28U) -#define INSERTED_TRIGGER_MODE ((uint32_t)20U) +#define ROUTINE_TRIGGER_MODE ((uint32_t)28U) +#define INSERTED_TRIGGER_MODE ((uint32_t)20U) /* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) +/* ADC routine channel macro */ +#define ADC_ROUTINE_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_ROUTINE_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_ROUTINE_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_ROUTINE_CHANNEL_RANK_LENGTH ((uint8_t)5U) /* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) /* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) /* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! \brief reset ADC @@ -73,9 +71,9 @@ void adc_deinit(void) } /*! - \brief configure the ADC clock for all the ADCs - \param[in] prescaler: configure ADCs prescaler ratio - only one parameter can be selected which is shown as below: + \brief configure the ADC clock for all the ADCs + \param[in] prescaler: configure ADCs prescaler ratio + only one parameter can be selected which is shown as below: \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 @@ -84,8 +82,8 @@ void adc_deinit(void) \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 - \param[out] none - \retval none + \param[out] none + \retval none */ void adc_clock_config(uint32_t prescaler) { @@ -94,88 +92,88 @@ void adc_clock_config(uint32_t prescaler) } /*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none */ -void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) { - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ + if(newvalue) { + if(0U != (function & ADC_SCAN_MODE)) { /* enable scan mode */ ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* enable inserted channel group convert automatically */ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* enable inserted sequence convert automatically */ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ + } + if(0U != (function & ADC_CONTINUOUS_MODE)) { /* enable continuous mode */ ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ + } + } else { + if(0U != (function & ADC_SCAN_MODE)) { /* disable scan mode */ ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* disable inserted channel group convert automatically */ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* disable inserted sequence convert automatically */ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ + } + if(0U != (function & ADC_CONTINUOUS_MODE)) { /* disable continuous mode */ ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } + } } } /*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none */ -void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) { - if(ADC_DATAALIGN_RIGHT != data_alignment){ + if(ADC_DATAALIGN_RIGHT != data_alignment) { /* MSB alignment */ ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ + } else { /* LSB alignment */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); } } /*! - \brief enable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_enable(uint32_t adc_periph) { - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { /* enable ADC */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } + } } /*! - \brief disable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_disable(uint32_t adc_periph) { @@ -184,112 +182,112 @@ void adc_disable(uint32_t adc_periph) } /*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_calibration_enable(uint32_t adc_periph) { /* reset the selected ADC calibration registers */ ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { } /* enable ADC calibration process */ ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { } } /*! - \brief configure temperature sensor and internal reference voltage channel or VBAT channel function - \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel - only one parameter can be selected which is shown as below: - \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 - \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 - \param[in] newvalue: ENABLE or DISABLE -\param[out] none - \retval none + \brief configure temperature sensor and internal reference voltage channel or VBAT channel function + \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + only one parameter can be selected which is shown as below: + \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 + \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none */ void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) { - if(newvalue){ - if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + if(newvalue) { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { /* enable ADC0 Vbat channel */ ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; } - if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { /* enable ADC0 Vref and Temperature channel */ ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; - } - }else{ - if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + } + } else { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { /* disable ADC0 Vbat channel */ ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; } - if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { /* disable ADC0 Vref and Temperature channel */ ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; - } + } } } /*! - \brief configure ADC resolution - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none */ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); ADC_CTL0(adc_periph) |= (uint32_t)resolution; } /*! - \brief configure ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none */ -void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio) +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio) { - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ + } else { ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); } /* config the shift and ratio */ @@ -298,10 +296,10 @@ void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t s } /*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_oversample_mode_enable(uint32_t adc_periph) { @@ -309,10 +307,10 @@ void adc_oversample_mode_enable(uint32_t adc_periph) } /*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_oversample_mode_disable(uint32_t adc_periph) { @@ -320,10 +318,10 @@ void adc_oversample_mode_disable(uint32_t adc_periph) } /*! - \brief enable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_dma_mode_enable(uint32_t adc_periph) { @@ -332,7 +330,7 @@ void adc_dma_mode_enable(uint32_t adc_periph) } /*! - \brief disable DMA request + \brief disable DMA request \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none @@ -344,7 +342,7 @@ void adc_dma_mode_disable(uint32_t adc_periph) } /*! - \brief when DMA=1, the DMA engine issues a request at end of each regular conversion + \brief when DMA=1, the DMA engine issues a request at end of each routine conversion \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none @@ -366,69 +364,69 @@ void adc_dma_request_after_last_disable(uint32_t adc_periph) } /*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel - \param[out] none - \retval none + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for routine sequence ,the number has no effect for inserted sequence + \param[out] none + \retval none */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length) +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length) { - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: + /* disable discontinuous mode of routine & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: /* config the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - if((length <= 8U) && (length >= 1U)){ + if((length <= 8U) && (length >= 1U)) { ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } - /* enable regular channel group discontinuous mode */ + /* enable routine sequence discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; break; case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ + /* enable inserted sequence discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; break; case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ + /* disable discontinuous mode of routine & inserted channel */ default: break; } } /*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none + \brief configure the length of routine sequence or inserted sequence + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] length: the length of the channel + routine channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length) +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - if((length >= 1U) && (length <= 16U)){ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + if((length >= 1U) && (length <= 16U)) { + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } break; case ADC_INSERTED_CHANNEL: - if((length >= 1U) && (length <= 4U)){ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + if((length >= 1U) && (length <= 4U)) { + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } break; default: @@ -437,149 +435,149 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , } /*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles - \param[out] none - \retval none + \brief configure ADC routine channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the routine sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ - /* the regular group sequence rank is smaller than six */ + uint32_t rsq, sampt; + + /* ADC routine sequence config */ + if(rank < ADC_ROUTINE_CHANNEL_RANK_SIX) { + /* the routine sequence rank is smaller than six */ rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank)); ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ - /* the regular group sequence rank is smaller than twelve */ + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_TWELVE) { + /* the routine sequence rank is smaller than twelve */ rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX))); ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ - /* the regular group sequence rank is smaller than sixteen */ + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_SIXTEEN) { + /* the routine sequence rank is smaller than sixteen */ rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE))); ADC_RSQ0(adc_periph) = rsq; - }else{ + } else { } - + /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the regular group sequence rank is smaller than ten */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the routine sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the regular group sequence rank is smaller than eighteen */ + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the routine sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; - }else{ + } else { } } /*! \brief configure ADC inserted channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] rank: the inserted sequence rank,this parameter must be between 0 to 3 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx \param[in] sample_time: The sample time value only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles \param[out] none \retval none */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint8_t inserted_length; - uint32_t isq,sampt; + uint32_t isq, sampt; - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - if(rank < 4U){ + /* get inserted sequence length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted sequence */ + if(rank < 4U) { isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); ADC_ISQ(adc_periph) = isq; } /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the inserted group sequence rank is smaller than ten */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the inserted sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the inserted group sequence rank is smaller than eighteen */ + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the inserted sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; - }else{ + } else { } } /*! - \brief configure ADC inserted channel offset + \brief configure ADC inserted channel offset \param[in] adc_periph: ADCx,x=0,1,2 \param[in] inserted_channel : insert channel select only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 \param[in] offset : the offset data \param[out] none \retval none */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) { uint8_t inserted_length; uint32_t num = 0U; - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if(num <= ADC_OFFSET_LENGTH){ + + if(num <= ADC_OFFSET_LENGTH) { /* calculate the offset of the register */ num = num * ADC_OFFSET_SHIFT_LENGTH; /* config the offset of the selected channels */ @@ -588,62 +586,62 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_c } /*! - \brief configure ADC external trigger source + \brief configure ADC external trigger source \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - for regular channel: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] external_trigger_source: routine or inserted sequence trigger source + for routine sequence: only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel - for inserted channel: + \arg ADC_EXTTRIG_ROUTINE_T0_CH0: external trigger timer 0 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH1: external trigger timer 0 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH2: external trigger timer 0 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH1: external trigger timer 1 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH2: external trigger timer 1 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH3: external trigger timer 1 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_TRGO: external trigger timer 1 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_CH0 : external trigger timer 2 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_TRGO : external trigger timer 2 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T3_CH3: external trigger timer 3 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH0: external trigger timer 4 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH1: external trigger timer 4 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH2: external trigger timer 4 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_CH0: external trigger timer 7 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_TRGO: external trigger timer 7 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_EXTI_11: external trigger extiline 11 select for routine sequence + for inserted sequence: only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event - \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event - \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event + \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event + \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 \param[out] none \retval none */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ + /* configure ADC inserted sequence external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; @@ -653,58 +651,58 @@ void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channe } /*! - \brief enable ADC external trigger + \brief enable ADC external trigger \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[in] trigger_mode: external trigger mode only one parameter can be selected which is shown as below: - \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable - \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger - \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger - \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger + \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable + \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger + \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger + \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger \param[out] none \retval none */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode) +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular channel group external trigger mode */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); - ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << REGULAR_TRIGGER_MODE); - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted channel group external trigger mode */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); - ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << INSERTED_TRIGGER_MODE); - break; - default: - break; - } + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << ROUTINE_TRIGGER_MODE); + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE); + break; + default: + break; + } } /*! - \brief enable ADC software trigger + \brief enable ADC software trigger \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[out] none \retval none */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* enable ADC regular channel group software trigger */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* enable ADC routine sequence software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; break; case ADC_INSERTED_CHANNEL: - /* enable ADC inserted channel group software trigger */ + /* enable ADC inserted sequence software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; break; default: @@ -713,60 +711,60 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group } /*! - \brief configure end of conversion mode + \brief configure end of conversion mode \param[in] adc_periph: ADCx,x=0,1,2 \param[in] end_selection: end of conversion mode only one parameter can be selected which is shown as below: - \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. - \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically. + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of routine conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically. \param[out] none \retval none */ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) +void adc_end_of_conversion_config(uint32_t adc_periph, uint8_t end_selection) { - switch(end_selection){ - case ADC_EOC_SET_SEQUENCE: - /* only at the end of a sequence of regular conversions, the EOC bit is set */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); - break; - case ADC_EOC_SET_CONVERSION: - /* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); - break; - default: - break; + switch(end_selection) { + case ADC_EOC_SET_SEQUENCE: + /* only at the end of a sequence of routine conversions, the EOC bit is set */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); + break; + case ADC_EOC_SET_CONVERSION: + /* at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); + break; + default: + break; } } /*! - \brief read ADC regular group data register + \brief read ADC routine data register \param[in] adc_periph: ADCx,x=0,1,2 \param[in] none \param[out] none \retval the conversion value */ -uint16_t adc_regular_data_read(uint32_t adc_periph) +uint16_t adc_routine_data_read(uint32_t adc_periph) { return (uint16_t)(ADC_RDATA(adc_periph)); } /*! - \brief read ADC inserted group data register + \brief read ADC inserted data register \param[in] adc_periph: ADCx,x=0,1,2 \param[in] inserted_channel : insert channel select only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 \param[out] none \retval the conversion value */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) { uint32_t idata; /* read the data of the selected channel */ - switch(inserted_channel){ + switch(inserted_channel) { case ADC_INSERTED_CHANNEL_0: /* read the data of channel 0 */ idata = ADC_IDATA0(adc_periph); @@ -791,26 +789,26 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) } /*! - \brief disable ADC analog watchdog single channel + \brief disable ADC analog watchdog single channel \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none */ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ) +void adc_watchdog_single_channel_disable(uint32_t adc_periph) { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); } /*! - \brief enable ADC analog watchdog single channel + \brief enable ADC analog watchdog single channel \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) + \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) \param[out] none \retval none */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel) +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); @@ -820,31 +818,31 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channe } /*! - \brief configure ADC analog watchdog group channel + \brief configure ADC analog watchdog sequence channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence) { ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* routine channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; break; case ADC_INSERTED_CHANNEL: /* inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ + case ADC_ROUTINE_INSERTED_CHANNEL: + /* routine and inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); break; default: @@ -853,30 +851,30 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel } /*! - \brief disable ADC analog watchdog + \brief disable ADC analog watchdog \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_sequence) { - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* disable ADC analog watchdog regular channel group */ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* disable ADC analog watchdog routine sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); break; case ADC_INSERTED_CHANNEL: - /* disable ADC analog watchdog inserted channel group */ + /* disable ADC analog watchdog inserted sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* disable ADC analog watchdog regular and inserted channel group */ + case ADC_ROUTINE_INSERTED_CHANNEL: + /* disable ADC analog watchdog routine and inserted sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); break; default: @@ -885,14 +883,14 @@ void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) } /*! - \brief configure ADC analog watchdog threshold + \brief configure ADC analog watchdog threshold \param[in] adc_periph: ADCx,x=0,1,2 \param[in] low_threshold: analog watchdog low threshold,0..4095 \param[in] high_threshold: analog watchdog high threshold,0..4095 \param[out] none \retval none */ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) { /* configure ADC analog watchdog low threshold */ ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); @@ -901,23 +899,23 @@ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold } /*! - \brief get the ADC flag bits + \brief get the ADC flag bits \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) { FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ + if(ADC_STAT(adc_periph) & adc_flag) { reval = SET; } return reval; @@ -925,42 +923,42 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) } /*! - \brief clear the ADC flag bits + \brief clear the ADC flag bits \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag \param[out] none \retval none */ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); } /*! - \brief get the bit state of ADCx software start conversion + \brief get the bit state of ADCx software start conversion \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)){ + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) { reval = SET; } return reval; } /*! - \brief get the bit state of ADCx software inserted channel start conversion + \brief get the bit state of ADCx software inserted channel start conversion \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] none \param[out] none @@ -969,56 +967,56 @@ FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)){ + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)) { reval = SET; } return reval; } /*! - \brief get the ADC interrupt bits + \brief get the ADC interrupt bits \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc interrupt bits only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) { FlagStatus interrupt_flag = RESET; uint32_t state; /* check the interrupt bits */ - switch(adc_interrupt){ + switch(adc_interrupt) { case ADC_INT_FLAG_WDE: /* get the ADC analog watchdog interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; } break; case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ + /* get the ADC end of sequence conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { interrupt_flag = SET; - } + } break; case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ + /* get the ADC end of inserted sequence conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { interrupt_flag = SET; } break; case ADC_INT_FLAG_ROVF: - /* get the ADC regular data register overflow interrupt bits */ + /* get the ADC routine data register overflow interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; - if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state){ - interrupt_flag = SET; + if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) { + interrupt_flag = SET; } break; default: @@ -1028,47 +1026,47 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) } /*! - \brief clear the ADC flag + \brief clear the ADC flag \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc status flag only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt \param[out] none \retval none */ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); } /*! - \brief enable ADC interrupt + \brief enable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc interrupt flag only one parameter can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag \param[out] none \retval none */ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) { - switch(adc_interrupt){ + switch(adc_interrupt) { case ADC_INT_WDE: /* enable analog watchdog interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; break; case ADC_INT_EOC: - /* enable end of group conversion interrupt */ + /* enable end of sequence conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; break; case ADC_INT_EOIC: - /* enable end of inserted group conversion interrupt */ + /* enable end of inserted sequence conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; break; case ADC_INT_ROVF: @@ -1080,20 +1078,20 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) } /*! - \brief disable ADC interrupt + \brief disable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc interrupt flag only one parameter can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag \param[out] none \retval none */ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) { - switch(adc_interrupt){ + switch(adc_interrupt) { /* select the interrupt source */ case ADC_INT_WDE: ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); @@ -1113,22 +1111,22 @@ void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) } /*! - \brief configure the ADC sync mode - \param[in] sync_mode: ADC sync mode + \brief configure the ADC sync mode + \param[in] sync_mode: ADC sync mode only one parameter can be selected which is shown as below: - \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode - \arg ADC_DAUL_REGULAL_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode - \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined regular parallel & inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION: all ADCs work in combined regular parallel & trigger rotation mode - \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL: all ADCs work in regular parallel mode - \arg ADC_ALL_REGULAL_FOLLOW_UP: all ADCs work in follow-up mode - \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode + \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel & inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel & trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode + \arg ADC_DAUL_ROUTINE_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined routine parallel & inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION: all ADCs work in combined routine parallel & trigger rotation mode + \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL: all ADCs work in routine parallel mode + \arg ADC_ALL_ROUTINE_FOLLOW_UP: all ADCs work in follow-up mode + \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode \param[out] none \retval none */ @@ -1139,10 +1137,10 @@ void adc_sync_mode_config(uint32_t sync_mode) } /*! - \brief configure the delay between 2 sampling phases in ADC sync modes - \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + \brief configure the delay between 2 sampling phases in ADC sync modes + \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes only one parameter can be selected which is shown as below: - \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles + \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles \param[out] none \retval none */ @@ -1153,23 +1151,23 @@ void adc_sync_delay_config(uint32_t sample_delay) } /*! - \brief configure ADC sync DMA mode selection + \brief configure ADC sync DMA mode selection \param[in] dma_mode: ADC sync DMA mode only one parameter can be selected which is shown as below: - \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 - \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 + \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled + \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 + \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 \param[out] none \retval none */ -void adc_sync_dma_config(uint32_t dma_mode ) +void adc_sync_dma_config(uint32_t dma_mode) { ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDMA); ADC_SYNCCTL |= dma_mode; } /*! - \brief configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected + \brief configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected \param[in] none \param[out] none \retval none @@ -1180,7 +1178,7 @@ void adc_sync_dma_request_after_last_enable(void) } /*! - \brief configure ADC sync DMA engine issues requests according to the SYNCDMA bits + \brief configure ADC sync DMA engine issues requests according to the SYNCDMA bits \param[in] none \param[out] none \retval none @@ -1191,12 +1189,12 @@ void adc_sync_dma_request_after_last_disable(void) } /*! - \brief read ADC sync regular data register + \brief read ADC sync routine data register \param[in] none \param[out] none - \retval sync regular data + \retval sync routine data */ -uint32_t adc_sync_regular_data_read(void) +uint32_t adc_sync_routine_data_read(void) { return (uint32_t)ADC_SYNCDATA; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c index 92cab85..fbc8675 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c @@ -1,47 +1,44 @@ /*! \file gd32f4xx_can.c \brief CAN driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-11-27, V2.0.1, firmware for GD32F4xx - \version 2020-07-14, V2.0.2, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_can.h" +#include #define CAN_ERROR_HANDLE(s) do{}while(1) /*! - \brief deinitialize CAN + \brief deinitialize CAN \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -59,86 +56,89 @@ void can_deinit(uint32_t can_periph) } /*! - \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct only one parameter can be selected which is shown as below: \arg CAN_INIT_STRUCT: the CAN initial struct \arg CAN_FILTER_STRUCT: the CAN filter struct \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none + \param[out] p_struct: the pointer of the specific struct \retval none */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct) +void can_struct_para_init(can_struct_type_enum type, void *p_struct) { uint8_t i; - + + if(NULL == p_struct) { + CAN_ERROR_HANDLE("struct parameter can not be NULL \r\n"); + } + /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); + switch(type) { + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct *)p_struct)->auto_retrans = DISABLE; + ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct *)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct *)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_receive_message_struct *)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct *)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct *)p_struct)->rx_efid = 0U; + ((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct *)p_struct)->rx_fi = 0U; + ((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct *)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); } } /*! - \brief initialize CAN + \brief initialize CAN \param[in] can_periph \arg CANx(x=0,1) \param[in] can_parameter_init: parameters for CAN initializtion @@ -149,30 +149,30 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct) \arg time_triggered: ENABLE or DISABLE \arg auto_bus_off_recovery: ENABLE or DISABLE \arg auto_wake_up: ENABLE or DISABLE - \arg no_auto_retrans: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE \arg rec_fifo_overwrite: ENABLE or DISABLE \arg trans_fifo_order: ENABLE or DISABLE \arg prescaler: 0x0001 - 0x0400 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) { uint32_t timeout = CAN_TIMEOUT; ErrStatus flag = ERROR; - + /* disable sleep mode */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; /* enable initialize mode */ CAN_CTL(can_periph) |= CAN_CTL_IWMOD; /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { flag = ERROR; - }else{ + } else { /* set the bit timing register */ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ @@ -181,138 +181,138 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ + if(ENABLE == can_parameter_init->time_triggered) { CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_TTC; } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + /* automatic bus-off management */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery) { CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; } /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ + if(ENABLE == can_parameter_init->auto_wake_up) { CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_AWU; } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->no_auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ + /* automatic retransmission mode */ + if(ENABLE == can_parameter_init->auto_retrans) { CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_ARD; } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ + /* receive FIFO overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite) { CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ + } else { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + } + /* transmit FIFO order */ + if(ENABLE == can_parameter_init->trans_fifo_order) { CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } + } /* disable initialize mode */ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; timeout = CAN_TIMEOUT; /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } /* check exit initialize mode */ - if(0U != timeout){ + if(0U != timeout) { flag = SUCCESS; } - } + } return flag; } /*! - \brief initialize CAN filter + \brief initialize CAN filter \param[in] can_filter_parameter_init: struct for CAN filter initialization \arg filter_list_high: 0x0000 - 0xFFFF \arg filter_list_low: 0x0000 - 0xFFFF \arg filter_mask_high: 0x0000 - 0xFFFF \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 \arg filter_number: 0 - 27 \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT \arg filter_enable: ENABLE or DISABLE \param[out] none \retval none */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) { uint32_t val = 0U; - + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); /* filter lock disable */ CAN_FCTL(CAN0) |= CAN_FCTL_FLD; /* disable filter */ CAN_FW(CAN0) &= ~(uint32_t)val; - + /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { /* set filter 16 bits */ CAN_FSCFG(CAN0) &= ~(uint32_t)val; /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); } /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { /* set filter 32 bits */ CAN_FSCFG(CAN0) |= (uint32_t)val; /* 32 bits list or first 32 bits list */ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); /* 32 bits mask or second 32 bits list */ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); } - + /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { /* mask mode */ CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ + } else { /* list mode */ CAN_FMCFG(CAN0) |= (uint32_t)val; } - + /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { /* FIFO0 */ CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - }else{ + } else { /* FIFO1 */ CAN_FAFIFO(CAN0) |= (uint32_t)val; } - + /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - + if(ENABLE == can_filter_parameter_init->filter_enable) { + CAN_FW(CAN0) |= (uint32_t)val; } - + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } /*! - \brief set CAN1 fliter start bank number + \brief set CAN1 filter start bank number \param[in] start_bank: CAN1 start bank number only one parameter can be selected which is shown as below: \arg (1..27) @@ -326,12 +326,12 @@ void can1_filter_start_bank(uint8_t start_bank) /* set CAN1 filter start number */ CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } /*! - \brief enable CAN debug freeze + \brief enable CAN debug freeze \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -341,7 +341,8 @@ void can_debug_freeze_enable(uint32_t can_periph) { /* set DFZ bit */ CAN_CTL(can_periph) |= CAN_CTL_DFZ; - if(CAN0 == can_periph){ + + if(CAN0 == can_periph) { dbg_periph_enable(DBG_CAN0_HOLD); }else{ dbg_periph_enable(DBG_CAN1_HOLD); @@ -349,7 +350,7 @@ void can_debug_freeze_enable(uint32_t can_periph) } /*! - \brief disable CAN debug freeze + \brief disable CAN debug freeze \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -359,6 +360,7 @@ void can_debug_freeze_disable(uint32_t can_periph) { /* set DFZ bit */ CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; + if(CAN0 == can_periph){ dbg_periph_disable(DBG_CAN0_HOLD); }else{ @@ -367,7 +369,7 @@ void can_debug_freeze_disable(uint32_t can_periph) } /*! - \brief enable CAN time trigger mode + \brief enable CAN time trigger mode \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -376,17 +378,17 @@ void can_debug_freeze_disable(uint32_t can_periph) void can_time_trigger_mode_enable(uint32_t can_periph) { uint8_t mailbox_number; - - /* enable the tcc mode */ + + /* enable the TTC mode */ CAN_CTL(can_periph) |= CAN_CTL_TTC; /* enable time stamp */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; } } /*! - \brief disable CAN time trigger mode + \brief disable CAN time trigger mode \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -394,18 +396,18 @@ void can_time_trigger_mode_enable(uint32_t can_periph) */ void can_time_trigger_mode_disable(uint32_t can_periph) { - uint8_t mailbox_number; - - /* disable the TCC mode */ + uint8_t mailbox_number; + + /* disable the TTC mode */ CAN_CTL(can_periph) &= ~CAN_CTL_TTC; /* reset TSEN bits */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; } } /*! - \brief transmit CAN message + \brief transmit CAN message \param[in] can_periph \arg CANx(x=0,1) \param[in] transmit_message: struct for CAN transmit message @@ -418,48 +420,48 @@ void can_time_trigger_mode_disable(uint32_t can_periph) \param[out] none \retval mailbox_number */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) { uint8_t mailbox_number = CAN_MAILBOX0; /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + } else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + } else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { mailbox_number = CAN_MAILBOX2; - }else{ + } else { mailbox_number = CAN_NOMAILBOX; } /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ + if(CAN_NOMAILBOX == mailbox_number) { return CAN_NOMAILBOX; } - + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ + if(CAN_FF_STANDARD == transmit_message->tx_ff) { /* set transmit mailbox standard identifier */ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ + transmit_message->tx_ft); + } else { /* set transmit mailbox extended identifier */ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); + transmit_message->tx_ff | \ + transmit_message->tx_ft); } /* set the data length */ CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; /* set the data */ CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); /* enable transmission */ CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; @@ -467,7 +469,7 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t } /*! - \brief get CAN transmit state + \brief get CAN transmit state \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number @@ -480,9 +482,9 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox { can_transmit_state_enum state = CAN_TRANSMIT_FAILED; uint32_t val = 0U; - - /* check selected mailbox state */ - switch(mailbox_number){ + + /* check selected mailbox state */ + switch(mailbox_number) { /* mailbox0 */ case CAN_MAILBOX0: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); @@ -499,26 +501,26 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox val = CAN_TRANSMIT_FAILED; break; } - - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): + + switch(val) { + /* transmit pending */ + case(CAN_STATE_PENDING): state = CAN_TRANSMIT_PENDING; break; - /* mailbox0 transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + /* mailbox0 transmit succeeded */ + case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_OK; break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + /* mailbox1 transmit succeeded */ + case(CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_OK; break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + /* mailbox2 transmit succeeded */ + case(CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_OK; break; - /* transmit failed */ - default: + /* transmit failed */ + default: state = CAN_TRANSMIT_FAILED; break; } @@ -526,7 +528,7 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox } /*! - \brief stop CAN transmission + \brief stop CAN transmission \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number @@ -537,25 +539,25 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox */ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) { - if(CAN_MAILBOX0 == mailbox_number){ + if(CAN_MAILBOX0 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { } - }else if(CAN_MAILBOX1 == mailbox_number){ + } else if(CAN_MAILBOX1 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { } - }else if(CAN_MAILBOX2 == mailbox_number){ + } else if(CAN_MAILBOX2 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { } - }else{ + } else { /* illegal parameters */ } } /*! - \brief CAN receive message + \brief CAN receive message \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number @@ -570,25 +572,25 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) \arg rx_fi: 0 - 27 \retval none */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) { /* get the frame format */ receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ + if(CAN_FF_STANDARD == receive_message->rx_ff) { /* get standard identifier */ receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ + } else { /* get extended identifier */ receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); } - + /* get frame type */ - receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); /* filtering index */ receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - /* get recevie data length */ + /* get receive data length */ receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - + /* receive data */ receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); @@ -598,17 +600,17 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - + /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ + } else { CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; } } /*! - \brief release FIFO0 + \brief release FIFO \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number @@ -619,44 +621,44 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) { - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ + } else if(CAN_FIFO1 == fifo_number) { CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ + } else { /* illegal parameters */ CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); } } /*! - \brief CAN receive message length + \brief CAN receive message length \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) + \arg CAN_FIFOx(x=0,1) \param[out] none \retval message length */ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) { uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ + + if(CAN_FIFO0 == fifo_number) { /* FIFO0 */ val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ + } else if(CAN_FIFO1 == fifo_number) { /* FIFO1 */ val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ + } else { /* illegal parameters */ } return val; } /*! - \brief set CAN working mode + \brief set CAN working mode \param[in] can_periph \arg CANx(x=0,1) \param[in] can_working_mode @@ -671,56 +673,56 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) { ErrStatus flag = ERROR; /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode) { /* disable sleep mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); /* set initialize mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else if(CAN_MODE_NORMAL == working_mode){ + } else if(CAN_MODE_NORMAL == working_mode) { /* enter normal mode */ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { timeout--; } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else if(CAN_MODE_SLEEP == working_mode){ + } else if(CAN_MODE_SLEEP == working_mode) { /* disable initialize mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); /* set sleep mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { timeout--; } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else{ + } else { flag = ERROR; } return flag; } /*! - \brief wake up CAN + \brief wake up CAN \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -730,24 +732,24 @@ ErrStatus can_wakeup(uint32_t can_periph) { ErrStatus flag = ERROR; uint32_t timeout = CAN_TIMEOUT; - + /* wakeup */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { timeout--; } /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } return flag; } /*! - \brief get CAN error type + \brief get CAN error type \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -765,14 +767,14 @@ can_error_enum can_error_get(uint32_t can_periph) { can_error_enum error; error = CAN_ERROR_NONE; - + /* get error type */ error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); return error; } /*! - \brief get CAN receive error number + \brief get CAN receive error number \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -781,14 +783,14 @@ can_error_enum can_error_get(uint32_t can_periph) uint8_t can_receive_error_number_get(uint32_t can_periph) { uint8_t val; - + /* get error count */ val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); return val; } /*! - \brief get CAN transmit error number + \brief get CAN transmit error number \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -797,69 +799,13 @@ uint8_t can_receive_error_number_get(uint32_t can_periph) uint8_t can_transmit_error_number_get(uint32_t can_periph) { uint8_t val; - + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); return val; } /*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state + \brief get CAN flag state \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN flags, refer to can_flag_enum @@ -873,9 +819,9 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \arg CAN_FLAG_ERRIF: error flag \arg CAN_FLAG_SLPWS: sleep working state \arg CAN_FLAG_IWS: initial working state - \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO - \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO - \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in TX FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in TX FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in TX FIFO \arg CAN_FLAG_TME2: transmit mailbox 2 empty \arg CAN_FLAG_TME1: transmit mailbox 1 empty \arg CAN_FLAG_TME0: transmit mailbox 0 empty @@ -902,17 +848,17 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \retval FlagStatus: SET or RESET */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ +{ /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear CAN flag state + \brief clear CAN flag state \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN flags, refer to can_flag_enum @@ -945,7 +891,63 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) } /*! - \brief get CAN interrupt flag state + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN interrupt flag state \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum @@ -973,29 +975,29 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f { uint32_t ret1 = RESET; uint32_t ret2 = RESET; - - /* get the staus of interrupt flag */ - if (flag == CAN_INT_FLAG_RFF0) { + + /* get the status of interrupt flag */ + if(flag == CAN_INT_FLAG_RFL0) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); - } else if (flag == CAN_INT_FLAG_RFF1) { + } else if(flag == CAN_INT_FLAG_RFL1) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); - } else if (flag == CAN_INT_FLAG_ERRN) { + } else if(flag == CAN_INT_FLAG_ERRN) { ret1 = can_error_get(can_periph); } else { ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); } - /* get the staus of interrupt enale bit */ + /* get the status of interrupt enable bit */ ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); - if(ret1 && ret2){ + if(ret1 && ret2) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear CAN interrupt flag state - \param[in] can_periph + \brief clear CAN interrupt flag state + \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c index 2e369e7..b0cf588 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c @@ -2,35 +2,33 @@ \file gd32f4xx_crc.c \brief CRC driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -38,8 +36,9 @@ OF SUCH DAMAGE. #define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) #define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + /*! - \brief deinit CRC calculation unit + \brief deinit CRC calculation unit \param[in] none \param[out] none \retval none @@ -52,7 +51,7 @@ void crc_deinit(void) } /*! - \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF + \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF \param[in] none \param[out] none \retval none @@ -63,7 +62,7 @@ void crc_data_register_reset(void) } /*! - \brief read the value of the data register + \brief read the value of the data register \param[in] none \param[out] none \retval 32-bit value of the data register @@ -76,7 +75,7 @@ uint32_t crc_data_register_read(void) } /*! - \brief read the value of the free data register + \brief read the value of the free data register \param[in] none \param[out] none \retval 8-bit value of the free data register @@ -89,7 +88,7 @@ uint8_t crc_free_data_register_read(void) } /*! - \brief write data to the free data register + \brief write data to the free data register \param[in] free_data: specified 8-bit data \param[out] none \retval none @@ -100,7 +99,7 @@ void crc_free_data_register_write(uint8_t free_data) } /*! - \brief calculate the CRC value of a 32-bit data + \brief calculate the CRC value of a 32-bit data \param[in] sdata: specified 32-bit data \param[out] none \retval 32-bit value calculated by CRC @@ -112,7 +111,7 @@ uint32_t crc_single_data_calculate(uint32_t sdata) } /*! - \brief calculate the CRC value of an array of 32-bit values + \brief calculate the CRC value of an array of 32-bit values \param[in] array: pointer to an array of 32-bit values \param[in] size: size of the array \param[out] none @@ -121,7 +120,7 @@ uint32_t crc_single_data_calculate(uint32_t sdata) uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) { uint32_t index; - for(index = 0U; index < size; index++){ + for(index = 0U; index < size; index++) { CRC_DATA = array[index]; } return (CRC_DATA); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c index 1ad9e01..9492d95 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c @@ -2,35 +2,33 @@ \file gd32f4xx_ctc.c \brief CTC driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -135,27 +133,12 @@ void ctc_refsource_polarity_config(uint32_t polarity) CTC_CTL1 |= (uint32_t)polarity; } -/*! - \brief select USBFS or USBHS SOF signal - \param[in] usbsof: - \arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected - \arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected - \param[out] none - \retval none -*/ -void ctc_usbsof_signal_select(uint32_t usbsof) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); - CTC_CTL1 |= (uint32_t)usbsof; -} - /*! \brief select reference signal source \param[in] refs: only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_GPIO: GPIO is selected \arg CTC_REFSOURCE_LXTAL: LXTAL is selected - \arg CTC_REFSOURCE_USBSOF: USBSOF is selected \param[out] none \retval none */ @@ -221,7 +204,7 @@ void ctc_counter_reload_value_config(uint16_t reload_value) uint16_t ctc_counter_capture_value_read(void) { uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> CTC_REFCAP_OFFSET); + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> CTC_REFCAP_OFFSET); return (capture_value); } @@ -235,9 +218,9 @@ uint16_t ctc_counter_capture_value_read(void) */ FlagStatus ctc_counter_direction_read(void) { - if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { return SET; - }else{ + } else { return RESET; } } @@ -281,7 +264,7 @@ uint8_t ctc_irc48m_trim_value_read(void) */ void ctc_interrupt_enable(uint32_t interrupt) { - CTC_CTL0 |= (uint32_t)interrupt; + CTC_CTL0 |= (uint32_t)interrupt; } /*! @@ -297,7 +280,7 @@ void ctc_interrupt_enable(uint32_t interrupt) */ void ctc_interrupt_disable(uint32_t interrupt) { - CTC_CTL0 &= (uint32_t)(~interrupt); + CTC_CTL0 &= (uint32_t)(~interrupt); } /*! @@ -305,11 +288,11 @@ void ctc_interrupt_disable(uint32_t interrupt) \param[in] int_flag: the CTC interrupt flag only one parameter can be selected which is shown as below: \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt \arg CTC_INT_FLAG_EREF: expect reference interrupt \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt \param[out] none \retval FlagStatus: SET or RESET @@ -317,20 +300,20 @@ void ctc_interrupt_disable(uint32_t interrupt) FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) { uint32_t interrupt_flag = 0U, intenable = 0U; - + /* check whether the interrupt is enabled */ - if(RESET != (int_flag & CTC_FLAG_MASK)){ + if(RESET != (int_flag & CTC_FLAG_MASK)) { intenable = CTC_CTL0 & CTC_CTL0_ERRIE; - }else{ + } else { intenable = CTC_CTL0 & int_flag; } - + /* get interrupt flag status */ interrupt_flag = CTC_STAT & int_flag; - if(interrupt_flag && intenable){ + if(interrupt_flag && intenable) { return SET; - }else{ + } else { return RESET; } } @@ -340,20 +323,20 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) \param[in] int_flag: the CTC interrupt flag only one parameter can be selected which is shown as below: \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt \param[out] none \retval none -*/ +*/ void ctc_interrupt_flag_clear(uint32_t int_flag) { - if(RESET != (int_flag & CTC_FLAG_MASK)){ + if(RESET != (int_flag & CTC_FLAG_MASK)) { CTC_INTC |= CTC_INTC_ERRIC; - }else{ + } else { CTC_INTC |= int_flag; } } @@ -361,10 +344,10 @@ void ctc_interrupt_flag_clear(uint32_t int_flag) /*! \brief get CTC flag \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: + only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_CKERR: clock trim error bit \arg CTC_FLAG_REFMISS: reference sync pulse miss @@ -374,9 +357,9 @@ void ctc_interrupt_flag_clear(uint32_t int_flag) */ FlagStatus ctc_flag_get(uint32_t flag) { - if(RESET != (CTC_STAT & flag)){ + if(RESET != (CTC_STAT & flag)) { return SET; - }else{ + } else { return RESET; } } @@ -386,8 +369,8 @@ FlagStatus ctc_flag_get(uint32_t flag) \param[in] flag: the CTC flag only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_CKERR: clock trim error bit \arg CTC_FLAG_REFMISS: reference sync pulse miss @@ -397,9 +380,9 @@ FlagStatus ctc_flag_get(uint32_t flag) */ void ctc_flag_clear(uint32_t flag) { - if(RESET != (flag & CTC_FLAG_MASK)){ + if(RESET != (flag & CTC_FLAG_MASK)) { CTC_INTC |= CTC_INTC_ERRIC; - }else{ + } else { CTC_INTC |= flag; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c index b789856..180881c 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_dac.c \brief DAC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,7 +40,7 @@ OF SUCH DAMAGE. #define DH_8BIT_OFFSET ((uint32_t)8U) /*! - \brief deinitialize DAC + \brief deinitialize DAC \param[in] none \param[out] none \retval none @@ -54,97 +52,97 @@ void dac_deinit(void) } /*! - \brief enable DAC + \brief enable DAC \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DEN1; } -} +} /*! - \brief disable DAC + \brief disable DAC \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DEN1; } } /*! - \brief enable DAC DMA function + \brief enable DAC DMA function \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_dma_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DDMAEN1; } } /*! - \brief disable DAC DMA function + \brief disable DAC DMA function \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_dma_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DDMAEN1; } } /*! - \brief enable DAC output buffer + \brief enable DAC output buffer \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_output_buffer_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DBOFF1; } } /*! - \brief disable DAC output buffer + \brief disable DAC output buffer \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_output_buffer_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DBOFF0; - }else{ + } else { DAC_CTL |= DAC_CTL_DBOFF1; } } /*! - \brief get DAC output value + \brief get DAC output value \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval DAC output data @@ -152,10 +150,10 @@ void dac_output_buffer_disable(uint32_t dac_periph) uint16_t dac_output_value_get(uint32_t dac_periph) { uint16_t data = 0U; - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* store the DAC0 output value */ data = (uint16_t)DAC0_DO; - }else{ + } else { /* store the DAC1 output value */ data = (uint16_t)DAC1_DO; } @@ -163,7 +161,7 @@ uint16_t dac_output_value_get(uint32_t dac_periph) } /*! - \brief set the DAC specified data holding register value + \brief set the DAC specified data holding register value \param[in] dac_periph: DACx(x = 0,1) \param[in] dac_align: data alignment only one parameter can be selected which is shown as below: @@ -176,8 +174,8 @@ uint16_t dac_output_value_get(uint32_t dac_periph) */ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) { - if(DAC0 == dac_periph){ - switch(dac_align){ + if(DAC0 == dac_periph) { + switch(dac_align) { /* data right 12 bit alignment */ case DAC_ALIGN_12B_R: DAC0_R12DH = data; @@ -193,8 +191,8 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) default: break; } - }else{ - switch(dac_align){ + } else { + switch(dac_align) { /* data right 12 bit alignment */ case DAC_ALIGN_12B_R: DAC1_R12DH = data; @@ -214,37 +212,37 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) } /*! - \brief enable DAC trigger + \brief enable DAC trigger \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_trigger_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DTEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DTEN1; } } /*! - \brief disable DAC trigger + \brief disable DAC trigger \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_trigger_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DTEN1; } } /*! - \brief set DAC trigger source + \brief set DAC trigger source \param[in] dac_periph: DACx(x = 0,1) \param[in] triggersource: external triggers of DAC only one parameter can be selected which is shown as below: @@ -259,13 +257,13 @@ void dac_trigger_disable(uint32_t dac_periph) \param[out] none \retval none */ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL0; DAC_CTL |= triggersource; - }else{ + } else { /* configure DAC1 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL1; DAC_CTL |= (triggersource << DAC1_REG_OFFSET); @@ -273,36 +271,36 @@ void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) } /*! - \brief enable DAC software trigger + \brief enable DAC software trigger \param[in] dac_periph: DACx(x = 0,1) \retval none */ void dac_software_trigger_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_SWT |= DAC_SWT_SWTR0; - }else{ + } else { DAC_SWT |= DAC_SWT_SWTR1; } } /*! - \brief disable DAC software trigger + \brief disable DAC software trigger \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_software_trigger_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ + } else { DAC_SWT &= ~DAC_SWT_SWTR1; } } /*! - \brief configure DAC wave mode + \brief configure DAC wave mode \param[in] dac_periph: DACx(x = 0,1) \param[in] wave_mode: noise wave mode only one parameter can be selected which is shown as below: @@ -314,11 +312,11 @@ void dac_software_trigger_disable(uint32_t dac_periph) */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 wave mode */ DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL |= wave_mode; - }else{ + } else { /* configure DAC1 wave mode */ DAC_CTL &= ~DAC_CTL_DWM1; DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); @@ -326,7 +324,7 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) } /*! - \brief configure DAC wave bit width + \brief configure DAC wave bit width \param[in] dac_periph: DACx(x = 0,1) \param[in] bit_width: noise wave bit width only one parameter can be selected which is shown as below: @@ -347,11 +345,11 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) */ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= bit_width; - }else{ + } else { /* configure DAC1 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (bit_width << DAC1_REG_OFFSET); @@ -359,7 +357,7 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) } /*! - \brief configure DAC LFSR noise mode + \brief configure DAC LFSR noise mode \param[in] dac_periph: DACx(x = 0,1) \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode only one parameter can be selected which is shown as below: @@ -380,11 +378,11 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) */ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= unmask_bits; - }else{ + } else { /* configure DAC1 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); @@ -392,7 +390,7 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) } /*! - \brief configure DAC triangle noise mode + \brief configure DAC triangle noise mode \param[in] dac_periph: DACx(x = 0,1) \param[in] amplitude: triangle amplitude in DAC triangle noise mode only one parameter can be selected which is shown as below: @@ -413,11 +411,11 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= amplitude; - }else{ + } else { /* configure DAC1 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (amplitude << DAC1_REG_OFFSET); @@ -425,7 +423,7 @@ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) } /*! - \brief enable DAC concurrent mode + \brief enable DAC concurrent mode \param[in] none \param[out] none \retval none @@ -438,7 +436,7 @@ void dac_concurrent_enable(void) } /*! - \brief disable DAC concurrent mode + \brief disable DAC concurrent mode \param[in] none \param[out] none \retval none @@ -451,7 +449,7 @@ void dac_concurrent_disable(void) } /*! - \brief enable DAC concurrent software trigger function + \brief enable DAC concurrent software trigger function \param[in] none \param[out] none \retval none @@ -460,11 +458,11 @@ void dac_concurrent_software_trigger_enable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); + DAC_SWT |= (swt); } /*! - \brief disable DAC concurrent software trigger function + \brief disable DAC concurrent software trigger function \param[in] none \param[out] none \retval none @@ -477,7 +475,7 @@ void dac_concurrent_software_trigger_disable(void) } /*! - \brief enable DAC concurrent buffer function + \brief enable DAC concurrent buffer function \param[in] none \param[out] none \retval none @@ -490,7 +488,7 @@ void dac_concurrent_output_buffer_enable(void) } /*! - \brief disable DAC concurrent buffer function + \brief disable DAC concurrent buffer function \param[in] none \param[out] none \retval none @@ -503,7 +501,7 @@ void dac_concurrent_output_buffer_disable(void) } /*! - \brief set DAC concurrent mode data holding register value + \brief set DAC concurrent mode data holding register value \param[in] dac_align: data alignment only one parameter can be selected which is shown as below: \arg DAC_ALIGN_8B_R: data right 8b alignment @@ -517,7 +515,7 @@ void dac_concurrent_output_buffer_disable(void) void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) { uint32_t data = 0U; - switch(dac_align){ + switch(dac_align) { /* data right 12b alignment */ case DAC_ALIGN_12B_R: data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; @@ -539,7 +537,7 @@ void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) } /*! - \brief enable DAC concurrent interrupt funcution + \brief enable DAC concurrent interrupt funcution \param[in] none \param[out] none \retval none @@ -552,7 +550,7 @@ void dac_concurrent_interrupt_enable(void) } /*! - \brief disable DAC concurrent interrupt funcution + \brief disable DAC concurrent interrupt funcution \param[in] none \param[out] none \retval none @@ -565,75 +563,75 @@ void dac_concurrent_interrupt_disable(void) } /*! - \brief enable DAC interrupt(DAC DMA underrun interrupt) + \brief get the specified DAC flag (DAC DMA underrun flag) \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void dac_interrupt_enable(uint32_t dac_periph) +FlagStatus dac_flag_get(uint32_t dac_periph) { - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL |= DAC_CTL_DDUDRIE1; + FlagStatus temp_flag = RESET; + if(DAC0 == dac_periph) { + /* check the DMA underrun flag */ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)) { + temp_flag = SET; + } + } else { + /* check the DMA underrun flag */ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)) { + temp_flag = SET; + } } + return temp_flag; } /*! - \brief disable DAC interrupt(DAC DMA underrun interrupt) + \brief clear the specified DAC flag (DAC DMA underrun flag) \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_interrupt_disable(uint32_t dac_periph) +void dac_flag_clear(uint32_t dac_periph) { - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL &= ~DAC_CTL_DDUDRIE1; + if(DAC0 == dac_periph) { + DAC_STAT |= DAC_STAT_DDUDR0; + } else { + DAC_STAT |= DAC_STAT_DDUDR1; } } /*! - \brief get the specified DAC flag (DAC DMA underrun flag) + \brief enable DAC interrupt(DAC DMA underrun interrupt) \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval FlagStatus: SET or RESET + \retval none */ -FlagStatus dac_flag_get(uint32_t dac_periph) +void dac_interrupt_enable(uint32_t dac_periph) { - FlagStatus temp_flag = RESET; - if(DAC0 == dac_periph){ - /* check the DMA underrun flag */ - if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)){ - temp_flag = SET; - } - }else{ - /* check the DMA underrun flag */ - if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)){ - temp_flag = SET; - } + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDUDRIE0; + } else { + DAC_CTL |= DAC_CTL_DDUDRIE1; } - return temp_flag; } /*! - \brief clear the specified DAC flag (DAC DMA underrun flag) + \brief disable DAC interrupt(DAC DMA underrun interrupt) \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_flag_clear(uint32_t dac_periph) +void dac_interrupt_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ - DAC_STAT |= DAC_STAT_DDUDR0; - }else{ - DAC_STAT |= DAC_STAT_DDUDR1; + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDUDRIE0; + } else { + DAC_CTL &= ~DAC_CTL_DDUDRIE1; } } /*! - \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval FlagStatus: SET or RESET @@ -643,18 +641,18 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) FlagStatus temp_flag = RESET; uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { temp_flag = SET; } - }else{ + } else { /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1; ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { temp_flag = SET; } } @@ -662,16 +660,16 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) } /*! - \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_interrupt_flag_clear(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_STAT |= DAC_STAT_DDUDR0; - }else{ + } else { DAC_STAT |= DAC_STAT_DDUDR1; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c index 4cbdba5..0fe3a40 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_dbg.c \brief DBG driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -95,29 +93,28 @@ void dbg_low_power_disable(uint32_t dbg_low_power) \brief enable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum only one parameter can be selected which is shown as below: - \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted - \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted - \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted - \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted - \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted - \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted - \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted - \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted - \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted - \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted - \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted - \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted - \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted - \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted - \arg \param[out] none + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted \retval none */ void dbg_periph_enable(dbg_periph_enum dbg_periph) @@ -129,28 +126,28 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph) \brief disable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum only one parameter can be selected which is shown as below: - \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted - \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted - \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted - \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted - \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted - \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted - \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted - \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted - \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted - \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted - \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted - \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted - \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted - \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted \param[out] none \retval none */ @@ -181,18 +178,3 @@ void dbg_trace_pin_disable(void) DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; } -/*! - \brief trace pin mode selection - \param[in] trace_mode: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE; - DBG_CTL0 |= trace_mode; -} diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c index 45576e2..8548e65 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_dci.c \brief DCI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -62,7 +60,7 @@ void dci_deinit(void) \param[out] none \retval none */ -void dci_init(dci_parameter_struct* dci_struct) +void dci_init(dci_parameter_struct *dci_struct) { uint32_t reg = 0U; /* disable capture function and DCI */ @@ -79,18 +77,18 @@ void dci_init(dci_parameter_struct* dci_struct) } /*! - \brief enable DCI function + \brief enable DCI function \param[in] none \param[out] none \retval none */ void dci_enable(void) { - DCI_CTL |= DCI_CTL_DCIEN; + DCI_CTL |= DCI_CTL_DCIEN; } /*! - \brief disable DCI function + \brief disable DCI function \param[in] none \param[out] none \retval none @@ -101,7 +99,7 @@ void dci_disable(void) } /*! - \brief enable DCI capture + \brief enable DCI capture \param[in] none \param[out] none \retval none @@ -112,7 +110,7 @@ void dci_capture_enable(void) } /*! - \brief disable DCI capture + \brief disable DCI capture \param[in] none \param[out] none \retval none @@ -123,7 +121,7 @@ void dci_capture_disable(void) } /*! - \brief enable DCI jpeg mode + \brief enable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -134,7 +132,7 @@ void dci_jpeg_enable(void) } /*! - \brief disable DCI jpeg mode + \brief disable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -167,7 +165,7 @@ void dci_crop_window_disable(void) } /*! - \brief configure DCI cropping window + \brief configure DCI cropping window \param[in] start_x: window horizontal start position \param[in] start_y: window vertical start position \param[in] size_width: window horizontal size @@ -177,8 +175,8 @@ void dci_crop_window_disable(void) */ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height) { - DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y<<16)); - DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height<<16)); + DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y << 16)); + DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height << 16)); } /*! @@ -213,7 +211,7 @@ void dci_embedded_sync_disable(void) */ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); } /*! @@ -227,7 +225,7 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); } /*! @@ -258,18 +256,18 @@ uint32_t dci_data_read(void) FlagStatus dci_flag_get(uint32_t flag) { uint32_t stat = 0U; - - if(flag >> 31){ + + if(flag >> 31) { /* get flag status from DCI_STAT1 register */ stat = DCI_STAT1; - }else{ + } else { /* get flag status from DCI_STAT0 register */ stat = DCI_STAT0; } - - if(flag & stat){ + + if(flag & stat) { return SET; - }else{ + } else { return RESET; } } @@ -279,7 +277,7 @@ FlagStatus dci_flag_get(uint32_t flag) \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none @@ -295,7 +293,7 @@ void dci_interrupt_enable(uint32_t interrupt) \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none @@ -311,7 +309,7 @@ void dci_interrupt_disable(uint32_t interrupt) \param[in] int_flag: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none @@ -327,7 +325,7 @@ void dci_interrupt_flag_clear(uint32_t int_flag) \param[in] int_flag: \arg DCI_INT_FLAG_EF: end of frame interrupt flag \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag - \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag + \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag \arg DCI_INT_FLAG_EL: end of line interrupt flag \param[out] none @@ -335,9 +333,9 @@ void dci_interrupt_flag_clear(uint32_t int_flag) */ FlagStatus dci_interrupt_flag_get(uint32_t int_flag) { - if(RESET == (DCI_INTF & int_flag)){ + if(RESET == (DCI_INTF & int_flag)) { return RESET; - }else{ + } else { return SET; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c index 1ec4eef..a188938 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c @@ -1,40 +1,36 @@ /*! \file gd32f4xx_dma.c \brief DMA driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - #include "gd32f4xx_dma.h" /* DMA register bit offset */ @@ -52,19 +48,19 @@ OF SUCH DAMAGE. void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) { /* disable DMA a channel */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; /* reset DMA channel registers */ - DMA_CHCTL(dma_periph,channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph,channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph,channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHM0ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_CHM1ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_CHFCTL(dma_periph,channelx) = DMA_CHFCTL_RESET_VALUE; - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); - }else{ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE; + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); + } else { channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); } } @@ -74,7 +70,7 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) \param[out] none \retval none */ -void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct) +void dma_single_data_para_struct_init(dma_single_data_parameter_struct *init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; @@ -94,7 +90,7 @@ void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_str \param[out] none \retval none */ -void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct) +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct *init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; @@ -123,56 +119,56 @@ void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struc memory0_addr: memory base address memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none */ -void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct) +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct *init_struct) { uint32_t ctl; - + /* select single data mode */ - DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN; - + DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_MDMEN; + /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; - + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; - + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; + /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct->number; - + DMA_CHCNT(dma_periph, channelx) = init_struct->number; + /* configure peripheral and memory transfer width,channel priotity,transfer mode */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } } @@ -185,7 +181,7 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d \param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode periph_addr: peripheral base address periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX memory0_addr: memory0 base address memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE @@ -195,53 +191,54 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none */ -void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct) +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct *init_struct) { uint32_t ctl; - + /* select multi data mode and configure FIFO critical value */ - DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); - + DMA_CHFCTL(dma_periph, channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); + /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; - + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; - + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; + /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct->number; - + DMA_CHCNT(dma_periph, channelx) = init_struct->number; + /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); - ctl |= (init_struct->periph_width | (init_struct->memory_width ) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | init_struct->periph_burst_width); - DMA_CHCTL(dma_periph,channelx) = ctl; + ctl |= (init_struct->periph_width | (init_struct->memory_width) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | + init_struct->periph_burst_width); + DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } } @@ -257,14 +254,14 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm */ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { - DMA_CHPADDR(dma_periph,channelx) = address; + DMA_CHPADDR(dma_periph, channelx) = address; } /*! \brief set DMA Memory0 base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set Memory base address + \param[in] channelx: specify which DMA channel to set Memory base address \arg DMA_CHx(x=0..7) \param[in] memory_flag: DMA_MEMORY_x(x=0,1) \param[in] address: Memory base address @@ -273,10 +270,10 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) { - if(memory_flag){ - DMA_CHM1ADDR(dma_periph,channelx) = address; - }else{ - DMA_CHM0ADDR(dma_periph,channelx) = address; + if(memory_flag) { + DMA_CHM1ADDR(dma_periph, channelx) = address; + } else { + DMA_CHM0ADDR(dma_periph, channelx) = address; } } @@ -292,21 +289,21 @@ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, u */ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) { - DMA_CHCNT(dma_periph,channelx) = number; + DMA_CHCNT(dma_periph, channelx) = number; } /*! \brief get the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number + \param[in] channelx: specify which DMA channel to set number \arg DMA_CHx(x=0..7) \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA + \retval uint32_t: the number of remaining data to be transferred by the DMA */ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) { - return (uint32_t)DMA_CHCNT(dma_periph,channelx); + return (uint32_t)DMA_CHCNT(dma_periph, channelx); } /*! @@ -322,17 +319,17 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) \arg DMA_PRIORITY_HIGH: high priority \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority \param[out] none - \retval none + \retval none */ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PRIO; ctl |= priority; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! @@ -349,15 +346,15 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_ \param[out] none \retval none */ -void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) +void dma_memory_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_MBURST; ctl |= mbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! @@ -375,15 +372,15 @@ void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channe \param[out] none \retval none */ -void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) +void dma_periph_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PBURST; ctl |= pbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! @@ -404,18 +401,18 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_MWIDTH; ctl |= msize; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure transfer data size of peripheral + \brief configure transfer data size of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] msize: transfer data size of peripheral only one parameter can be selected which is shown as below: @@ -425,22 +422,22 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin \param[out] none \retval none */ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PWIDTH; ctl |= psize; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! \brief configure memory address generation generation_algorithm \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] generation_algorithm: the address generation algorithm only one parameter can be selected which is shown as below: @@ -451,10 +448,10 @@ void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, ui */ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) { - if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } } @@ -462,7 +459,7 @@ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum \brief configure peripheral address generation_algorithm \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] generation_algorithm: the address generation algorithm only one parameter can be selected which is shown as below: @@ -474,13 +471,13 @@ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum */ void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) { - if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; } } @@ -488,63 +485,63 @@ void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_e \brief enable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval none */ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; } /*! \brief disable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval none */ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } /*! \brief enable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval none */ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; } /*! \brief disable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval none */ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; } /*! \brief configure the direction of data transfer on the channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] direction: specify the direction of data transfer only one parameter can be selected which is shown as below: @@ -558,34 +555,34 @@ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channel { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_TM; ctl |= direction; - - DMA_CHCTL(dma_periph,channelx) = ctl; + + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! \brief DMA switch buffer mode config \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] memory1_addr: memory1 base address \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 \param[out] none - \retval none + \retval none */ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) { /* configure memory1 base address */ - DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; + DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr; - if(DMA_MEMORY_0 == memory_select){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; + if(DMA_MEMORY_0 == memory_select) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS; } } @@ -593,16 +590,16 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel \brief DMA using memory get \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval the using memory + \retval the using memory */ uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) { - if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ + if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) { return DMA_MEMORY_1; - }else{ + } else { return DMA_MEMORY_0; } } @@ -611,32 +608,32 @@ uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) \brief DMA channel peripheral select \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] sub_periph: specify DMA channel peripheral \arg DMA_SUBPERIx(x=0..7) \param[out] none - \retval none + \retval none */ void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PERIEN; ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); - - DMA_CHCTL(dma_periph,channelx) = ctl; + + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! \brief DMA flow controller configure \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) - \param[in] controller: specify DMA flow controler + \param[in] controller: specify DMA flow controler only one parameter can be selected which is shown as below: \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller @@ -645,10 +642,10 @@ void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum chan */ void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) { - if(DMA_FLOW_CONTROLLER_DMA == controller){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; + if(DMA_FLOW_CONTROLLER_DMA == controller) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_TFCS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_TFCS; } } @@ -656,20 +653,20 @@ void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, \brief DMA switch buffer mode enable \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] newvalue: ENABLE or DISABLE \param[out] none - \retval none + \retval none */ void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { /* switch buffer mode enable */ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN; - }else{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_SBMEN; + } else { /* switch buffer mode disable */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_SBMEN; } } @@ -677,18 +674,18 @@ void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channel \brief DMA FIFO status get \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval the using memory + \retval the using memory */ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) { - return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); + return (DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FCNT); } /*! - \brief get DMA flag is set or not + \brief get DMA flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag @@ -705,17 +702,17 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) */ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - if(channelx < DMA_CH4){ - if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ + if(channelx < DMA_CH4) { + if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { return SET; - }else{ + } else { return RESET; } - }else{ + } else { channelx -= (dma_channel_enum)4; - if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ + if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { return SET; - }else{ + } else { return RESET; } } @@ -739,16 +736,66 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx); - }else{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } else { channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag,channelx); + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to enbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) |= source; + } else { + DMA_CHFCTL(dma_periph, channelx) |= source; } } /*! - \brief get DMA interrupt flag is set or not + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to disbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) &= ~source; + } else { + DMA_CHFCTL(dma_periph, channelx) &= ~source; + } +} + +/*! + \brief get DMA interrupt flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get interrupt flag @@ -765,64 +812,64 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla */ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { - uint32_t interrupt_enable = 0U,interrupt_flag = 0U; + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; dma_channel_enum channel_flag_offset = channelx; - if(channelx < DMA_CH4){ - switch(interrupt){ + if(channelx < DMA_CH4) { + switch(interrupt) { case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; break; case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; break; case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; break; case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; break; case DMA_INTF_FTFIF: - interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx)); - interrupt_enable = (DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE); + interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx)); + interrupt_enable = (DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE); break; default: break; } - }else{ + } else { channel_flag_offset -= (dma_channel_enum)4; - switch(interrupt){ + switch(interrupt) { case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; break; case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; break; case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; break; case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; break; case DMA_INTF_FTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; break; default: break; } } - - if(interrupt_flag && interrupt_enable){ + + if(interrupt_flag && interrupt_enable) { return SET; - }else{ + } else { return RESET; } } @@ -845,61 +892,10 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx */ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); - }else{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); + } else { channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); } } - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) |= source; - }else{ - DMA_CHFCTL(dma_periph,channelx) |= source; - } -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) &= ~source; - }else{ - DMA_CHFCTL(dma_periph,channelx) &= ~source; - } -} - diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c index 3432058..4065944 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c @@ -2,48 +2,45 @@ \file gd32f4xx_enet.c \brief ENET driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, + Copyright (c) 2023, GigaDevice Semiconductor Inc. + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_enet.h" #if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) +__align(4) enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) +__align(4) enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) +__align(4) uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) +__align(4) uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined ( __ICCARM__ ) /*!< IAR compiler */ @@ -57,10 +54,10 @@ uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive bu uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined (__GNUC__) /* GNU Compiler */ -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ #endif /* __CC_ARM */ @@ -73,25 +70,26 @@ enet_descriptors_struct *dma_current_ptp_txdesc = NULL; enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; /* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static uint32_t enet_unknow_err = 0U; /* array of register offset for debug information get */ static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, -0x104C, 0x1050, 0x1054}; + 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, + 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + + 0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, + 0x104C, 0x1050, 0x1054 +}; /* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ static void enet_default_init(void); #ifdef USE_DELAY /* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms +#define _ENET_DELAY_ delay_ms #else /* insert a delay time */ static void enet_delay(uint32_t ncount); @@ -115,7 +113,7 @@ void enet_deinit(void) /*! \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise + note -- this function must be called before enet_init(), otherwise configuration will be no effect \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum only one parameter can be selected which is shown as below @@ -124,7 +122,7 @@ void enet_deinit(void) \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters \arg VLAN_OPTION: choose to configure vlan related parameters \arg FLOWCTL_OPTION: choose to configure flow control related parameters \arg HASHH_OPTION: choose to configure hash high @@ -133,7 +131,7 @@ void enet_deinit(void) \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters \arg TIMER_OPTION: choose to configure time counter related parameters \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option + \param[in] para: the related parameters according to the option all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters: - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; @@ -179,7 +177,7 @@ void enet_deinit(void) FLOWCTL_OPTION related parameters: - MAC_FCTL_PTM(regval) ; - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; @@ -226,7 +224,7 @@ void enet_deinit(void) */ void enet_initpara_config(enet_option_enum option, uint32_t para) { - switch(option){ + switch(option) { case FORWARD_OPTION: /* choose to configure forward_frame, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; @@ -255,11 +253,11 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case DMA_OPTION: /* choose to configure dma_function, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - + #ifndef SELECT_DESCRIPTORS_ENHANCED_MODE para &= ~ENET_ENHANCED_DESCRIPTOR; -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + enet_initpara.dma_function = para; break; case VLAN_OPTION: @@ -295,7 +293,7 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case TIMER_OPTION: /* choose to configure timer_config, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; + enet_initpara.timer_config = para; break; case INTERFRAMEGAP_OPTION: /* choose to configure interframegap, and save the configuration parameters */ @@ -303,14 +301,14 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) enet_initpara.interframegap = para; break; default: - break; - } -} + break; + } +} /*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared + \brief initialize ENET peripheral with generally concerned parameters and the less cared parameters - \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum + \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum only one parameter can be selected which is shown as below \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex @@ -318,13 +316,13 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum + \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum only one parameter can be selected which is shown as below \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, refer to enet_frmrecept_enum + \param[in] recept: frame filter function, refer to enet_frmrecept_enum only one parameter can be selected which is shown as below \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled \arg ENET_RECEIVEALL: all received frame are forwarded to application @@ -335,193 +333,193 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) */ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) { - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; uint32_t media_temp = 0U; uint32_t timeout = 0U; uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; + ErrStatus phy_state = ERROR, enet_state = ERROR; /* PHY interface configuration, configure SMI clock and reset PHY chip */ -// if(ERROR == enet_phy_config()){ -// _ENET_DELAY_(PHY_RESETDELAY); -// if(ERROR == enet_phy_config()){ -// return enet_state; -// } -// } +/** AvV **/ +// if(ERROR == enet_phy_config()) { +// _ENET_DELAY_(PHY_RESETDELAY); +// if(ERROR == enet_phy_config()) { +// return enet_state; +// } +// } +/** AvV **/ /* initialize ENET peripheral with generally concerned parameters */ enet_default_init(); /* 1st, configure mediamode */ media_temp = (uint32_t)mediamode; /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { /* wait for PHY_LINKED_STATUS bit be set */ - do{ + do { enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; + phy_value &= PHY_LINKED_STATUS; timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); + } while((RESET == phy_value) && (timeout < PHY_READ_TO)); /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ + if(PHY_READ_TO == timeout) { return enet_state; } - /* reset timeout counter */ timeout = 0U; /* enable auto-negotiation */ phy_value = PHY_AUTONEGOTIATION; phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ + if(!phy_state) { /* return ERROR due to write timeout */ return enet_state; } /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ + do { enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_value &= PHY_AUTONEGO_COMPLETE; timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ + if(PHY_READ_TO == timeout) { return enet_state; } - /* reset timeout counter */ timeout = 0U; /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { media_temp = ENET_MODE_FULLDUPLEX; - }else{ + } else { media_temp = ENET_MODE_HALFDUPLEX; } - + /* configure the communication speed of MAC following the auto-negotiation result */ #if(PHY_TYPE == RTL8201F) /** AvV **/ if ((uint16_t) RESET == (phy_value & PHY_SPEED_STATUS)) { #else if ((uint16_t) RESET != (phy_value & PHY_SPEED_STATUS)) { #endif - media_temp |= ENET_SPEEDMODE_10M; - } else { - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ -// phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); -// phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); -// phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); -// if(!phy_state){ -// /* return ERROR due to write timeout */ -// return enet_state; -// } -// /* PHY configuration need some time */ -// _ENET_DELAY_(PHY_CONFIGDELAY); + media_temp |= ENET_SPEEDMODE_10M; + } else { + media_temp |= ENET_SPEEDMODE_100M; + } + } else { +// phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); +// phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); +// phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); +// if(!phy_state) { +// /* return ERROR due to write timeout */ +// return enet_state; +// } +// /* PHY configuration need some time */ +// _ENET_DELAY_(PHY_CONFIGDELAY); } /* after configuring the PHY, use mediamode to configure registers */ reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); reg_value |= media_temp; ENET_MAC_CFG = reg_value; - - + + /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ reg_value &= ~ENET_DMA_CTL_DTCERFD; reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); ENET_DMA_CTL = reg_value; } - + /* 3rd, configure recept */ ENET_MAC_FRMF |= (uint32_t)recept; /* 4th, configure different function options */ /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { reg_temp = enet_initpara.forward_frame; reg_value = ENET_MAC_CFG; temp = reg_temp; /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD)); + reg_value &= (~(ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD)); temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); reg_value |= temp; ENET_MAC_CFG = reg_value; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); reg_value |= (temp >> 2); ENET_DMA_CTL = reg_value; } /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { temp = enet_initpara.dmabus_mode; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + | ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { temp = enet_initpara.dma_maxburst; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { temp = enet_initpara.dma_arbitration; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); reg_value |= temp; ENET_DMA_BCTL = reg_value; } - + /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { temp = enet_initpara.store_forward_mode; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); reg_value |= temp; ENET_DMA_CTL = reg_value; } /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { reg_temp = enet_initpara.dma_function; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); reg_value |= temp; ENET_DMA_CTL = reg_value; - + reg_value = ENET_DMA_BCTL; temp = reg_temp; /* configure ENET_DMA_BCTL register */ @@ -532,9 +530,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { reg_temp = enet_initpara.vlan_config; - + reg_value = ENET_MAC_VLT; /* configure ENET_MAC_VLT register */ reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); @@ -543,84 +541,84 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { reg_temp = enet_initpara.flow_control; reg_value = ENET_MAC_FCTL; temp = reg_temp; /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); reg_value |= temp; ENET_MAC_FCTL = reg_value; reg_value = ENET_MAC_FCTH; temp = reg_temp; /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD ) << 8); + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8); reg_value |= (temp >> 8); ENET_MAC_FCTH = reg_value; } /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { ENET_MAC_HLH = enet_initpara.hashtable_high; - } + } /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { ENET_MAC_HLL = enet_initpara.hashtable_low; - } + } /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { reg_temp = enet_initpara.framesfilter_mode; - + reg_value = ENET_MAC_FRMF; /* configure ENET_MAC_FRMF register */ reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); reg_value |= reg_temp; ENET_MAC_FRMF = reg_value; - } + } /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { reg_temp = enet_initpara.halfduplex_param; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { reg_temp = enet_initpara.timer_config; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } - + } + /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { reg_temp = enet_initpara.interframegap; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~ENET_MAC_CFG_IGBS; reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } enet_state = SUCCESS; return enet_state; @@ -637,21 +635,21 @@ ErrStatus enet_software_reset(void) uint32_t timeout = 0U; ErrStatus enet_state = ERROR; uint32_t dma_flag; - + /* reset all core internal registers located in CLK_TX and CLK_RX */ ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - + /* wait for reset operation complete */ - do{ + do { dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { enet_state = SUCCESS; } - + return enet_state; } @@ -665,19 +663,19 @@ uint32_t enet_rxframe_size_get(void) { uint32_t size = 0U; uint32_t status; - + /* get rdes0 information of current RxDMA descriptor */ status = dma_current_rxdesc->status; - + /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)) { return 0U; } - + /* if has any error, or the frame uses two or more descriptors */ if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { /* drop current receive frame */ enet_rxframe_drop(); @@ -686,44 +684,44 @@ uint32_t enet_rxframe_size_get(void) #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE /* if is an ethernet-type frame, and IP frame payload error occurred */ if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && - ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){ - /* drop current receive frame */ - enet_rxframe_drop(); + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)) { + /* drop current receive frame */ + enet_rxframe_drop(); return 1U; } -#else +#else /* if is an ethernet-type frame, and IP frame payload error occurred */ if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); return 1U; - } -#endif + } +#endif /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { /* get the size of the received data including CRC */ size = GET_RDES0_FRML(status); - /* substract the CRC size */ + /* substract the CRC size */ size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))) { size = size + 4U; } - }else{ + } else { enet_unknow_err++; enet_rxframe_drop(); return 1U; } - - /* return packet size */ + + /* return packet size */ return size; } @@ -741,62 +739,62 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; + uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; maxsize = ENET_TXBUF_SIZE; - + /* select chain mode */ desc_status = ENET_TDES0_TCHM; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; maxsize = ENET_RXBUF_SIZE; - + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; } - } + } } /*! @@ -814,64 +812,64 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ + + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! @@ -884,69 +882,69 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status); size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } - + /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); } - - }else{ + + } else { /* return ERROR */ return ERROR; } } /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } - + return SUCCESS; } @@ -962,55 +960,55 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) { uint32_t offset = 0U; uint32_t dma_tbu_flag, dma_tu_flag; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; - } - + } + /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } - + /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } @@ -1060,7 +1058,7 @@ void enet_disable(void) } /*! - \brief configure MAC address + \brief configure MAC address \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: set MAC address 0 filter @@ -1068,10 +1066,10 @@ void enet_disable(void) \arg ENET_MAC_ADDRESS2: set MAC address 2 filter \arg ENET_MAC_ADDRESS3: set MAC address 3 filter \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \param[out] none \retval none -*/ +*/ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) { REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); @@ -1079,7 +1077,7 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get MAC address + \brief get MAC address \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: get MAC address 0 filter @@ -1087,9 +1085,9 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) \arg ENET_MAC_ADDRESS2: get MAC address 2 filter \arg ENET_MAC_ADDRESS3: get MAC address 3 filter \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \retval none -*/ +*/ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) { paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); @@ -1101,12 +1099,12 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get the ENET MAC/MSC/PTP/DMA status flag + \brief get the ENET MAC/MSC/PTP/DMA status flag \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_MPKR: magic packet received flag \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag \arg ENET_MAC_FLAG_WUM: WUM status flag \arg ENET_MAC_FLAG_MSC: MSC status flag \arg ENET_MAC_FLAG_MSCR: MSC receive status flag @@ -1146,15 +1144,15 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) */ FlagStatus enet_flag_get(enet_flag_enum enet_flag) { - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear the ENET DMA status flag + \brief clear the ENET DMA status flag \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear @@ -1182,7 +1180,7 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) } /*! - \brief enable ENET MAC/MSC/DMA interrupt + \brief enable ENET MAC/MSC/DMA interrupt \param[in] enet_int: ENET interrupt,, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask @@ -1213,17 +1211,17 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) */ void enet_interrupt_enable(enet_int_enum enet_int) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { /* ENET_DMA_INTEN register interrupt */ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ + } else { /* other INTMSK register interrupt */ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); } } /*! - \brief disable ENET MAC/MSC/DMA interrupt + \brief disable ENET MAC/MSC/DMA interrupt \param[in] enet_int: ENET interrupt, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask @@ -1254,17 +1252,17 @@ void enet_interrupt_enable(enet_int_enum enet_int) */ void enet_interrupt_disable(enet_int_enum enet_int) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { /* ENET_DMA_INTEN register interrupt */ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ + } else { /* other INTMSK register interrupt */ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); } } /*! - \brief get ENET MAC/MSC/DMA interrupt flag + \brief get ENET MAC/MSC/DMA interrupt flag \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_FLAG_WUM: WUM status flag @@ -1301,15 +1299,15 @@ void enet_interrupt_disable(enet_int_enum enet_int) */ FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) { - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear ENET DMA interrupt flag + \brief clear ENET DMA interrupt flag \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag @@ -1356,7 +1354,7 @@ void enet_tx_enable(void) \retval none */ void enet_tx_disable(void) -{ +{ ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; enet_txfifo_flush(); ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; @@ -1387,10 +1385,10 @@ void enet_rx_disable(void) } /*! - \brief put registers value into the application buffer + \brief put registers value into the application buffer \param[in] type: register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR @@ -1401,22 +1399,22 @@ void enet_rx_disable(void) void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) { uint32_t offset = 0U, max = 0U, limit = 0U; - + offset = (uint32_t)type; max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); + /* prevent element in this array is out of range */ - if(max > limit){ + if(max > limit) { max = limit; } - - for(; offset < max; offset++){ + + for(; offset < max; offset++) { /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); + *preg = REG32((ENET) + enet_reg_tab[offset]); preg++; } -} +} /*! \brief get the enet debug status from the debug register @@ -1440,8 +1438,8 @@ void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t uint32_t enet_debug_status_get(uint32_t mac_debug) { uint32_t temp_state = 0U; - - switch(mac_debug){ + + switch(mac_debug) { case ENET_RX_ASYNCHRONOUS_FIFO_STATE: temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); break; @@ -1458,16 +1456,16 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); break; default: - if(RESET != (ENET_MAC_DBG & mac_debug)){ + if(RESET != (ENET_MAC_DBG & mac_debug)) { temp_state = 0x1U; } - break; + break; } return temp_state; } /*! - \brief enable the MAC address filter + \brief enable the MAC address filter \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter @@ -1481,7 +1479,7 @@ void enet_address_filter_enable(enet_macaddress_enum mac_addr) } /*! - \brief disable the MAC address filter + \brief disable the MAC address filter \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter @@ -1496,7 +1494,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) } /*! - \brief configure the MAC address filter + \brief configure the MAC address filter \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter @@ -1505,7 +1503,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) \param[in] addr_mask: select which MAC address bytes will be mask one or more parameters can be selected which are shown as below \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits @@ -1520,7 +1518,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) { uint32_t reg; - + /* get the address filter register value which is to be configured */ reg = REG32(ENET_ADDRH_BASE + mac_addr); @@ -1535,55 +1533,55 @@ void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mas \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus enet_phy_config(void) { uint32_t ahbclk; uint32_t reg; uint16_t phy_value; ErrStatus enet_state = ERROR; - + /* clear the previous MDC clock */ reg = ENET_MAC_PHY_CTL; reg &= ~ENET_MAC_PHY_CTL_CLR; /* get the HCLK frequency */ ahbclk = rcu_clock_freq_get(CK_AHB); - + /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)) { reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + } else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)) { reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ + } else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)) { reg |= ENET_MDC_HCLK_DIV42; - }else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)){ + } else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)) { reg |= ENET_MDC_HCLK_DIV62; - }else if((ENET_RANGE(ahbclk, 150000000U, 200000000U))||(200000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV102; - }else{ + } else if((ENET_RANGE(ahbclk, 150000000U, 240000000U)) || (240000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV102; + } else { return enet_state; } ENET_MAC_PHY_CTL = reg; /* reset PHY */ phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { return enet_state; } - /* PHY reset need some time */ + /* PHY reset need some time */ _ENET_DELAY_(ENET_DELAY_TO); - + /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { return enet_state; } /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ + if(RESET == (phy_value & PHY_RESET)) { enet_state = SUCCESS; } - + return enet_state; } @@ -1594,7 +1592,7 @@ ErrStatus enet_phy_config(void) \arg ENET_PHY_READ: read data from phy register \param[in] phy_address: 0x0000 - 0x001F \param[in] phy_reg: 0x0000 - 0x001F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction \retval ErrStatus: SUCCESS or ERROR */ @@ -1604,34 +1602,33 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - /* configure ENET_MAC_PHY_CTL with write/read operation */ + /* configure ENET_MAC_PHY_CTL with write/read operation */ reg = ENET_MAC_PHY_CTL; reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; + if(ENET_PHY_WRITE == direction) { + ENET_MAC_PHY_DATA = *pvalue; } - + /* do PHY write/read operation, and wait the operation complete */ ENET_MAC_PHY_CTL = reg; - do{ + do { phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { enet_state = SUCCESS; } - /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction) { + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; } - + return enet_state; } @@ -1647,7 +1644,7 @@ ErrStatus enet_phyloopback_enable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* enable the PHY loopback mode */ temp_phy |= PHY_LOOPBACK; @@ -1670,7 +1667,7 @@ ErrStatus enet_phyloopback_disable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* disable the PHY loopback mode */ temp_phy &= (uint16_t)~PHY_LOOPBACK; @@ -1695,10 +1692,10 @@ ErrStatus enet_phyloopback_disable(void) void enet_forward_feature_enable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG |= mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL |= (mask >> 2); } @@ -1717,15 +1714,15 @@ void enet_forward_feature_enable(uint32_t feature) void enet_forward_feature_disable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG &= ~mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL &= ~(mask >> 2); } - -/*! + +/*! \brief enable ENET fliter feature \param[in] feature: the feature of ENET fliter mode one or more parameters can be selected which are shown as below @@ -1770,18 +1767,18 @@ void enet_fliter_feature_disable(uint32_t feature) \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state = ERROR; uint32_t temp = 0U; /* in full-duplex mode, must make sure this bit is 0 before writing register */ temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ + if(RESET == temp) { ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; enet_state = SUCCESS; } - return enet_state; + return enet_state; } /*! @@ -1790,7 +1787,7 @@ ErrStatus enet_pauseframe_generate(void) only one parameter can be selected which is shown as below \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected \param[out] none \retval none @@ -1846,7 +1843,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) */ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) { - ENET_MAC_FCTH = ((deactive | active) >> 8); + ENET_MAC_FCTH = ((deactive | active) >> 8); } /*! @@ -1862,7 +1859,7 @@ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) */ void enet_flowcontrol_feature_enable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1882,7 +1879,7 @@ void enet_flowcontrol_feature_enable(uint32_t feature) */ void enet_flowcontrol_feature_disable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1910,7 +1907,7 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) } /*! - \brief poll the DMA transmission/reception enable by writing any value to the + \brief poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below @@ -1921,15 +1918,15 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) */ void enet_dmaprocess_resume(enet_dmadirection_enum direction) { - if(ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { ENET_DMA_TPEN = 0U; - }else{ + } else { ENET_DMA_RPEN = 0U; } } /*! - \brief check and recover the Rx process + \brief check and recover the Rx process \param[in] none \param[out] none \retval none @@ -1938,15 +1935,15 @@ void enet_rxprocess_check_recovery(void) { uint32_t status; - /* get DAV information of current RxDMA descriptor */ + /* get DAV information of current RxDMA descriptor */ status = dma_current_rxdesc->status; status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with receive descriptor address pointer updated by RxDMA controller */ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; } } @@ -1961,19 +1958,19 @@ ErrStatus enet_txfifo_flush(void) uint32_t flush_state; uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - + /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + do { + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(RESET == flush_state){ + if(RESET == flush_state) { enet_state = SUCCESS; } - + return enet_state; } @@ -1989,14 +1986,14 @@ ErrStatus enet_txfifo_flush(void) \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none + \param[out] none \retval address value */ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) { uint32_t reval = 0U; - reval = REG32((ENET) +(uint32_t)addr_get); + reval = REG32((ENET) + (uint32_t)addr_get); return reval; } @@ -2018,36 +2015,36 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate { uint32_t reval = 0xFFFFFFFFU; - switch(info_get){ + switch(info_get) { case RXDESC_BUFFER_1_SIZE: reval = GET_RDES1_RB1S(desc->control_buffer_size); break; case RXDESC_BUFFER_2_SIZE: reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: + break; + case RXDESC_FRAME_LENGTH: reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ + if(reval > 4U) { reval = reval - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))) { reval = reval + 4U; - } - }else{ + } + } else { reval = 0U; } - + break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_COLLISION_COUNT: + case TXDESC_COLLISION_COUNT: reval = GET_TDES0_COCNT(desc->status); - break; + break; default: break; } @@ -2064,7 +2061,7 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) { uint32_t temp_counter = 0U; - + temp_counter = ENET_DMA_MFBOCNT; *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); @@ -2075,7 +2072,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \param[in] desc: the descriptor pointer which users want to get flag \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_DB: deferred \arg ENET_TDES0_UFE: underflow error \arg ENET_TDES0_EXD: excessive deferral \arg ENET_TDES0_VFRM: VLAN frame @@ -2088,18 +2085,18 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_TDES0_JT: jabber timeout \arg ENET_TDES0_ES: error summary \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TTMSS: transmit timestamp status \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error + + \arg ENET_RDES0_PCERR: payload checksum error \arg ENET_RDES0_EXSV: extended status valid \arg ENET_RDES0_CERR: CRC error \arg ENET_RDES0_DBERR: dribble bit error @@ -2112,11 +2109,11 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_RDES0_LDES: last descriptor \arg ENET_RDES0_FDES: first descriptor \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_OERR: overflow error \arg ENET_RDES0_LERR: length error \arg ENET_RDES0_SAFF: SA filter fail \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_ERRS: error summary \arg ENET_RDES0_DAFF: destination address filter fail \arg ENET_RDES0_DAV: descriptor available \param[out] none @@ -2125,8 +2122,8 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) { FlagStatus enet_flag = RESET; - - if ((uint32_t)RESET != (desc->status & desc_flag)){ + + if((uint32_t)RESET != (desc->status & desc_flag)) { enet_flag = SET; } @@ -2143,13 +2140,13 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2168,13 +2165,13 @@ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2184,7 +2181,7 @@ void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2195,7 +2192,7 @@ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct * } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time \param[in] desc: the descriptor pointer which users want to configure \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) \param[out] none @@ -2216,36 +2213,36 @@ void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc void enet_rxframe_drop(void) { /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if(NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); } - - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); } - }else{ + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc) { dma_current_ptp_rxdesc++; } } @@ -2301,8 +2298,8 @@ void enet_dma_feature_disable(uint32_t feature) uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) { uint32_t reval = 0xFFFFFFFFU; - - switch (desc_status){ + + switch(desc_status) { case ENET_RDES4_IPPLDT: reval = GET_RDES4_IPPLDT(desc->extended_status); break; @@ -2310,13 +2307,13 @@ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_ reval = GET_RDES4_PTPMT(desc->extended_status); break; default: - if ((uint32_t)RESET != (desc->extended_status & desc_status)){ + if((uint32_t)RESET != (desc->extended_status & desc_status)) { reval = 1U; - }else{ + } else { reval = 0U; - } + } } - + return reval; } @@ -2346,59 +2343,59 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configuration each descriptor */ - for(num = 0U; num < count; num++){ + + /* configuration each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } - } + } } /*! @@ -2416,69 +2413,69 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ + + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configure each descriptor */ - for(num=0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2491,54 +2488,54 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t offset = 0U, size = 0U; uint32_t timeout = 0U; uint32_t rdes0_tsv_flag; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } /* copy data from Rx buffer to application buffer */ - for(offset = 0; offset < size; offset++){ + for(offset = 0; offset < size; offset++) { (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); } - }else{ + } else { return ERROR; } - } - + } + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and write to the RDES6 and RDES7 */ - do{ + do { rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); timeout++; - }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); - + } while((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; } - + /* clear the ENET_RDES0_TSV flag */ dma_current_rxdesc->status &= ~ENET_RDES0_TSV; /* get the timestamp value of the received frame */ @@ -2548,35 +2545,35 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* Clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct *)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } } - + return SUCCESS; } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2589,56 +2586,56 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t offset = 0; uint32_t dma_tbu_flag, dma_tu_flag; uint32_t tdes0_ttmss_flag; - uint32_t timeout = 0; - + uint32_t timeout = 0; + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; - } + } /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0; offset < length; offset++){ + for(offset = 0; offset < length; offset++) { (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* Clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do { tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; } - + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -2646,18 +2643,18 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, timestamp[1] = dma_current_txdesc->timestamp_high; } - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_txdesc = (enet_descriptors_struct *)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } } @@ -2693,67 +2690,67 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! @@ -2776,57 +2773,57 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive ring mode and set buffer1 size */ desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -2834,14 +2831,14 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2851,37 +2848,37 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ + for(offset = 0U; offset < size; offset++) { (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); } - - }else{ + + } else { return ERROR; } } @@ -2891,42 +2888,42 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - + /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); dma_current_ptp_rxdesc ++; } } @@ -2935,7 +2932,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2946,23 +2943,23 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) { uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; } - + /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } /* set the frame length */ @@ -2971,31 +2968,31 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do { tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; - } - + } + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -3005,30 +3002,30 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ + if(0U != dma_current_ptp_txdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_txdesc++; } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; } } return SUCCESS; @@ -3037,7 +3034,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /*! - \brief wakeup frame filter register pointer reset + \brief wakeup frame filter register pointer reset \param[in] none \param[out] none \retval none @@ -3048,7 +3045,7 @@ void enet_wum_filter_register_pointer_reset(void) } /*! - \brief set the remote wakeup frame registers + \brief set the remote wakeup frame registers \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) \param[out] none \retval none @@ -3056,15 +3053,15 @@ void enet_wum_filter_register_pointer_reset(void) void enet_wum_filter_config(uint32_t pdata[]) { uint32_t num = 0U; - + /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { ENET_MAC_RWFF = pdata[num]; } } /*! - \brief enable wakeup management features + \brief enable wakeup management features \param[in] feature: the wake up type which is selected one or more parameters can be selected which are shown as below \arg ENET_WUM_POWER_DOWN: power down mode @@ -3080,7 +3077,7 @@ void enet_wum_feature_enable(uint32_t feature) } /*! - \brief disable wakeup management features + \brief disable wakeup management features \param[in] feature: the wake up type which is selected one or more parameters can be selected which are shown as below \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception @@ -3095,8 +3092,8 @@ void enet_wum_feature_disable(uint32_t feature) } /*! - \brief reset the MAC statistics counters - \param[in] none + \brief reset the MAC statistics counters + \param[in] none \param[out] none \retval none */ @@ -3124,7 +3121,7 @@ void enet_msc_feature_enable(uint32_t feature) /*! \brief disable the MAC statistics counter features \param[in] feature: the feature of MAC statistics counter - one or more parameters can be selected which are shown as below + one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover \arg ENET_MSC_RESET_ON_READ: reset on read \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze @@ -3133,11 +3130,11 @@ void enet_msc_feature_enable(uint32_t feature) */ void enet_msc_feature_disable(uint32_t feature) { - ENET_MSC_CTL &= (~feature); + ENET_MSC_CTL &= (~feature); } /*! - \brief configure MAC statistics counters preset mode + \brief configure MAC statistics counters preset mode \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum only one parameter can be selected which is shown as below \arg ENET_MSC_PRESET_NONE: do not preset MSC counter @@ -3153,7 +3150,7 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) } /*! - \brief get MAC statistics counter + \brief get MAC statistics counter \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum only one parameter can be selected which is shown as below \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter @@ -3168,9 +3165,9 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) { uint32_t reval; - + reval = REG32((ENET + (uint32_t)counter)); - + return reval; } @@ -3230,7 +3227,7 @@ void enet_ptp_feature_disable(uint32_t feature) \arg ENET_SNOOPING_PTP_VERSION_2: version 2 \arg ENET_SNOOPING_PTP_VERSION_1: version 1 \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot - \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, management and signaling message \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message @@ -3243,7 +3240,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) uint32_t timeout = 0U; ErrStatus enet_state = SUCCESS; - switch(func){ + switch(func) { case ENET_CKNT_ORDINARY: case ENET_CKNT_BOUNDARY: case ENET_CKNT_END_TO_END: @@ -3251,53 +3248,53 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; ENET_PTP_TSCTL |= (uint32_t)func; break; - case ENET_PTP_ADDEND_UPDATE: + case ENET_PTP_ADDEND_UPDATE: /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } + } break; case ENET_PTP_SYSTIME_UPDATE: /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + do { + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; + } + break; case ENET_PTP_SYSTIME_INIT: /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; + } + break; default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))) { + ENET_PTP_TSCTL |= temp_config; + } else { + ENET_PTP_TSCTL &= ~temp_config; } - break; + break; } return enet_state; @@ -3332,7 +3329,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time + \param[in] subsecond: the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns \param[out] none \retval none @@ -3340,7 +3337,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) { ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); } /*! @@ -3359,7 +3356,7 @@ void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) /*! \brief get the current system time \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -3372,9 +3369,9 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) uint32_t temp_sec = 0U, temp_subs = 0U; /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; + temp_sec = (uint32_t)ENET_PTP_TSH; temp_subs = (uint32_t)ENET_PTP_TSL; - + /* get sysytem time and construct the enet_ptp_systime_struct structure */ systime_struct->second = temp_sec; systime_struct->subsecond = GET_PTP_TSL_STMSS(temp_subs); @@ -3386,15 +3383,15 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) \param[in] freq: PPS output frequency only one parameter can be selected which is shown as below \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency - \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency - \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency - \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency - \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency - \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency - \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency @@ -3423,7 +3420,7 @@ void enet_initpara_reset(void) enet_initpara.dma_maxburst = 0U; enet_initpara.dma_arbitration = 0U; enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; + enet_initpara.dma_function = 0U; enet_initpara.vlan_config = 0U; enet_initpara.flow_control = 0U; enet_initpara.hashtable_high = 0U; @@ -3432,10 +3429,10 @@ void enet_initpara_reset(void) enet_initpara.halfduplex_param = 0U; enet_initpara.timer_config = 0U; enet_initpara.interframegap = 0U; -} +} /*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() \param[in] none \param[out] none \retval none @@ -3449,20 +3446,20 @@ static void enet_default_init(void) reg_value = ENET_MAC_CFG; reg_value &= MAC_CFG_MASK; reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_TYPEFRAME_CRC_DROP_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; ENET_MAC_CFG = reg_value; - + /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ ENET_MAC_HLH = 0x0U; @@ -3472,31 +3469,31 @@ static void enet_default_init(void) /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ reg_value = ENET_MAC_FCTL; reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; ENET_MAC_FCTL = reg_value; /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); /* DMA */ /* configure ENET_DMA_CTL register */ reg_value = ENET_DMA_CTL; reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_SECONDFRAME_OPT_DISABLE; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_SECONDFRAME_OPT_DISABLE; ENET_DMA_CTL = reg_value; /* configure ENET_DMA_BCTL register */ reg_value = ENET_DMA_BCTL; reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ - |ENET_NORMAL_DESCRIPTOR; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE | ENET_MIXED_BURST_DISABLE \ + | ENET_NORMAL_DESCRIPTOR; ENET_DMA_BCTL = reg_value; } @@ -3509,9 +3506,9 @@ static void enet_default_init(void) */ static void enet_delay(uint32_t ncount) { - __IO uint32_t delay_time = 0U; - - for(delay_time = ncount; delay_time != 0U; delay_time--){ + __IO uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--) { } } #endif /* USE_DELAY */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c index 11def48..ae15aca 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_exmc.c \brief EXMC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -112,9 +110,6 @@ OF SUCH DAMAGE. #define SDARI_ARINTV_OFFSET ((uint32_t)1U) -#define SDRSCTL_SSCR_OFFSET ((uint32_t)1U) -#define SDRSCTL_SDSC_OFFSET ((uint32_t)4U) - #define SDSTAT_STA0_OFFSET ((uint32_t)1U) #define SDSTAT_STA1_OFFSET ((uint32_t)3U) @@ -124,7 +119,7 @@ OF SUCH DAMAGE. #define INTEN_INTS_OFFSET ((uint32_t)3U) /*! - \brief deinitialize EXMC NOR/SRAM region + \brief deinitialize EXMC NOR/SRAM region \param[in] exmc_norsram_region: select the region of bank0 only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) @@ -140,12 +135,12 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region) } /*! - \brief initialize exmc_norsram_parameter_struct with the default values + \brief initialize exmc_norsram_parameter_struct with the default values \param[in] none \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer \retval none */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { /* configure the structure with default values */ exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; @@ -171,7 +166,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - /* write timing configure, when extended mode is used */ + /* configure write timing, when extended mode is used */ exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; @@ -180,11 +175,11 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i } /*! - \brief initialize EXMC NOR/SRAM region + \brief initialize EXMC NOR/SRAM region \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE + extended_mode: ENABLE or DISABLE asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE @@ -199,7 +194,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 - bus_latency: 0x0U~0xFU + bus_latency: 0x0U~0xFU asyn_data_setuptime: 0x01U~0xFFU asyn_address_holdtime: 0x1U~0xFU asyn_address_setuptime: 0x0U~0xFU @@ -207,60 +202,62 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 - bus_latency: 0x0U~0xFU + bus_latency: 0x0U~0xFU asyn_data_setuptime: 0x01U~0xFFU asyn_address_holdtime: 0x1U~0xFU asyn_address_setuptime: 0x0U~0xFU \param[out] none \retval none */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { - uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; /* get the register value */ snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRMUX )); + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WEN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWTEN | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX)); + /* configure control bits */ snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + /* configure timing */ sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* enable nor flash access */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { snctl |= (uint32_t)EXMC_SNCTL_NREN; } - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ + /* configure extended mode */ + if(ENABLE == exmc_norsram_init_struct->extended_mode) { snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET )| - (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode; - }else{ + (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + } else { snwtcfg = BANK0_SNWTCFG_RESET; } @@ -271,8 +268,8 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) } /*! - \brief enable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \brief enable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none @@ -284,8 +281,8 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region) } /*! - \brief disable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + \brief disable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none @@ -297,7 +294,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region) } /*! - \brief deinitialize EXMC NAND bank + \brief deinitialize EXMC NAND bank \param[in] exmc_nand_bank: select the bank of NAND only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1..2) @@ -314,12 +311,12 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) } /*! - \brief initialize exmc_norsram_parameter_struct with the default values + \brief initialize exmc_norsram_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_norsram_parameter_struct pointer \retval none */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct) { /* configure the structure with default values */ exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; @@ -340,7 +337,7 @@ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struc } /*! - \brief initialize EXMC NAND bank + \brief initialize EXMC NAND bank \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 @@ -362,37 +359,37 @@ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struc \param[out] none \retval none */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) { uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; - - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) | + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; } /*! - \brief enable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank + \brief enable NAND bank + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none @@ -404,8 +401,8 @@ void exmc_nand_enable(uint32_t exmc_nand_bank) } /*! - \brief disable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank + \brief disable NAND bank + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none @@ -417,7 +414,7 @@ void exmc_nand_disable(uint32_t exmc_nand_bank) } /*! - \brief deinitialize EXMC PC card bank + \brief deinitialize EXMC PC card bank \param[in] none \param[out] none \retval none @@ -433,12 +430,12 @@ void exmc_pccard_deinit(void) } /*! - \brief initialize exmc_pccard_parameter_struct with the default values + \brief initialize exmc_pccard_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none */ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) { /* configure the structure with default values */ exmc_pccard_init_struct->wait_feature = DISABLE; @@ -459,7 +456,7 @@ void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init } /*! - \brief initialize EXMC PC card bank + \brief initialize EXMC PC card bank \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 @@ -482,35 +479,35 @@ void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init \param[out] none \retval none */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) { /* configure the EXMC bank3 PC card control register */ EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD ) | - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ); } /*! - \brief enable PC Card Bank + \brief enable PC Card Bank \param[in] none \param[out] none \retval none @@ -521,18 +518,18 @@ void exmc_pccard_enable(void) } /*! - \brief disable PC Card Bank + \brief disable PC Card Bank \param[in] none \param[out] none \retval none */ void exmc_pccard_disable(void) { - EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; } /*! - \brief deinitialize EXMC SDRAM device + \brief deinitialize EXMC SDRAM device \param[in] exmc_sdram_device: select the SRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0, 1) @@ -551,12 +548,12 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) } /*! - \brief initialize exmc_sdram_parameter_struct with the default values + \brief initialize exmc_sdram_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none */ -void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) { /* configure the structure with default values */ exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; @@ -567,7 +564,7 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; exmc_sdram_init_struct->write_protection = ENABLE; exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; - exmc_sdram_init_struct->brust_read_switch = DISABLE; + exmc_sdram_init_struct->burst_read_switch = DISABLE; exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; @@ -580,11 +577,11 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st } /*! - \brief initialize EXMC SDRAM device + \brief initialize EXMC SDRAM device \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 - brust_read_switch: ENABLE or DISABLE + burst_read_switch: ENABLE or DISABLE sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK write_protection: ENABLE or DISABLE cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 @@ -603,62 +600,62 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st \param[out] none \retval none */ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) { uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device){ - /* configuration EXMC_SDCTL0 */ - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| - exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| - exmc_sdram_init_struct->pipeline_read_delay; + /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { + /* configure EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); - /* configuration EXMC_SDTCFG0 */ - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - }else{ - /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* configure EXMC_SDTCFG0 */ + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); + } else { + /* configure EXMC_SDCTL0 and EXMC_SDCTL1 */ /* some bits in the EXMC_SDCTL1 register are reserved */ - sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); - - sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | - exmc_sdram_init_struct->pipeline_read_delay; + sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK)); + + sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); - sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - exmc_sdram_init_struct->write_protection ; + sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)); EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - - /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ + + /* configure EXMC_SDTCFG0 and EXMC_SDTCFG1 */ /* some bits in the EXMC_SDTCFG1 register are reserved */ sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); - sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET); + sdtcfg0 |= (uint32_t)((((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET)); - sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); + sdtcfg1 = (uint32_t)(((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET)); EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; @@ -666,7 +663,22 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) } /*! - \brief deinitialize exmc SQPIPSRAM + \brief initialize exmc_sdram_struct_command_para_init with the default values + \param[in] none + \param[out] the initialized struct exmc_sdram_struct_command_para_init pointer + \retval none +*/ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure the structure with default value */ + exmc_sdram_command_init_struct->mode_register_content = 0U; + exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; + exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT; + exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION; +} + +/*! + \brief deinitialize exmc SQPIPSRAM \param[in] none \param[out] none \retval none @@ -682,12 +694,12 @@ void exmc_sqpipsram_deinit(void) } /*! - \brief initialize exmc_sqpipsram_parameter_struct with the default values + \brief initialize exmc_sqpipsram_parameter_struct with the default values \param[in] the struct exmc_sqpipsram_parameter_struct pointer \param[out] none \retval none */ -void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) { /* configure the structure with default values */ exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; @@ -697,7 +709,7 @@ void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpip } /*! - \brief initialize EXMC SQPIPSRAM + \brief initialize EXMC SQPIPSRAM \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 @@ -706,18 +718,18 @@ void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpip \param[out] none \retval none */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) { /* initialize SQPI controller */ EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | - exmc_sqpipsram_init_struct->id_length | - exmc_sqpipsram_init_struct->address_bits | - exmc_sqpipsram_init_struct->command_bits; + exmc_sqpipsram_init_struct->id_length | + exmc_sqpipsram_init_struct->address_bits | + exmc_sqpipsram_init_struct->command_bits; } /*! - \brief configure consecutive clock - \param[in] clock_mode: specifie when the clock is generated + \brief configure consecutive clock + \param[in] clock_mode: specify when the clock is generated only one parameter can be selected which is shown as below: \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally @@ -726,15 +738,15 @@ void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_st */ void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) { - if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ + if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode) { EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; - }else{ + } else { EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; } } /*! - \brief configure CRAM page size + \brief configure CRAM page size \param[in] exmc_norsram_region: select the region of bank0 only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) @@ -758,8 +770,8 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s } /*! - \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[in] newvalue: ENABLE or DISABLE @@ -768,18 +780,18 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s */ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { /* enable the selected NAND bank ECC function */ EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ + } else { /* disable the selected NAND bank ECC function */ EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; } } /*! - \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none @@ -791,22 +803,22 @@ uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) } /*! - \brief enable or disable read sample + \brief enable or disable read sample \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void exmc_sdram_readsample_enable(ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; - }else{ + } else { EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); } } /*! - \brief configure the delayed sample clock of read data + \brief configure the delayed sample clock of read data \param[in] delay_cell: SDRAM the delayed sample clock of read data only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) @@ -819,38 +831,37 @@ void exmc_sdram_readsample_enable(ControlStatus newvalue) void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) { uint32_t sdrsctl = 0U; - + /* reset the bits */ sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); /* set the bits */ - sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | - ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); + sdrsctl |= (uint32_t)(delay_cell | extra_hclk); EXMC_SDRSCTL = sdrsctl; } /*! - \brief configure the SDRAM memory command - \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command + \brief configure the SDRAM memory command + \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command mode_register_content: auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 - bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT - command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, - EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, - EXMC_SDRAM_POWERDOWN_ENTRY + bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT + command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY \param[out] none \retval none */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) { /* configure command register */ EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | - (exmc_sdram_command_init_struct->bank_select) | - ((exmc_sdram_command_init_struct->auto_refresh_number)) | - ((exmc_sdram_command_init_struct->mode_register_content)<bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content) << SDCMD_MRC_OFFSET)); } /*! - \brief set auto-refresh interval + \brief set auto-refresh interval \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands, 0x0000~0x1FFF \param[out] none \retval none @@ -863,7 +874,7 @@ void exmc_sdram_refresh_count_set(uint32_t exmc_count) } /*! - \brief set the number of successive auto-refresh command + \brief set the number of successive auto-refresh command \param[in] exmc_number: the number of successive Auto-refresh cycles will be send, 1~15 \param[out] none \retval none @@ -876,8 +887,8 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) } /*! - \brief config the write protection function - \param[in] exmc_sdram_device: specifie the SDRAM device + \brief configure the write protection function + \param[in] exmc_sdram_device: specify the SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) \param[in] newvalue: ENABLE or DISABLE @@ -886,17 +897,17 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; - }else{ + } else { EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); } } /*! - \brief get the status of SDRAM device0 or device1 - \param[in] exmc_sdram_device: specifie the SDRAM device + \brief get the status of SDRAM device0 or device1 + \param[in] exmc_sdram_device: specify the SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) \param[out] none @@ -906,9 +917,9 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) { uint32_t sdstat = 0U; - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device){ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) { sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); - }else{ + } else { sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); } @@ -916,7 +927,7 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) } /*! - \brief set the read command + \brief set the read command \param[in] read_command_mode: configure SPI PSRAM read command mode only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode @@ -928,18 +939,18 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) \param[out] none \retval none */ -void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle, uint32_t read_command_code) +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code) { uint32_t srcmd; - + srcmd = (uint32_t) read_command_mode | - ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | - ((read_command_code & EXMC_SRCMD_RCMD)); + ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | + ((read_command_code & EXMC_SRCMD_RCMD)); EXMC_SRCMD = srcmd; } /*! - \brief set the write command + \brief set the write command \param[in] write_command_mode: configure SPI PSRAM write command mode only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode @@ -951,18 +962,18 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wa \param[out] none \retval none */ -void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle, uint32_t write_command_code) +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t write_wait_cycle, uint32_t write_command_code) { uint32_t swcmd; - + swcmd = (uint32_t) write_command_mode | - ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | - ((write_command_code & EXMC_SWCMD_WCMD)); + ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | + ((write_command_code & EXMC_SWCMD_WCMD)); EXMC_SWCMD = swcmd; } /*! - \brief send SPI read ID command + \brief send SPI read ID command \param[in] none \param[out] none \retval none @@ -973,7 +984,7 @@ void exmc_sqpipsram_read_id_command_send(void) } /*! - \brief send SPI special command which does not have address and data phase + \brief send SPI special command which does not have address and data phase \param[in] none \param[out] none \retval none @@ -984,7 +995,7 @@ void exmc_sqpipsram_write_cmd_send(void) } /*! - \brief get the EXMC SPI ID low data + \brief get the EXMC SPI ID low data \param[in] none \param[out] none \retval the ID low data @@ -995,7 +1006,7 @@ uint32_t exmc_sqpipsram_low_id_get(void) } /*! - \brief get the EXMC SPI ID high data + \brief get the EXMC SPI ID high data \param[in] none \param[out] none \retval the ID high data @@ -1006,7 +1017,7 @@ uint32_t exmc_sqpipsram_high_id_get(void) } /*! - \brief get the bit value of EXMC send write command bit or read ID command + \brief get the bit value of EXMC send write command bit or read ID command \param[in] send_command_flag: the send command flag only one parameter can be selected which is shown as below: \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit @@ -1017,33 +1028,33 @@ uint32_t exmc_sqpipsram_high_id_get(void) FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) { uint32_t flag = 0x00000000U; - - if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag){ + + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag) { flag = EXMC_SRCMD; - }else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag){ + } else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag) { flag = EXMC_SWCMD; - }else{ + } else { } - - if (flag & send_command_flag){ + + if(flag & send_command_flag) { /* flag is set */ return SET; - }else{ + } else { /* flag is reset */ return RESET; } } /*! - \brief enable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device + \brief enable EXMC interrupt + \param[in] exmc_bank: specify the NAND bank,PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: specify get which interrupt flag + \param[in] interrupt: specify EXMC interrupt flag only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag @@ -1054,25 +1065,25 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) */ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) |= interrupt; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDARI |= EXMC_SDARI_REIE; } } /*! - \brief disable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \brief disable EXMC interrupt + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: specify get which interrupt flag + \param[in] interrupt: specify EXMC interrupt flag only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag @@ -1083,18 +1094,18 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) */ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) &= ~interrupt; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDARI &= ~EXMC_SDARI_REIE; } } /*! - \brief get EXMC flag status - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \brief get EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1112,30 +1123,30 @@ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) +FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag) { uint32_t status = 0x00000000U; - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); - }else{ - /* SDRAM device0 or device1 */ + } else { + /* SDRAM device0 or device1 */ status = EXMC_SDSTAT; } - - if ((status & flag) != (uint32_t)flag ){ + + if((status & flag) != (uint32_t)flag) { /* flag is reset */ return RESET; - }else{ + } else { /* flag is set */ return SET; } } /*! - \brief clear EXMC flag status - \param[in] exmc_bank: specifie the NAND bank , PCCARD bank or SDRAM device + \brief clear EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1155,18 +1166,18 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) */ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) &= ~flag; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDSTAT &= ~flag; - } + } } /*! - \brief get EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \brief get EXMC interrupt flag + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1184,32 +1195,32 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) */ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) { - uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; + uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); - }else{ - /* SDRAM device0 or device1 */ + } else { + /* SDRAM device0 or device1 */ status = EXMC_SDARI; interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); } interrupt_enable = (status & interrupt); - if ((interrupt_enable) && (interrupt_state)){ + if((interrupt_enable) && (interrupt_state)) { /* interrupt flag is set */ return SET; - }else{ + } else { /* interrupt flag is reset */ return RESET; } } /*! - \brief clear EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \brief clear EXMC interrupt flag + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1227,10 +1238,10 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) */ void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDARI |= EXMC_SDARI_REC; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c index a37e7cd..3be3003 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c @@ -1,41 +1,40 @@ /*! \file gd32f4xx_exti.c \brief EXTI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_exti.h" +#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) + /*! \brief deinitialize the EXTI \param[in] none @@ -45,15 +44,15 @@ OF SUCH DAMAGE. void exti_deinit(void) { /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x00000000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; + EXTI_INTEN = EXTI_REG_RESET_VALUE; + EXTI_EVEN = EXTI_REG_RESET_VALUE; + EXTI_RTEN = EXTI_REG_RESET_VALUE; + EXTI_FTEN = EXTI_REG_RESET_VALUE; + EXTI_SWIEV = EXTI_REG_RESET_VALUE; } /*! - \brief initialize the EXTI + \brief initialize the EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -71,17 +70,17 @@ void exti_deinit(void) \retval none */ void exti_init(exti_line_enum linex, \ - exti_mode_enum mode, \ - exti_trig_type_enum trig_type) + exti_mode_enum mode, \ + exti_trig_type_enum trig_type) { /* reset the EXTI line x */ EXTI_INTEN &= ~(uint32_t)linex; EXTI_EVEN &= ~(uint32_t)linex; EXTI_RTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; - + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ + switch(mode) { case EXTI_INTERRUPT: EXTI_INTEN |= (uint32_t)linex; break; @@ -91,9 +90,9 @@ void exti_init(exti_line_enum linex, \ default: break; } - + /* set the EXTI trigger type */ - switch(trig_type){ + switch(trig_type) { case EXTI_TRIG_RISING: EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; @@ -165,7 +164,7 @@ void exti_event_disable(exti_line_enum linex) } /*! - \brief enable EXTI software interrupt event + \brief enable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -178,7 +177,7 @@ void exti_software_interrupt_enable(exti_line_enum linex) } /*! - \brief disable EXTI software interrupt event + \brief disable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -191,7 +190,7 @@ void exti_software_interrupt_disable(exti_line_enum linex) } /*! - \brief get EXTI lines flag + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -200,15 +199,15 @@ void exti_software_interrupt_disable(exti_line_enum linex) */ FlagStatus exti_flag_get(exti_line_enum linex) { - if(RESET != (EXTI_PD & (uint32_t)linex)){ + if(RESET != (EXTI_PD & (uint32_t)linex)) { return SET; - }else{ + } else { return RESET; - } + } } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -221,7 +220,7 @@ void exti_flag_clear(exti_line_enum linex) } /*! - \brief get EXTI lines flag when the interrupt flag is set + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -230,20 +229,15 @@ void exti_flag_clear(exti_line_enum linex) */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ + if(RESET != (EXTI_PD & (uint32_t)linex)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -254,4 +248,3 @@ void exti_interrupt_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; } - diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c index b5cd2fa..68d6b92 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c @@ -2,35 +2,33 @@ \file gd32f4xx_fmc.c \brief FMC driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -38,7 +36,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_fmc.h" /*! - \brief set the wait state counter value + \brief set the FMC wait state counter \param[in] wscnt: wait state counter value only one parameter can be selected which is shown as below: \arg WS_WSCNT_0: FMC 0 wait @@ -63,7 +61,7 @@ OF SUCH DAMAGE. void fmc_wscnt_set(uint32_t wscnt) { uint32_t reg; - + reg = FMC_WS; /* set the wait state counter value */ reg &= ~FMC_WC_WSCNT; @@ -78,7 +76,7 @@ void fmc_wscnt_set(uint32_t wscnt) */ void fmc_unlock(void) { - if((RESET != (FMC_CTL & FMC_CTL_LK))){ + if((RESET != (FMC_CTL & FMC_CTL_LK))) { /* write the FMC key */ FMC_KEY = UNLOCK_KEY0; FMC_KEY = UNLOCK_KEY1; @@ -97,38 +95,84 @@ void fmc_lock(void) FMC_CTL |= FMC_CTL_LK; } +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) + +/*! + \brief FMC erase page + \param[in] page_addr: the page address to be erased. + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_page_erase(uint32_t page_addr) +{ + fmc_state_enum fmc_state = FMC_READY; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* unlock page erase operation */ + FMC_PEKEY = UNLOCK_PE_KEY; + + /* start page erase */ + FMC_PECFG = FMC_PE_EN | page_addr; + FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL |= FMC_CTL_SER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + FMC_PECFG &= ~FMC_PE_EN; + FMC_CTL &= ~FMC_CTL_SER; + } + + /* return the FMC state */ + return fmc_state; +} + +#endif + /*! - \brief erase sector + \brief FMC erase sector \param[in] fmc_sector: select the sector to erase only one parameter can be selected which is shown as below: - \arg CTL_SECTOR_NUMBER_0: sector 0 - \arg CTL_SECTOR_NUMBER_1: sector 1 - \arg CTL_SECTOR_NUMBER_2: sector 2 - \arg CTL_SECTOR_NUMBER_3: sector 3 - \arg CTL_SECTOR_NUMBER_4: sector 4 - \arg CTL_SECTOR_NUMBER_5: sector 5 - \arg CTL_SECTOR_NUMBER_6: sector 6 - \arg CTL_SECTOR_NUMBER_7: sector 7 - \arg CTL_SECTOR_NUMBER_8: sector 8 - \arg CTL_SECTOR_NUMBER_9: sector 9 - \arg CTL_SECTOR_NUMBER_10: sector 10 - \arg CTL_SECTOR_NUMBER_11: sector 11 - \arg CTL_SECTOR_NUMBER_12: sector 12 - \arg CTL_SECTOR_NUMBER_13: sector 13 - \arg CTL_SECTOR_NUMBER_14: sector 14 - \arg CTL_SECTOR_NUMBER_15: sector 15 - \arg CTL_SECTOR_NUMBER_16: sector 16 - \arg CTL_SECTOR_NUMBER_17: sector 17 - \arg CTL_SECTOR_NUMBER_18: sector 18 - \arg CTL_SECTOR_NUMBER_19: sector 19 - \arg CTL_SECTOR_NUMBER_20: sector 20 - \arg CTL_SECTOR_NUMBER_21: sector 21 - \arg CTL_SECTOR_NUMBER_22: sector 22 - \arg CTL_SECTOR_NUMBER_23: sector 23 - \arg CTL_SECTOR_NUMBER_24: sector 24 - \arg CTL_SECTOR_NUMBER_25: sector 25 - \arg CTL_SECTOR_NUMBER_26: sector 26 - \arg CTL_SECTOR_NUMBER_27: sector 27 + \arg CTL_SECTOR_NUMBER_0: sector 0 + \arg CTL_SECTOR_NUMBER_1: sector 1 + \arg CTL_SECTOR_NUMBER_2: sector 2 + \arg CTL_SECTOR_NUMBER_3: sector 3 + \arg CTL_SECTOR_NUMBER_4: sector 4 + \arg CTL_SECTOR_NUMBER_5: sector 5 + \arg CTL_SECTOR_NUMBER_6: sector 6 + \arg CTL_SECTOR_NUMBER_7: sector 7 + \arg CTL_SECTOR_NUMBER_8: sector 8 + \arg CTL_SECTOR_NUMBER_9: sector 9 + \arg CTL_SECTOR_NUMBER_10: sector 10 + \arg CTL_SECTOR_NUMBER_11: sector 11 + \arg CTL_SECTOR_NUMBER_12: sector 12 + \arg CTL_SECTOR_NUMBER_13: sector 13 + \arg CTL_SECTOR_NUMBER_14: sector 14 + \arg CTL_SECTOR_NUMBER_15: sector 15 + \arg CTL_SECTOR_NUMBER_16: sector 16 + \arg CTL_SECTOR_NUMBER_17: sector 17 + \arg CTL_SECTOR_NUMBER_18: sector 18 + \arg CTL_SECTOR_NUMBER_19: sector 19 + \arg CTL_SECTOR_NUMBER_20: sector 20 + \arg CTL_SECTOR_NUMBER_21: sector 21 + \arg CTL_SECTOR_NUMBER_22: sector 22 + \arg CTL_SECTOR_NUMBER_23: sector 23 + \arg CTL_SECTOR_NUMBER_24: sector 24 + \arg CTL_SECTOR_NUMBER_25: sector 25 + \arg CTL_SECTOR_NUMBER_26: sector 26 + \arg CTL_SECTOR_NUMBER_27: sector 27 \param[out] none \retval state of FMC \arg FMC_READY: the operation has been completed @@ -138,7 +182,6 @@ void fmc_lock(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) @@ -147,7 +190,7 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start sector erase */ FMC_CTL &= ~FMC_CTL_SN; FMC_CTL |= (FMC_CTL_SER | fmc_sector); @@ -166,7 +209,7 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) } /*! - \brief erase whole chip + \brief FMC erase whole chip \param[in] none \param[out] none \retval state of FMC @@ -177,7 +220,6 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_mass_erase(void) @@ -186,7 +228,7 @@ fmc_state_enum fmc_mass_erase(void) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start whole chip erase */ FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); FMC_CTL |= FMC_CTL_START; @@ -203,7 +245,7 @@ fmc_state_enum fmc_mass_erase(void) } /*! - \brief erase all FMC sectors in bank0 + \brief FMC erase whole bank0 \param[in] none \param[out] none \retval state of FMC @@ -214,7 +256,6 @@ fmc_state_enum fmc_mass_erase(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_bank0_erase(void) @@ -223,7 +264,7 @@ fmc_state_enum fmc_bank0_erase(void) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start FMC bank0 erase */ FMC_CTL |= FMC_CTL_MER0; FMC_CTL |= FMC_CTL_START; @@ -240,7 +281,7 @@ fmc_state_enum fmc_bank0_erase(void) } /*! - \brief erase all FMC sectors in bank1 + \brief FMC erase whole bank1 \param[in] none \param[out] none \retval state of FMC @@ -251,7 +292,6 @@ fmc_state_enum fmc_bank0_erase(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_bank1_erase(void) @@ -260,7 +300,7 @@ fmc_state_enum fmc_bank1_erase(void) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start FMC bank1 erase */ FMC_CTL |= FMC_CTL_MER1; FMC_CTL |= FMC_CTL_START; @@ -289,7 +329,6 @@ fmc_state_enum fmc_bank1_erase(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) @@ -298,11 +337,11 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_WORD; - FMC_CTL |= FMC_CTL_PG; + FMC_CTL |= FMC_CTL_PG; REG32(address) = data; @@ -330,7 +369,6 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) @@ -339,7 +377,7 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_HALF_WORD; @@ -371,7 +409,6 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) @@ -379,8 +416,8 @@ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_BYTE; @@ -407,7 +444,7 @@ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) */ void ob_unlock(void) { - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)){ + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)) { /* write the FMC key */ FMC_OBKEY = OB_UNLOCK_KEY0; FMC_OBKEY = OB_UNLOCK_KEY1; @@ -434,14 +471,8 @@ void ob_lock(void) */ void ob_start(void) { - fmc_state_enum fmc_state = FMC_READY; /* set the OB_START bit in OBCTL0 register */ FMC_OBCTL0 |= FMC_OBCTL0_OB_START; - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY != fmc_state){ - while(1){ - } - } } /*! @@ -456,10 +487,10 @@ void ob_erase(void) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + reg = FMC_OBCTL0; + reg1 = FMC_OBCTL1; - if(FMC_READY == fmc_state){ - reg = FMC_OBCTL0; - reg1 = FMC_OBCTL1; + if(FMC_READY == fmc_state) { /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); @@ -490,25 +521,28 @@ void ob_erase(void) \arg OB_WP_23_27: sector23~27 \arg OB_WP_ALL: all sector \param[out] none - \retval none + \retval SUCCESS or ERROR */ -void ob_write_protection_enable(uint32_t ob_wp) +ErrStatus ob_write_protection_enable(uint32_t ob_wp) { uint32_t reg0 = FMC_OBCTL0; uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ - while(1){ - } + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; } /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - reg0 &= (~((uint32_t)ob_wp << 16)); + if(FMC_READY == fmc_state) { + reg0 &= (~((uint32_t)ob_wp << 16U)); reg1 &= (~(ob_wp & 0xFFFF0000U)); FMC_OBCTL0 = reg0; FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; } } @@ -520,31 +554,34 @@ void ob_write_protection_enable(uint32_t ob_wp) \arg OB_WP_23_27: sector23~27 \arg OB_WP_ALL: all sector \param[out] none - \retval none + \retval SUCCESS or ERROR */ -void ob_write_protection_disable(uint32_t ob_wp) +ErrStatus ob_write_protection_disable(uint32_t ob_wp) { uint32_t reg0 = FMC_OBCTL0; uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ - while(1){ - } + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; } /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - reg0 |= ((uint32_t)ob_wp << 16); + if(FMC_READY == fmc_state) { + reg0 |= ((uint32_t)ob_wp << 16U); reg1 |= (ob_wp & 0xFFFF0000U); FMC_OBCTL0 = reg0; FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; } } /*! \brief enable erase/program protection and D-bus read protection - \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector + \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector one or more parameters can be selected which are shown as below: \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) \arg OB_DRP_23_27: sector23~27 @@ -558,38 +595,31 @@ void ob_drp_enable(uint32_t ob_drp) uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; - uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; - uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; - /*disable write protection before enable D-bus read protection*/ - if((RESET != drp_state) && ((FMC_OBCTL0_WP0 != wp0_state) && (FMC_OBCTL1_WP1 != wp1_state))){ - while(1){ - } - } + /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - reg0 &= ~FMC_OBCTL0_WP0; - reg1 &= ~FMC_OBCTL1_WP1; - reg0 |= ((uint32_t)ob_drp << 16); + if(FMC_READY == fmc_state) { + if(RESET == drp_state) { + reg0 &= ~FMC_OBCTL0_WP0; + reg1 &= ~FMC_OBCTL1_WP1; + } + reg0 |= ((uint32_t)ob_drp << 16U); + reg0 |= FMC_OBCTL0_DRP; reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; FMC_OBCTL1 = reg1; - FMC_OBCTL0 |= FMC_OBCTL0_DRP; } } /*! \brief disable erase/program protection and D-bus read protection - \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - one or more parameters can be selected which are shown as below: - \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) - \arg OB_DRP_23_27: sector23~27 - \arg OB_DRP_ALL: all sector + \param[in] none \param[out] none \retval none */ -void ob_drp_disable(uint32_t ob_drp) +void ob_drp_disable(void) { uint32_t reg0 = FMC_OBCTL0; uint32_t reg1 = FMC_OBCTL1; @@ -597,27 +627,26 @@ void ob_drp_disable(uint32_t ob_drp) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - if(((uint8_t)(reg0 >> 8)) == (uint8_t)FMC_NSPC){ + if(FMC_READY == fmc_state) { + if(((uint8_t)(reg0 >> 8U)) == (uint8_t)FMC_NSPC) { /* security protection should be set as low level protection before disable D-BUS read protection */ reg0 &= ~FMC_OBCTL0_SPC; - reg0 |= ((uint32_t)FMC_LSPC << 8); + reg0 |= ((uint32_t)FMC_LSPC << 8U); FMC_OBCTL0 = reg0; - ob_start(); - while(FMC_READY != fmc_ready_wait(FMC_TIMEOUT_COUNT)); - }else if(((uint8_t)(reg0 >> 8)) == (uint8_t)FMC_HSPC){ - return; + /* set the OB_START bit in OBCTL0 register */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_START; } /* it is necessary to disable the security protection at the same time when D-BUS read protection is disabled */ reg0 &= ~FMC_OBCTL0_SPC; - reg0 |= ((uint32_t)FMC_NSPC << 8); + reg0 |= ((uint32_t)FMC_NSPC << 8U); reg0 |= FMC_OBCTL0_WP0; reg0 &= (~FMC_OBCTL0_DRP); FMC_OBCTL0 = reg0; reg1 |= FMC_OBCTL1_WP1; FMC_OBCTL1 = reg1; + } } @@ -637,19 +666,19 @@ void ob_security_protection_config(uint8_t ob_spc) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { uint32_t reg; reg = FMC_OBCTL0; /* reset the OBCTL0_SPC, set according to ob_spc */ reg &= ~FMC_OBCTL0_SPC; - reg |= ((uint32_t)ob_spc << 8); + reg |= ((uint32_t)ob_spc << 8U); FMC_OBCTL0 = reg; } } /*! - \brief program the FMC user option byte + \brief program the FMC user option byte \param[in] ob_fwdgt: option byte watchdog value only one parameter can be selected which is shown as below: \arg OB_FWDGT_SW: software free watchdog @@ -657,11 +686,11 @@ void ob_security_protection_config(uint8_t ob_spc) \param[in] ob_deepsleep: option byte deepsleep reset value only one parameter can be selected which is shown as below: \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode \param[in] ob_stdby:option byte standby reset value only one parameter can be selected which is shown as below: \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode \param[out] none \retval none */ @@ -672,7 +701,7 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { uint32_t reg; reg = FMC_OBCTL0; @@ -696,7 +725,7 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) void ob_user_bor_threshold(uint32_t ob_bor_th) { uint32_t reg; - + reg = FMC_OBCTL0; /* set the BOR level */ reg &= ~FMC_OBCTL0_BOR_TH; @@ -715,13 +744,34 @@ void ob_user_bor_threshold(uint32_t ob_bor_th) void ob_boot_mode_config(uint32_t boot_mode) { uint32_t reg; - + reg = FMC_OBCTL0; /* set option byte boot bank value */ reg &= ~FMC_OBCTL0_BB; FMC_OBCTL0 = (reg | boot_mode); } +#if defined (GD32F450) || defined (GD32F470) +/*! + \brief configure the option byte double bank select, only for 1MB flash memory series + \param[in] double_bank: specifies the option byte double bank select + only one parameter can be selected which is shown as below: + \arg OB_DBS_DISABLE: single bank when flash size is 1M bytes + \arg OB_DBS_ENABLE: double banks when flash size is 1M bytes + \param[out] none + \retval none +*/ +void ob_double_bank_select(uint32_t double_bank) +{ + uint32_t reg; + + reg = FMC_OBCTL0; + /* set option byte double bank select */ + reg &= ~FMC_OBCTL0_DBS; + FMC_OBCTL0 = (reg | double_bank); +} +#endif + /*! \brief get the FMC user option byte \param[in] none @@ -730,7 +780,7 @@ void ob_boot_mode_config(uint32_t boot_mode) */ uint8_t ob_user_get(void) { - return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5) & (uint8_t)0x07); + return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5U) & 0x07U); } /*! @@ -742,7 +792,7 @@ uint8_t ob_user_get(void) uint16_t ob_write_protection0_get(void) { /* return the FMC write protection option byte value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF); + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); } /*! @@ -754,11 +804,11 @@ uint16_t ob_write_protection0_get(void) uint16_t ob_write_protection1_get(void) { /* return the the FMC write protection option byte value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF); + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); } /*! - \brief get the FMC D-bus read protection protection + \brief get the FMC erase/program protection and D-bus read protection option bytes value \param[in] none \param[out] none \retval the FMC erase/program protection and D-bus read protection option bytes value @@ -766,11 +816,15 @@ uint16_t ob_write_protection1_get(void) uint16_t ob_drp0_get(void) { /* return the FMC erase/program protection and D-bus read protection option bytes value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF); + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } } /*! - \brief get the FMC D-bus read protection protection + \brief get the FMC erase/program protection and D-bus read protection option bytes value \param[in] none \param[out] none \retval the FMC erase/program protection and D-bus read protection option bytes value @@ -778,11 +832,15 @@ uint16_t ob_drp0_get(void) uint16_t ob_drp1_get(void) { /* return the FMC erase/program protection and D-bus read protection option bytes value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF); + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } } /*! - \brief get the FMC option byte security protection + \brief get option byte security protection code value \param[in] none \param[out] none \retval FlagStatus: SET or RESET @@ -790,10 +848,10 @@ uint16_t ob_drp1_get(void) FlagStatus ob_spc_get(void) { FlagStatus spc_state = RESET; - - if (((uint8_t)(FMC_OBCTL0 >> 8)) != (uint8_t)FMC_NSPC){ + + if(((uint8_t)(FMC_OBCTL0 >> 8U)) != FMC_NSPC) { spc_state = SET; - }else{ + } else { spc_state = RESET; } return spc_state; @@ -808,7 +866,49 @@ FlagStatus ob_spc_get(void) uint8_t ob_user_bor_threshold_get(void) { /* return the FMC BOR threshold value */ - return (uint8_t)((uint8_t)FMC_OBCTL0 & (uint8_t)0x0C); + return (uint8_t)((uint8_t)FMC_OBCTL0 & 0x0CU); +} + +/*! + \brief get flag set or reset + \param[in] fmc_flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag bit + \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit + \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit + \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit + \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t fmc_flag) +{ + if(FMC_STAT & fmc_flag) { + return SET; + } + /* return the state of corresponding FMC flag */ + return RESET; +} + +/*! + \brief clear the FMC pending flag + \param[in] FMC_flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit + \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit + \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit + \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t fmc_flag) +{ + /* clear the flags */ + FMC_STAT = fmc_flag; } /*! @@ -840,45 +940,56 @@ void fmc_interrupt_disable(uint32_t fmc_int) } /*! - \brief get flag set or reset - \param[in] fmc_flag: check FMC flag + \brief get FMC interrupt flag set or reset + \param[in] fmc_int_flag: FMC interrupt flag only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag bit - \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit - \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit - \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit - \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus fmc_flag_get(uint32_t fmc_flag) +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag) { - if(FMC_STAT & fmc_flag){ - return SET; + if(FMC_FLAG_END == fmc_int_flag) { + /* end of operation interrupt flag */ + if(FMC_CTL & FMC_CTL_ENDIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } else { + /* error interrupt flags */ + if(FMC_CTL & FMC_CTL_ERRIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } } - /* return the state of corresponding FMC flag */ - return RESET; + + return RESET; } /*! - \brief clear the FMC pending flag - \param[in] FMC_flag: clear FMC flag + \brief clear the FMC interrupt flag + \param[in] fmc_int_flag: FMC interrupt flag only one parameter can be selected which is shown as below: - \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit - \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit - \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag \param[out] none \retval none */ -void fmc_flag_clear(uint32_t fmc_flag) +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag) { - /* clear the flags */ - FMC_STAT = fmc_flag; + /* clear the interrupt flag */ + FMC_STAT = fmc_int_flag; } /*! @@ -893,33 +1004,28 @@ void fmc_flag_clear(uint32_t fmc_flag) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error */ fmc_state_enum fmc_state_get(void) { fmc_state_enum fmc_state = FMC_READY; - - if((FMC_STAT & FMC_FLAG_BUSY) == FMC_FLAG_BUSY){ + uint32_t temp_val = FMC_STAT; + + if(RESET != (temp_val & FMC_FLAG_BUSY)) { fmc_state = FMC_BUSY; - }else{ - if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ - fmc_state = FMC_WPERR; - }else{ - if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ - fmc_state = FMC_RDDERR; - }else{ - if((FMC_STAT & (uint32_t)0xEF) != (uint32_t)0x00){ - fmc_state = FMC_PGERR; - }else{ - if((FMC_STAT & FMC_FLAG_OPERR) != (uint32_t)0x00){ - fmc_state = FMC_OPERR; - }else{ - fmc_state = FMC_READY; - } - } - } - } + } else if(RESET != (temp_val & FMC_FLAG_RDDERR)) { + fmc_state = FMC_RDDERR; + } else if(RESET != (temp_val & FMC_FLAG_PGSERR)) { + fmc_state = FMC_PGSERR; + } else if(RESET != (temp_val & FMC_FLAG_PGMERR)) { + fmc_state = FMC_PGMERR; + } else if(RESET != (temp_val & FMC_FLAG_WPERR)) { + fmc_state = FMC_WPERR; + } else if(RESET != (temp_val & FMC_FLAG_OPERR)) { + fmc_state = FMC_OPERR; + } else { + fmc_state = FMC_READY; } + /* return the FMC state */ return fmc_state; } @@ -936,7 +1042,6 @@ fmc_state_enum fmc_state_get(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_ready_wait(uint32_t timeout) @@ -944,15 +1049,16 @@ fmc_state_enum fmc_ready_wait(uint32_t timeout) fmc_state_enum fmc_state = FMC_BUSY; /* wait for FMC ready */ - do{ + do { /* get FMC state */ fmc_state = fmc_state_get(); timeout--; - }while((FMC_BUSY == fmc_state) && (0U != timeout)); + } while((FMC_BUSY == fmc_state) && (0U != timeout)); - if(FMC_BUSY == fmc_state){ + if(0U == timeout) { fmc_state = FMC_TOERR; } + /* return the FMC state */ return fmc_state; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c index 30fc5ef..27b479b 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c @@ -1,14 +1,12 @@ /*! \file gd32f4xx_fwdgt.c \brief FWDGT driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -36,11 +34,6 @@ OF SUCH DAMAGE. #include "gd32f4xx_fwdgt.h" -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - /*! \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none @@ -74,6 +67,71 @@ void fwdgt_enable(void) FWDGT_CTL = FWDGT_KEY_ENABLE; } +/*! + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + /*! \brief reload the counter of FWDGT \param[in] none diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c index 9f8fd84..1e641d0 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c @@ -1,44 +1,42 @@ /*! \file gd32f4xx_gpio.c \brief GPIO driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_gpio.h" /*! - \brief reset GPIO port - \param[in] gpio_periph: GPIO port + \brief reset GPIO port + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none @@ -46,7 +44,7 @@ OF SUCH DAMAGE. */ void gpio_deinit(uint32_t gpio_periph) { - switch(gpio_periph){ + switch(gpio_periph) { case GPIOA: /* reset GPIOA */ rcu_periph_reset_enable(RCU_GPIOARST); @@ -98,8 +96,8 @@ void gpio_deinit(uint32_t gpio_periph) } /*! - \brief set GPIO mode - \param[in] gpio_periph: GPIO port + \brief set GPIO mode + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] mode: GPIO pin mode @@ -125,8 +123,8 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u ctl = GPIO_CTL(gpio_periph); pupd = GPIO_PUD(gpio_periph); - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { /* clear the specified pin mode bits */ ctl &= ~GPIO_MODE_MASK(i); /* set the specified pin mode bits */ @@ -144,18 +142,18 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u } /*! - \brief set GPIO output type and speed - \param[in] gpio_periph: GPIO port + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] otype: GPIO pin output mode \arg GPIO_OTYPE_PP: push pull mode \arg GPIO_OTYPE_OD: open drain mode \param[in] speed: GPIO pin output max speed - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_25MHZ: output max speed 25MHz + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_25MHZ: output max speed 25MHz \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \arg GPIO_OSPEED_200MHZ: output max speed 200MHz + \arg GPIO_OSPEED_MAX: output max speed more than 50MHz \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -167,21 +165,21 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed uint16_t i; uint32_t ospeedr; - if(GPIO_OTYPE_OD == otype){ + if(GPIO_OTYPE_OD == otype) { GPIO_OMODE(gpio_periph) |= (uint32_t)pin; - }else{ + } else { GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); } /* get the specified pin output speed bits value */ ospeedr = GPIO_OSPD(gpio_periph); - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { /* clear the specified pin output speed bits */ ospeedr &= ~GPIO_OSPEED_MASK(i); /* set the specified pin output speed bits */ - ospeedr |= GPIO_OSPEED_SET(i,speed); + ospeedr |= GPIO_OSPEED_SET(i, speed); } } GPIO_OSPD(gpio_periph) = ospeedr; @@ -189,7 +187,7 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed /*! \brief set GPIO pin bit - \param[in] gpio_periph: GPIO port + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -204,8 +202,8 @@ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) } /*! - \brief reset GPIO pin bit - \param[in] gpio_periph: GPIO port + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -220,8 +218,8 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) } /*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIO port + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -235,16 +233,16 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) */ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) { - if(RESET != bit_value){ + if(RESET != bit_value) { GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ + } else { GPIO_BC(gpio_periph) = (uint32_t)pin; } } /*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIO port + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] data: specify the value to be written to the port output control register @@ -257,8 +255,8 @@ void gpio_port_write(uint32_t gpio_periph, uint16_t data) } /*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIO port + \brief get GPIO pin input status + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -269,16 +267,16 @@ void gpio_port_write(uint32_t gpio_periph, uint16_t data) */ FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) { - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { return RESET; } } /*! - \brief get GPIO all pins input status - \param[in] gpio_periph: GPIO port + \brief get GPIO all pins input status + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none @@ -290,8 +288,8 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph) } /*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIO port + \brief get GPIO pin output status + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -302,18 +300,18 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph) */ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) { - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief get GPIO all pins output status - \param[in] gpio_periph: GPIO port + \brief get GPIO port output status + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none \retval output status of GPIO all pins */ @@ -323,8 +321,8 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) } /*! - \brief set GPIO alternate function - \param[in] gpio_periph: GPIO port + \brief set GPIO alternate function + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] alt_func_num: GPIO pin af function @@ -334,10 +332,10 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 \arg GPIO_AF_4: I2C0, I2C1, I2C2 \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 - \arg GPIO_AF_6: SPI1, SPI2, SAI0, SPI3, SPI4 + \arg GPIO_AF_6: SPI2, SPI3, SPI4 \arg GPIO_AF_7: USART0, USART1, USART2, SPI1, SPI2 \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 - \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13 + \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13, I2C1, I2C2, CTC \arg GPIO_AF_10: USB_FS, USB_HS \arg GPIO_AF_11: ENET \arg GPIO_AF_12: EXMC, SDIO, USB_HS @@ -358,19 +356,19 @@ void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) afrl = GPIO_AFSEL0(gpio_periph); afrh = GPIO_AFSEL1(gpio_periph); - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { /* clear the specified pin alternate function bits */ afrl &= ~GPIO_AFR_MASK(i); - afrl |= GPIO_AFR_SET(i,alt_func_num); + afrl |= GPIO_AFR_SET(i, alt_func_num); } } - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { /* clear the specified pin alternate function bits */ afrh &= ~GPIO_AFR_MASK(i - 8U); - afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); } } @@ -379,8 +377,8 @@ void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) } /*! - \brief lock GPIO pin bit - \param[in] gpio_periph: GPIO port + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -403,8 +401,8 @@ void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) } /*! - \brief toggle GPIO pin status - \param[in] gpio_periph: GPIO port + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin @@ -419,8 +417,8 @@ void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) } /*! - \brief toggle GPIO port status - \param[in] gpio_periph: GPIO port + \brief toggle GPIO port status + \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c index c9de1db..0323cb7 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c @@ -2,60 +2,57 @@ \file gd32f4xx_i2c.c \brief I2C driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-04-16, V2.0.2, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_i2c.h" /* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x00000032U) /*!< i2cclk maximum value */ +#define I2CCLK_MAX ((uint32_t)0x0000003CU) /*!< i2cclk maximum value */ #define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ #define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ #define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ /* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ +#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ /*! - \brief reset I2C + \brief reset I2C \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_deinit(uint32_t i2c_periph) { - switch(i2c_periph){ + switch(i2c_periph) { case I2C0: /* reset I2C0 */ rcu_periph_reset_enable(RCU_I2C0RST); @@ -77,13 +74,13 @@ void i2c_deinit(uint32_t i2c_periph) } /*! - \brief configure I2C clock + \brief configure I2C clock \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) \param[in] dutycyc: duty cycle in fast mode only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode + \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode \param[out] none \retval none */ @@ -91,59 +88,61 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) { uint32_t pclk1, clkc, freq, risetime; uint32_t temp; - + pclk1 = rcu_clock_freq_get(CK_APB1); /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { freq = I2CCLK_MAX; } temp = I2C_CTL1(i2c_periph); temp &= ~I2C_CTL1_I2CCLK; temp |= freq; - + I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ + + if(100000U >= clkspeed) { /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { I2C_RT(i2c_periph) = I2CCLK_MAX; - }else{ + } else if(risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { I2C_RT(i2c_periph) = risetime; } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { /* the CLKC in standard mode minmum value is 4 */ clkc = 0x04U; } - + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - }else if(400000U >= clkspeed){ + } else if(400000U >= clkspeed) { /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ + } else { /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } - if(0U == (clkc & I2C_CKCFG_CLKC)){ + if(0U == (clkc & I2C_CKCFG_CLKC)) { /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; + clkc |= 0x0001U; } I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; - }else{ + } else { } } /*! - \brief configure I2C address + \brief configure I2C address \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] mode: only one parameter can be selected which is shown as below: @@ -151,8 +150,8 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) \arg I2C_SMBUSMODE_ENABLE: SMBus mode \param[in] addformat: 7bits or 10bits only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits + \arg I2C_ADDFORMAT_7BITS: address format is 7 bits + \arg I2C_ADDFORMAT_10BITS: address format is 10 bits \param[in] addr: I2C address \param[out] none \retval none @@ -161,9 +160,9 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat { /* SMBus/I2C mode selected */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); + ctl &= ~(I2C_CTL0_SMBEN); ctl |= mode; I2C_CTL0(i2c_periph) = ctl; /* configure address */ @@ -172,26 +171,26 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat } /*! - \brief SMBus type selection + \brief select SMBus type \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] type: only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host + \arg I2C_SMBUS_DEVICE: SMBus mode device type + \arg I2C_SMBUS_HOST: SMBus mode host type \param[out] none \retval none */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) { - if(I2C_SMBUS_HOST == type){ + if(I2C_SMBUS_HOST == type) { I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ + } else { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); } } /*! - \brief whether or not to send an ACK + \brief whether or not to send an ACK \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] ack: only one parameter can be selected which is shown as below: @@ -202,50 +201,51 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) { - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ACKEN); + ctl |= ack; + I2C_CTL0(i2c_periph) = ctl; } /*! - \brief configure I2C POAP position + \brief configure I2C POAP position \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pos: only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte + \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte \param[out] none \retval none */ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) { + uint32_t ctl = 0U; /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_POAP); + ctl |= pos; + I2C_CTL0(i2c_periph) = ctl; } /*! - \brief master sends slave address + \brief master sends slave address \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] addr: slave address + \param[in] addr: slave address \param[in] trandirection: transmitter or receiver only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver \param[out] none \retval none */ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) { /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ + if(I2C_TRANSMITTER == trandirection) { addr = addr & I2C_TRANSMITTER; - }else{ + } else { addr = addr | I2C_RECEIVER; } /* send slave address */ @@ -253,7 +253,7 @@ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandire } /*! - \brief enable dual-address mode + \brief enable dual-address mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] addr: the second address in dual-address mode \param[out] none @@ -267,8 +267,8 @@ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) } /*! - \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -278,8 +278,8 @@ void i2c_dualaddr_disable(uint32_t i2c_periph) } /*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -289,8 +289,8 @@ void i2c_enable(uint32_t i2c_periph) } /*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -300,7 +300,7 @@ void i2c_disable(uint32_t i2c_periph) } /*! - \brief generate a START condition on I2C bus + \brief generate a START condition on I2C bus \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none @@ -311,7 +311,7 @@ void i2c_start_on_bus(uint32_t i2c_periph) } /*! - \brief generate a STOP condition on I2C bus + \brief generate a STOP condition on I2C bus \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none @@ -322,9 +322,9 @@ void i2c_stop_on_bus(uint32_t i2c_periph) } /*! - \brief I2C transmit data function + \brief I2C transmit data function \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ @@ -334,7 +334,7 @@ void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) } /*! - \brief I2C receive data function + \brief I2C receive data function \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval data of received @@ -345,28 +345,28 @@ uint8_t i2c_data_receive(uint32_t i2c_periph) } /*! - \brief enable I2C DMA mode + \brief configure I2C DMA mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] dmastate: only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable + \arg I2C_DMA_ON: enable DMA mode + \arg I2C_DMA_OFF: disable DMA mode \param[out] none \retval none */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) { /* configure I2C DMA function */ uint32_t ctl = 0U; - + ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); + ctl &= ~(I2C_CTL1_DMAON); ctl |= dmastate; I2C_CTL1(i2c_periph) = ctl; } /*! - \brief configure whether next DMA EOT is DMA last transfer or not + \brief configure whether next DMA EOT is DMA last transfer or not \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] dmalast: only one parameter can be selected which is shown as below: @@ -379,36 +379,36 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) { /* configure DMA last transfer */ uint32_t ctl = 0U; - + ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); + ctl &= ~(I2C_CTL1_DMALST); ctl |= dmalast; I2C_CTL1(i2c_periph) = ctl; } /*! - \brief whether to stretch SCL low when data is not ready in slave mode + \brief whether to stretch SCL low when data is not ready in slave mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] stretchpara: only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching + \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching \param[out] none \retval none */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { - /* configure I2C SCL strerching enable or disable */ + /* configure I2C SCL strerching */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); + ctl &= ~(I2C_CTL0_SS); ctl |= stretchpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief whether or not to response to a general call + \brief whether or not to response to a general call \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] gcallpara: only one parameter can be selected which is shown as below: @@ -421,15 +421,15 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) { /* configure slave response to a general call enable or disable */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); + ctl &= ~(I2C_CTL0_GCEN); ctl |= gcallpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief software reset I2C + \brief configure software reset of I2C \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] sreset: only one parameter can be selected which is shown as below: @@ -442,28 +442,28 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) { /* modify CTL0 and configure software reset I2C state */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); + ctl &= ~(I2C_CTL0_SRESET); ctl |= sreset; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief I2C PEC calculation on or off + \brief configure I2C PEC calculation \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecstate: only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off \param[out] none \retval none */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECEN); ctl |= pecstate; @@ -471,20 +471,20 @@ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) } /*! - \brief I2C whether to transfer PEC value + \brief configure whether to transfer PEC value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecpara: only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC + \arg I2C_PECTRANS_ENABLE: transfer PEC value + \arg I2C_PECTRANS_DISABLE: not transfer PEC value \param[out] none \retval none */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECTRANS); ctl |= pecpara; @@ -492,31 +492,31 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) } /*! - \brief get packet error checking value + \brief get packet error checking value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval PEC value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph) { - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); } /*! - \brief I2C issue alert through SMBA pin + \brief configure I2C alert through SMBA pin \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] smbuspara: only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin \param[out] none \retval none */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) { - /* issue alert through SMBA pin configure*/ + /* configure smubus alert through SMBA pin */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SALT); ctl |= smbuspara; @@ -524,7 +524,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) } /*! - \brief enable or disable I2C ARP protocol in SMBus switch + \brief configure I2C ARP protocol in SMBus \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] arpstate: only one parameter can be selected which is shown as below: @@ -533,11 +533,11 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) \param[out] none \retval none */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_ARPEN); ctl |= arpstate; @@ -545,105 +545,122 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) } /*! - \brief analog noise filter disable + \brief disable analog noise filter \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph) { - I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; + I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; } /*! - \brief analog noise filter enable + \brief enable analog noise filter \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_analog_noise_filter_enable(uint32_t i2c_periph) { - I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); + I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); } /*! - \brief digital noise filter configuration + \brief configure digital noise filter \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dfilterpara: refer to enum i2c_digital_filter_enum + \param[in] dfilterpara: refer to i2c_digital_filter_enum + only one parameter can be selected which is shown as below: + \arg I2C_DF_DISABLE: disable digital noise filter + \arg I2C_DF_1PCLK: enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 + \arg I2C_DF_2PCLK: enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 + \arg I2C_DF_3PCLK: enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 + \arg I2C_DF_4PCLK: enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 + \arg I2C_DF_5PCLK: enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 + \arg I2C_DF_6PCLK: enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 + \arg I2C_DF_7PCLK: enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 + \arg I2C_DF_8PCLK: enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 + \arg I2C_DF_9PCLK: enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 + \arg I2C_DF_10PCLK: enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 + \arg I2C_DF_11CLK: enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 + \arg I2C_DF_12CLK: enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 + \arg I2C_DF_13PCLK: enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 + \arg I2C_DF_14PCLK: enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 + \arg I2C_DF_15PCLK: enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 \param[out] none \retval none */ -void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara) +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara) { - I2C_FCTL(i2c_periph) |= dfilterpara; + I2C_FCTL(i2c_periph) |= dfilterpara; } /*! - \brief enable SAM_V interface + \brief enable SAM_V interface \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_sam_enable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; } /*! - \brief disable SAM_V interface + \brief disable SAM_V interface \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_sam_disable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); } /*! - \brief enable SAM_V interface timeout detect + \brief enable SAM_V interface timeout detect \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_sam_timeout_enable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; } /*! - \brief disable SAM_V interface timeout detect + \brief disable SAM_V interface timeout detect \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_sam_timeout_disable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); } /*! - \brief check I2C flag is set or not + \brief get I2C flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_SBSEND: start condition sent out in master mode \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \arg I2C_FLAG_BTC: byte transmission finishes \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus \arg I2C_FLAG_LOSTARB: arbitration lost in master mode \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver \arg I2C_FLAG_RXGC: general call address (00h) received \arg I2C_FLAG_DEFSMB: default address of SMBus device \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode @@ -657,26 +674,26 @@ void i2c_sam_timeout_disable(uint32_t i2c_periph) */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) { - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear I2C flag + \brief clear I2C flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \arg I2C_FLAG_TFF: txframe fall flag \arg I2C_FLAG_TFR: txframe rise flag \arg I2C_FLAG_RFF: rxframe fall flag @@ -686,27 +703,27 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) { - if(I2C_FLAG_ADDSEND == flag){ + if(I2C_FLAG_ADDSEND == flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); - }else{ + } else { I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); } } /*! - \brief enable I2C interrupt + \brief enable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt \param[out] none \retval none */ @@ -716,17 +733,17 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) } /*! - \brief disable I2C interrupt + \brief disable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt \param[out] none \retval none */ @@ -736,15 +753,15 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) } /*! - \brief check I2C interrupt flag + \brief get I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag @@ -753,7 +770,7 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag @@ -764,31 +781,31 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { uint32_t intenable = 0U, flagstatus = 0U, bufie; - + /* check BUFIE */ bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - + /* get the interrupt enable bit status */ intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); /* get the corresponding flag bit status */ flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ - intenable = 1U; - }else{ + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { + intenable = 1U; + } else { intenable = 0U; } } - if((0U != flagstatus) && (0U != intenable)){ + if((0U != flagstatus) && (0U != intenable)) { return SET; - }else{ - return RESET; + } else { + return RESET; } } /*! - \brief clear I2C interrupt flag + \brief clear I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: @@ -799,7 +816,7 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag @@ -809,11 +826,11 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { - if(I2C_INT_FLAG_ADDSEND == int_flag){ + if(I2C_INT_FLAG_ADDSEND == int_flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); - }else{ + } else { I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c index cd5a752..64c6f36 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_ipa.c \brief IPA driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -130,8 +128,8 @@ void ipa_background_lut_loading_enable(void) \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled \param[in] pfcm: pixel format convert mode only one parameter can be selected which is shown as below: - \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert - \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert + \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert + \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert \arg IPA_FGBGTODE: blending foreground and background memory to destination memory \arg IPA_FILL_UP_DE: fill up destination memory with specific color \param[out] none @@ -144,23 +142,23 @@ void ipa_pixel_format_convert_mode_set(uint32_t pfcm) } /*! - \brief initialize the structure of IPA foreground parameter struct with the default values, it is + \brief initialize the structure of IPA foreground parameter struct with the default values, it is suggested that call this function after an ipa_foreground_parameter_struct structure is defined \param[in] none \param[out] foreground_struct: the data needed to initialize foreground foreground_memaddr: foreground memory base address foreground_lineoff: foreground line offset - foreground_prealpha: foreground pre-defined alpha value + foreground_prealpha: foreground pre-defined alpha value foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) foreground_prered: foreground pre-defined red value - foreground_pregreen: foreground pre-defined green value + foreground_pregreen: foreground pre-defined green value foreground_preblue: foreground pre-defined blue value \retval none */ -void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct) +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct) { /* initialize the struct parameters with default values */ foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; @@ -189,15 +187,15 @@ void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground \param[out] none \retval none */ -void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct) { FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { tempflag = SET; /* reset the TEN in order to configure the following bits */ IPA_CTL &= ~IPA_CTL_TEN; } - + /* foreground memory base address configuration */ IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); IPA_FMADDR = foreground_struct->foreground_memaddr; @@ -205,23 +203,23 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); IPA_FLOFF = foreground_struct->foreground_lineoff; /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_FPCTL &= ~(IPA_FPCTL_FPDAV|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); - IPA_FPCTL |= (foreground_struct->foreground_prealpha<<24U); + IPA_FPCTL &= ~(IPA_FPCTL_FPDAV | IPA_FPCTL_FAVCA | IPA_FPCTL_FPF); + IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U); IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; IPA_FPCTL |= foreground_struct->foreground_pf; /* foreground pre-defined red green blue configuration */ - IPA_FPV &= ~(IPA_FPV_FPDRV|IPA_FPV_FPDGV|IPA_FPV_FPDBV); - IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U) - |(foreground_struct->foreground_preblue)); - - if(SET == tempflag){ + IPA_FPV &= ~(IPA_FPV_FPDRV | IPA_FPV_FPDGV | IPA_FPV_FPDBV); + IPA_FPV |= ((foreground_struct->foreground_prered << 16U) | (foreground_struct->foreground_pregreen << 8U) + | (foreground_struct->foreground_preblue)); + + if(SET == tempflag) { /* restore the state of TEN */ IPA_CTL |= IPA_CTL_TEN; } } /*! - \brief initialize the structure of IPA background parameter struct with the default values, it is + \brief initialize the structure of IPA background parameter struct with the default values, it is suggested that call this function after an ipa_background_parameter_struct structure is defined \param[in] none \param[out] background_struct: the data needed to initialize background @@ -237,7 +235,7 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) background_preblue: background pre-defined blue value \retval none */ -void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct) +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct) { /* initialize the struct parameters with default values */ background_struct->background_memaddr = IPA_DEFAULT_VALUE; @@ -266,15 +264,15 @@ void ipa_background_struct_para_init(ipa_background_parameter_struct* background \param[out] none \retval none */ -void ipa_background_init(ipa_background_parameter_struct* background_struct) +void ipa_background_init(ipa_background_parameter_struct *background_struct) { FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { tempflag = SET; /* reset the TEN in order to configure the following bits */ IPA_CTL &= ~IPA_CTL_TEN; } - + /* background memory base address configuration */ IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); IPA_BMADDR = background_struct->background_memaddr; @@ -282,23 +280,23 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct) IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); IPA_BLOFF = background_struct->background_lineoff; /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_BPCTL &= ~(IPA_BPCTL_BPDAV|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); - IPA_BPCTL |= (background_struct->background_prealpha<<24U); + IPA_BPCTL &= ~(IPA_BPCTL_BPDAV | IPA_BPCTL_BAVCA | IPA_BPCTL_BPF); + IPA_BPCTL |= (background_struct->background_prealpha << 24U); IPA_BPCTL |= background_struct->background_alpha_algorithm; - IPA_BPCTL |= background_struct->background_pf; + IPA_BPCTL |= background_struct->background_pf; /* background pre-defined red green blue configuration */ - IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV|IPA_BPV_BPDBV); - IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U) - |(background_struct->background_preblue)); - - if(SET == tempflag){ + IPA_BPV &= ~(IPA_BPV_BPDRV | IPA_BPV_BPDGV | IPA_BPV_BPDBV); + IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U) + | (background_struct->background_preblue)); + + if(SET == tempflag) { /* restore the state of TEN */ IPA_CTL |= IPA_CTL_TEN; } } /*! - \brief initialize the structure of IPA destination parameter struct with the default values, it is + \brief initialize the structure of IPA destination parameter struct with the default values, it is suggested that call this function after an ipa_destination_parameter_struct structure is defined \param[in] none \param[out] destination_struct: the data needed to initialize destination parameter @@ -314,7 +312,7 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct) image_height: height of the image to be processed \retval none */ -void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct) +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct) { /* initialize the struct parameters with default values */ destination_struct->destination_pf = IPA_DPF_ARGB8888; @@ -344,53 +342,53 @@ void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destinat \param[out] none \retval none */ -void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct) { uint32_t destination_pixelformat; FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { tempflag = SET; /* reset the TEN in order to configure the following bits */ IPA_CTL &= ~IPA_CTL_TEN; } - + /* destination pixel format configuration */ IPA_DPCTL &= ~(IPA_DPCTL_DPF); IPA_DPCTL = destination_struct->destination_pf; destination_pixelformat = destination_struct->destination_pf; /* destination pixel format ARGB8888 */ - switch(destination_pixelformat){ + switch(destination_pixelformat) { case IPA_DPF_ARGB8888: - IPA_DPV &= ~(IPA_DPV_DPDBV_0|(IPA_DPV_DPDGV_0)|(IPA_DPV_DPDRV_0)|(IPA_DPV_DPDAV_0)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<8U) - |(destination_struct->destination_prered<<16U) - |(destination_struct->destination_prealpha<<24U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U) + | (destination_struct->destination_prealpha << 24U)); break; /* destination pixel format RGB888 */ case IPA_DPF_RGB888: - IPA_DPV &= ~(IPA_DPV_DPDBV_1|(IPA_DPV_DPDGV_1)|(IPA_DPV_DPDRV_1)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<8U) - |(destination_struct->destination_prered<<16U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_1 | (IPA_DPV_DPDGV_1) | (IPA_DPV_DPDRV_1)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U)); break; /* destination pixel format RGB565 */ case IPA_DPF_RGB565: - IPA_DPV &= ~(IPA_DPV_DPDBV_2|(IPA_DPV_DPDGV_2)|(IPA_DPV_DPDRV_2)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<11U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_2 | (IPA_DPV_DPDGV_2) | (IPA_DPV_DPDRV_2)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 11U)); break; /* destination pixel format ARGB1555 */ case IPA_DPF_ARGB1555: - IPA_DPV &= ~(IPA_DPV_DPDBV_3|(IPA_DPV_DPDGV_3)|(IPA_DPV_DPDRV_3)|(IPA_DPV_DPDAV_3)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<10U) - |(destination_struct->destination_prealpha<<15U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_3 | (IPA_DPV_DPDGV_3) | (IPA_DPV_DPDRV_3) | (IPA_DPV_DPDAV_3)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 10U) + | (destination_struct->destination_prealpha << 15U)); break; /* destination pixel format ARGB4444 */ case IPA_DPF_ARGB4444: - IPA_DPV &= ~(IPA_DPV_DPDBV_4|(IPA_DPV_DPDGV_4)|(IPA_DPV_DPDRV_4)|(IPA_DPV_DPDAV_4)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<4U) - |(destination_struct->destination_prered<<8U) - |(destination_struct->destination_prealpha<<12U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_4 | (IPA_DPV_DPDGV_4) | (IPA_DPV_DPDRV_4) | (IPA_DPV_DPDAV_4)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 4U) + | (destination_struct->destination_prered << 8U) + | (destination_struct->destination_prealpha << 12U)); break; default: break; @@ -400,12 +398,12 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) IPA_DMADDR = destination_struct->destination_memaddr; /* destination line offset configuration */ IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); - IPA_DLOFF =destination_struct->destination_lineoff; + IPA_DLOFF = destination_struct->destination_lineoff; /* image size configuration */ - IPA_IMS &= ~(IPA_IMS_HEIGHT|IPA_IMS_WIDTH); - IPA_IMS |= ((destination_struct->image_width<<16U)|(destination_struct->image_height)); - - if(SET == tempflag){ + IPA_IMS &= ~(IPA_IMS_HEIGHT | IPA_IMS_WIDTH); + IPA_IMS |= ((destination_struct->image_width << 16U) | (destination_struct->image_height)); + + if(SET == tempflag) { /* restore the state of TEN */ IPA_CTL |= IPA_CTL_TEN; } @@ -422,25 +420,25 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) { FlagStatus tempflag = RESET; - if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){ + if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)) { tempflag = SET; /* reset the FLLEN in order to configure the following bits */ IPA_FPCTL &= ~IPA_FPCTL_FLLEN; } - + /* foreground LUT number of pixel configuration */ - IPA_FPCTL |= ((uint32_t)fg_lut_num<<8U); + IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U); /* foreground LUT pixel format configuration */ - if(IPA_LUT_PF_RGB888 == fg_lut_pf){ + if(IPA_LUT_PF_RGB888 == fg_lut_pf) { IPA_FPCTL |= IPA_FPCTL_FLPF; - }else{ + } else { IPA_FPCTL &= ~(IPA_FPCTL_FLPF); } /* foreground LUT memory base address configuration */ IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); IPA_FLMADDR = fg_lut_addr; - - if(SET == tempflag){ + + if(SET == tempflag) { /* restore the state of FLLEN */ IPA_FPCTL |= IPA_FPCTL_FLLEN; } @@ -457,25 +455,25 @@ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_ void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) { FlagStatus tempflag = RESET; - if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){ + if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)) { tempflag = SET; /* reset the BLLEN in order to configure the following bits */ IPA_BPCTL &= ~IPA_BPCTL_BLLEN; } - + /* background LUT number of pixel configuration */ - IPA_BPCTL |= ((uint32_t)bg_lut_num<<8U); + IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U); /* background LUT pixel format configuration */ - if(IPA_LUT_PF_RGB888 == bg_lut_pf){ + if(IPA_LUT_PF_RGB888 == bg_lut_pf) { IPA_BPCTL |= IPA_BPCTL_BLPF; - }else{ + } else { IPA_BPCTL &= ~(IPA_BPCTL_BLPF); } /* background LUT memory base address configuration */ IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); IPA_BLMADDR = bg_lut_addr; - - if(SET == tempflag){ + + if(SET == tempflag) { /* restore the state of BLLEN */ IPA_BPCTL |= IPA_BPCTL_BLLEN; } @@ -501,9 +499,9 @@ void ipa_line_mark_config(uint16_t line_num) */ void ipa_inter_timer_config(uint8_t timer_cfg) { - if(IPA_INTER_TIMER_ENABLE == timer_cfg){ + if(IPA_INTER_TIMER_ENABLE == timer_cfg) { IPA_ITCTL |= IPA_ITCTL_ITEN; - }else{ + } else { IPA_ITCTL &= ~(IPA_ITCTL_ITEN); } } @@ -518,7 +516,7 @@ void ipa_interval_clock_num_config(uint8_t clk_num) { /* NCCI[7:0] bits have no meaning if ITEN is '0' */ IPA_ITCTL &= ~(IPA_ITCTL_NCCI); - IPA_ITCTL |= ((uint32_t)clk_num<<8U); + IPA_ITCTL |= ((uint32_t)clk_num << 8U); } /*! @@ -536,9 +534,9 @@ void ipa_interval_clock_num_config(uint8_t clk_num) */ FlagStatus ipa_flag_get(uint32_t flag) { - if(RESET != (IPA_INTF & flag)){ + if(RESET != (IPA_INTF & flag)) { return SET; - }else{ + } else { return RESET; } } @@ -612,9 +610,9 @@ void ipa_interrupt_disable(uint32_t int_flag) */ FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) { - if(0U != (IPA_INTF & int_flag)){ + if(0U != (IPA_INTF & int_flag)) { return SET; - }else{ + } else { return RESET; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c index a1a8b6c..63f76a1 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c @@ -2,42 +2,40 @@ \file gd32f4xx_iref.c \brief IREF driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_iref.h" /*! - \brief deinit IREF + \brief deinitialize IREF \param[in] none \param[out] none \retval none @@ -60,7 +58,7 @@ void iref_enable(void) } /*! - \brief disable IREF + \brief disable IREF \param[in] none \param[out] none \retval none @@ -71,7 +69,7 @@ void iref_disable(void) } /*! - \brief set IREF mode + \brief set IREF mode \param[in] step \arg IREF_MODE_LOW_POWER: 1uA step \arg IREF_MODE_HIGH_CURRENT: 8uA step @@ -85,7 +83,7 @@ void iref_mode_set(uint32_t step) } /*! - \brief set IREF precision_trim_value + \brief set IREF precision_trim_value \param[in] precisiontrim \arg IREF_CUR_PRECISION_TRIM_X(x=0..31): (-15+ x)% \param[out] none @@ -98,7 +96,7 @@ void iref_precision_trim_value_set(uint32_t precisiontrim) } /*! - \brief set IREF sink mode + \brief set IREF sink mode \param[in] sinkmode \arg IREF_SOURCE_CURRENT : source current. \arg IREF_SINK_CURRENT: sink current @@ -112,7 +110,7 @@ void iref_sink_set(uint32_t sinkmode) } /*! - \brief set IREF step data + \brief set IREF step data \param[in] stepdata \arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x \param[out] none diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c index 2cf04fb..63a7572 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c @@ -1,37 +1,33 @@ /*! \file gd32f4xx_misc.c \brief MISC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx - \version 2021-12-09, V2.1.1, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -62,34 +58,34 @@ void nvic_priority_group_set(uint32_t nvic_prigroup) \param[out] none \retval none */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority) { uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; /* use the priority group value to get the temp_pre and the temp_sub */ - if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ - temp_pre=0U; - temp_sub=0x4U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ - temp_pre=1U; - temp_sub=0x3U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ - temp_pre=2U; - temp_sub=0x2U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ - temp_pre=3U; - temp_sub=0x1U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ - temp_pre=4U; - temp_sub=0x0U; - }else{ + if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) { + temp_pre = 0U; + temp_sub = 0x4U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) { + temp_pre = 1U; + temp_sub = 0x3U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) { + temp_pre = 2U; + temp_sub = 0x2U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) { + temp_pre = 3U; + temp_sub = 0x1U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) { + temp_pre = 4U; + temp_sub = 0x0U; + } else { nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre=2U; - temp_sub=0x2U; + temp_pre = 2U; + temp_sub = 0x2U; } /* get the temp_priority to fill the NVIC->IP register */ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); temp_priority = temp_priority << 0x04U; NVIC->IP[nvic_irq] = (uint8_t)temp_priority; /* enable the selected IRQ */ @@ -126,10 +122,10 @@ void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) /*! \brief set the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts \param[out] none \retval none @@ -142,10 +138,10 @@ void system_lowpower_set(uint8_t lowpower_mode) /*! \brief reset the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts \param[out] none \retval none @@ -166,10 +162,10 @@ void system_lowpower_reset(uint8_t lowpower_mode) void systick_clksource_set(uint32_t systick_clksource) { - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { /* set the systick clock source from HCLK */ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ + } else { /* set the systick clock source from HCLK/8 */ SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c index f71bfed..df389f4 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c @@ -2,42 +2,41 @@ \file gd32f4xx_pmu.c \brief PMU driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_pmu.h" #include "core_cm4.h" + /*! - \brief reset PMU register + \brief reset PMU registers \param[in] none \param[out] none \retval none @@ -50,7 +49,7 @@ void pmu_deinit(void) } /*! - \brief select low voltage detector threshold + \brief select low voltage detector threshold \param[in] lvdt_n: \arg PMU_LVDT_0: voltage threshold is 2.1V \arg PMU_LVDT_1: voltage threshold is 2.3V @@ -76,7 +75,19 @@ void pmu_lvd_select(uint32_t lvdt_n) } /*! - \brief select LDO output voltage + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL \param[in] ldo_output: \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode @@ -92,21 +103,30 @@ void pmu_ldo_output_select(uint32_t ldo_output) } /*! - \brief enable low-driver mode in deep-sleep mode - \param[in] lowdr_mode: - \arg PMU_LOWDRIVER_ENABLE: enable low-driver mode in deep-sleep mode - \arg PMU_LOWDRIVER_DISABLE: disable low-driver mode in deep-sleep mode + \brief enable high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] none \param[out] none \retval none */ -void pmu_low_driver_mode_enable(uint32_t lowdr_mode) +void pmu_highdriver_mode_enable(void) { - PMU_CTL &= ~PMU_CTL_LDEN; - PMU_CTL |= lowdr_mode; + PMU_CTL |= PMU_CTL_HDEN; } /*! - \brief switch high-driver mode + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief switch high-driver mode this bit set by software only when IRC16M or HXTAL used as system clock \param[in] highdr_switch: \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch @@ -117,77 +137,64 @@ void pmu_low_driver_mode_enable(uint32_t lowdr_mode) void pmu_highdriver_switch_select(uint32_t highdr_switch) { /* wait for HDRF flag set */ - while(SET != pmu_flag_get(PMU_FLAG_HDRF)){ + while(SET != pmu_flag_get(PMU_FLAG_HDRF)) { } PMU_CTL &= ~PMU_CTL_HDS; PMU_CTL |= highdr_switch; } /*! - \brief enable high-driver mode - this bit set by software only when IRC16M or HXTAL used as system clock + \brief enable low-driver mode in deep-sleep \param[in] none \param[out] none \retval none */ -void pmu_highdriver_mode_enable(void) +void pmu_lowdriver_mode_enable(void) { - PMU_CTL |= PMU_CTL_HDEN; + PMU_CTL |= PMU_CTL_LDEN; } /*! - \brief disable high-driver mode + \brief disable low-driver mode in deep-sleep \param[in] none \param[out] none \retval none */ -void pmu_highdriver_mode_disable(void) +void pmu_lowdriver_mode_disable(void) { - PMU_CTL &= ~PMU_CTL_HDEN; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; + PMU_CTL &= ~PMU_CTL_LDEN; } /*! - \brief low-driver mode when use low power LDO + \brief in deep-sleep mode, driver mode when use low power LDO \param[in] mode: \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO \param[out] none \retval none */ -void pmu_lowdriver_lowpower_config(uint32_t mode) +void pmu_lowpower_driver_config(uint32_t mode) { PMU_CTL &= ~PMU_CTL_LDLP; PMU_CTL |= mode; } /*! - \brief low-driver mode when use normal power LDO + \brief in deep-sleep mode, driver mode when use normal power LDO \param[in] mode: \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO \param[out] none \retval none */ -void pmu_lowdriver_normalpower_config(uint32_t mode) +void pmu_normalpower_driver_config(uint32_t mode) { PMU_CTL &= ~PMU_CTL_LDNP; PMU_CTL |= mode; } /*! - \brief PMU work at sleep mode + \brief PMU work in sleep mode \param[in] sleepmodecmd: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command @@ -198,157 +205,142 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) { /* clear sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - + /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ + if(WFI_CMD == sleepmodecmd) { __WFI(); - }else{ + } else { __WFE(); } } /*! - \brief PMU work at deepsleep mode + \brief PMU work in deep-sleep mode \param[in] ldo - \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: + \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deep-sleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deep-sleep mode + \param[in] lowdrive: + only one parameter can be selected which is shown as below: + \arg PMU_LOWDRIVER_DISABLE: Low-driver mode disable in deep-sleep mode + \arg PMU_LOWDRIVER_ENABLE: Low-driver mode enable in deep-sleep mode + \param[in] deepsleepmodecmd: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd) { - static uint32_t reg_snap[ 4 ]; + static uint32_t reg_snap[4]; /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN | PMU_CTL_LDNP | PMU_CTL_LDLP)); + /* set ldolp bit according to pmu_ldo */ PMU_CTL |= ldo; - + + /* configure low drive mode in deep-sleep mode */ + if(PMU_LOWDRIVER_ENABLE == lowdrive) { + if(PMU_LDO_NORMAL == ldo) { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDNP); + } else { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDLP); + } + } /* set sleepdeep bit of Cortex-M4 system control register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - reg_snap[ 0 ] = REG32( 0xE000E010U ); - reg_snap[ 1 ] = REG32( 0xE000E100U ); - reg_snap[ 2 ] = REG32( 0xE000E104U ); - reg_snap[ 3 ] = REG32( 0xE000E108U ); - - REG32( 0xE000E010U ) &= 0x00010004U; - REG32( 0xE000E180U ) = 0XFF7FF831U; - REG32( 0xE000E184U ) = 0XBFFFF8FFU; - REG32( 0xE000E188U ) = 0xFFFFEFFFU; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ + reg_snap[0] = REG32(0xE000E010U); + reg_snap[1] = REG32(0xE000E100U); + reg_snap[2] = REG32(0xE000E104U); + reg_snap[3] = REG32(0xE000E108U); + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFF7FF831U; + REG32(0xE000E184U) = 0XBFFFF8FFU; + REG32(0xE000E188U) = 0xFFFFEFFFU; + + /* select WFI or WFE command to enter deep-sleep mode */ + if(WFI_CMD == deepsleepmodecmd) { __WFI(); - }else{ + } else { __SEV(); __WFE(); __WFE(); } - - REG32( 0xE000E010U ) = reg_snap[ 0 ] ; - REG32( 0xE000E100U ) = reg_snap[ 1 ] ; - REG32( 0xE000E104U ) = reg_snap[ 2 ] ; - REG32( 0xE000E108U ) = reg_snap[ 3 ] ; - + + REG32(0xE000E010U) = reg_snap[0]; + REG32(0xE000E100U) = reg_snap[1]; + REG32(0xE000E104U) = reg_snap[2]; + REG32(0xE000E108U) = reg_snap[3]; + /* reset sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command + \brief pmu work in standby mode + \param[in] none \param[out] none \retval none */ -void pmu_to_standbymode(uint8_t standbymodecmd) +void pmu_to_standbymode(void) { - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; - + /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - __WFE(); - } + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFDFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI command to enter standby mode */ + __WFI(); } /*! - \brief backup SRAM LDO on - \param[in] bkp_ldo: - \arg PMU_BLDOON_OFF: backup SRAM LDO closed - \arg PMU_BLDOON_ON: open the backup SRAM LDO + \brief enable PMU wakeup pin + \param[in] none \param[out] none \retval none */ -void pmu_backup_ldo_config(uint32_t bkp_ldo) +void pmu_wakeup_pin_enable(void) { - PMU_CS &= ~PMU_CS_BLDOON; - PMU_CS |= bkp_ldo; + PMU_CS |= PMU_CS_WUPEN; } /*! - \brief reset flag bit - \param[in] flag_reset: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \brief disable PMU wakeup pin + \param[in] none \param[out] none \retval none */ -void pmu_flag_reset(uint32_t flag_reset) +void pmu_wakeup_pin_disable(void) { - switch(flag_reset){ - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default : - break; - } + PMU_CS &= ~PMU_CS_WUPEN; } /*! - \brief get flag state - \param[in] pmu_flag: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag - \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag - \arg PMU_FLAG_HDRF: high-driver ready flag - \arg PMU_FLAG_HDSRF: high-driver switch ready flag - \arg PMU_FLAG_LDRF: low-driver mode ready flag + \brief backup SRAM LDO on + \param[in] bkp_ldo: + \arg PMU_BLDOON_OFF: backup SRAM LDO closed + \arg PMU_BLDOON_ON: open the backup SRAM LDO \param[out] none - \retval FlagStatus: SET or RESET + \retval none */ -FlagStatus pmu_flag_get(uint32_t pmu_flag) +void pmu_backup_ldo_config(uint32_t bkp_ldo) { - if(PMU_CS & pmu_flag){ - return SET; - }else{ - return RESET; - } + PMU_CS &= ~PMU_CS_BLDOON; + PMU_CS |= bkp_ldo; } /*! - \brief enable backup domain write + \brief enable write access to the registers in backup domain \param[in] none \param[out] none \retval none @@ -359,7 +351,7 @@ void pmu_backup_write_enable(void) } /*! - \brief disable backup domain write + \brief disable write access to the registers in backup domain \param[in] none \param[out] none \retval none @@ -370,23 +362,48 @@ void pmu_backup_write_disable(void) } /*! - \brief enable wakeup pin - \param[in] none + \brief get flag state + \param[in] flag: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag + \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag + \arg PMU_FLAG_HDRF: high-driver ready flag + \arg PMU_FLAG_HDSRF: high-driver switch ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void pmu_wakeup_pin_enable(void) +FlagStatus pmu_flag_get(uint32_t flag) { - PMU_CS |= PMU_CS_WUPEN; + if(PMU_CS & flag) { + return SET; + } else { + return RESET; + } } /*! - \brief disable wakeup pin - \param[in] none + \brief clear flag bit + \param[in] flag: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag \param[out] none \retval none */ -void pmu_wakeup_pin_disable(void) +void pmu_flag_clear(uint32_t flag) { - PMU_CS &= ~PMU_CS_WUPEN; + switch(flag) { + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c index 215d631..5c99285 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_rcu.c \brief RCU driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -60,9 +58,9 @@ void rcu_deinit(void) RCU_CTL |= RCU_CTL_IRC16MEN; rcu_osci_stab_wait(RCU_IRC16M); RCU_CFG0 &= ~RCU_CFG0_SCS; - - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN + + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN | RCU_CTL_PLLSAIEN); RCU_CTL &= ~(RCU_CTL_HXTALBPS); /* reset CFG0 register */ @@ -78,14 +76,14 @@ void rcu_deinit(void) /* reset INT register */ RCU_INT = 0x00000000U; /* reset CFG1 register */ - RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); + RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); } /*! \brief enable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC: CRC clock \arg RCU_BKPSRAM: BKPSRAM clock \arg RCU_TCMSRAM: TCMSRAM clock @@ -101,17 +99,17 @@ void rcu_deinit(void) \arg RCU_TRNG: TRNG clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock \arg RCU_SDIO: SDIO clock \arg RCU_SYSCFG: SYSCFG clock \arg RCU_TLI: TLI clock @@ -129,7 +127,7 @@ void rcu_periph_clock_enable(rcu_periph_enum periph) \brief disable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC: CRC clock \arg RCU_BKPSRAM: BKPSRAM clock \arg RCU_TCMSRAM: TCMSRAM clock @@ -145,17 +143,17 @@ void rcu_periph_clock_enable(rcu_periph_enum periph) \arg RCU_TRNG: TRNG clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock \arg RCU_SDIO: SDIO clock \arg RCU_SYSCFG: SYSCFG clock \arg RCU_TLI: TLI clock @@ -173,7 +171,7 @@ void rcu_periph_clock_disable(rcu_periph_enum periph) \brief enable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC_SLP: CRC clock \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM0_SLP: SRAM0 clock @@ -192,17 +190,17 @@ void rcu_periph_clock_disable(rcu_periph_enum periph) \arg RCU_TRNG_SLP: TRNG clock \arg RCU_USBFS_SLP: USBFS clock \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock \arg RCU_PMU_SLP: PMU clock \arg RCU_DAC_SLP: DAC clock \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock \arg RCU_SDIO_SLP: SDIO clock \arg RCU_SYSCFG_SLP: SYSCFG clock \arg RCU_TLI_SLP: TLI clock @@ -220,7 +218,7 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) \brief disable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC_SLP: CRC clock \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM0_SLP: SRAM0 clock @@ -239,17 +237,17 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) \arg RCU_TRNG_SLP: TRNG clock \arg RCU_USBFS_SLP: USBFS clock \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock \arg RCU_PMU_SLP: PMU clock \arg RCU_DAC_SLP: DAC clock \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock \arg RCU_SDIO_SLP: SDIO clock \arg RCU_SYSCFG_SLP: SYSCFG clock \arg RCU_TLI_SLP: TLI clock @@ -267,7 +265,7 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \brief reset the peripherals \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA \arg RCU_IPARST: reset IPA @@ -277,16 +275,16 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \arg RCU_TRNGRST: reset TRNG \arg RCU_USBFSRST: reset USBFS \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC \arg RCU_SDIORST: reset SDIO \arg RCU_SYSCFGRST: reset SYSCFG \arg RCU_TLIRST: reset TLI @@ -304,7 +302,7 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \brief disable reset the peripheral \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA \arg RCU_IPARST: reset IPA @@ -314,16 +312,16 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \arg RCU_TRNGRST: reset TRNG \arg RCU_USBFSRST: reset USBFS \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC \arg RCU_SDIORST: reset SDIO \arg RCU_SYSCFGRST: reset SYSCFG \arg RCU_TLIRST: reset TLI @@ -372,7 +370,7 @@ void rcu_bkp_reset_disable(void) void rcu_system_clock_source_config(uint32_t ck_sys) { uint32_t reg; - + reg = RCU_CFG0; /* reset the SCS bits and set according to ck_sys */ reg &= ~RCU_CFG0_SCS; @@ -397,14 +395,14 @@ uint32_t rcu_system_clock_source_get(void) \brief configure the AHB clock prescaler selection \param[in] ck_ahb: AHB clock prescaler selection only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \arg RCU_AHB_CKSYS_DIVx (x = 1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB \param[out] none \retval none */ void rcu_ahb_clock_config(uint32_t ck_ahb) { uint32_t reg; - + reg = RCU_CFG0; /* reset the AHBPSC bits and set according to ck_ahb */ reg &= ~RCU_CFG0_AHBPSC; @@ -416,17 +414,17 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) \param[in] ck_apb1: APB1 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB / 2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB / 4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB / 8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB / 16 as CK_APB1 \param[out] none \retval none */ void rcu_apb1_clock_config(uint32_t ck_apb1) { uint32_t reg; - + reg = RCU_CFG0; /* reset the APB1PSC and set according to ck_apb1 */ reg &= ~RCU_CFG0_APB1PSC; @@ -438,17 +436,17 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) \param[in] ck_apb2: APB2 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB / 2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB / 4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB / 8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB / 16 as CK_APB2 \param[out] none \retval none */ void rcu_apb2_clock_config(uint32_t ck_apb2) { uint32_t reg; - + reg = RCU_CFG0; /* reset the APB2PSC and set according to ck_apb2 */ reg &= ~RCU_CFG0_APB2PSC; @@ -463,18 +461,18 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected \arg RCU_CKOUT0SRC_PLLP: PLLP selected - \param[in] ckout0_div: CK_OUT0 divider - \arg RCU_CKOUT0_DIVx(x=1,2,3,4,5): CK_OUT0 is divided by x + \param[in] ckout0_div: CK_OUT0 divider + \arg RCU_CKOUT0_DIVx(x = 1, 2, 3, 4, 5): CK_OUT0 is divided by x \param[out] none \retval none */ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) { uint32_t reg; - + reg = RCU_CFG0; /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ - reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV ); + reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV); RCU_CFG0 = (reg | ckout0_src | ckout0_div); } @@ -485,16 +483,16 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected \arg RCU_CKOUT1SRC_PLLI2SR: PLLI2SR selected \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT1SRC_PLLP: PLLP selected - \param[in] ckout1_div: CK_OUT1 divider - \arg RCU_CKOUT1_DIVx(x=1,2,3,4,5): CK_OUT1 is divided by x + \arg RCU_CKOUT1SRC_PLLP: PLLP selected + \param[in] ckout1_div: CK_OUT1 divider + \arg RCU_CKOUT1_DIVx(x = 1, 2, 3, 4, 5): CK_OUT1 is divided by x \param[out] none \retval none */ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) { uint32_t reg; - + reg = RCU_CFG0; /* reset the CKOUT1SRC, CKOUT1DIV and set according to ckout1_src and ckout1_div */ reg &= ~(RCU_CFG0_CKOUT1SEL | RCU_CFG0_CKOUT1DIV); @@ -502,7 +500,7 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) } /*! - \brief configure the main PLL clock + \brief configure the main PLL clock \param[in] pll_src: PLL clock source selection \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock @@ -521,35 +519,35 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin { uint32_t ss_modulation_inc; uint32_t ss_modulation_reg; - + ss_modulation_inc = 0U; ss_modulation_reg = RCU_PLLSSCTL; /* calculate the minimum factor of PLLN */ - if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON){ - if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN){ + if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON) { + if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN) { ss_modulation_inc += RCU_SS_MODULATION_DOWN_INC; - }else{ + } else { ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; } } - + /* check the function parameter */ - if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && - CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)){ - RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | - (pll_src) | (pll_q << 24); - }else{ + if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n, ss_modulation_inc) && + CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)) { + RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | + (pll_src) | (pll_q << 24); + } else { /* return status */ return ERROR; } - + /* return status */ return SUCCESS; } /*! - \brief configure the PLLI2S clock + \brief configure the PLLI2S clock \param[in] plli2s_n: the PLLI2S VCO clock multi factor \arg this parameter should be selected between 50 and 500 \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock @@ -560,19 +558,19 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) { /* check the function parameter */ - if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)){ + if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)) { RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); - }else{ + } else { /* return status */ return ERROR; } - + /* return status */ - return SUCCESS; + return SUCCESS; } /*! - \brief configure the PLLSAI clock + \brief configure the PLLSAI clock \param[in] pllsai_n: the PLLSAI VCO clock multi factor \arg this parameter should be selected between 50 and 500 \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock @@ -585,13 +583,13 @@ ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) { /* check the function parameter */ - if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)){ + if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)) { RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); - }else{ + } else { /* return status */ return ERROR; } - + /* return status */ return SUCCESS; } @@ -603,34 +601,34 @@ ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsa \arg RCU_RTCSRC_NONE: no clock selected \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock \arg RCU_RTCSRC_IRC32K: CK_IRC32K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL/RTCDIV selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL / RTCDIV selected as RTC source clock \param[out] none \retval none */ void rcu_rtc_clock_config(uint32_t rtc_clock_source) { uint32_t reg; - - reg = RCU_BDCTL; + + reg = RCU_BDCTL; /* reset the RTCSRC bits and set according to rtc_clock_source */ reg &= ~RCU_BDCTL_RTCSRC; RCU_BDCTL = (reg | rtc_clock_source); } /*! - \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source + \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source \param[in] rtc_div: RTC clock frequency division only one parameter can be selected which is shown as below: \arg RCU_RTC_HXTAL_NONE: no clock for RTC - \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL/x, x = 2....31 + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL / x, x = 2....31 \param[out] none \retval none */ void rcu_rtc_div_config(uint32_t rtc_div) { uint32_t reg; - - reg = RCU_CFG0; + + reg = RCU_CFG0; /* reset the RTCDIV bits and set according to rtc_div value */ reg &= ~RCU_CFG0_RTCDIV; RCU_CFG0 = (reg | rtc_div); @@ -649,8 +647,8 @@ void rcu_rtc_div_config(uint32_t rtc_div) void rcu_i2s_clock_config(uint32_t i2s_clock_source) { uint32_t reg; - - reg = RCU_CFG0; + + reg = RCU_CFG0; /* reset the I2SSEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG0_I2SSEL; RCU_CFG0 = (reg | i2s_clock_source); @@ -668,7 +666,7 @@ void rcu_i2s_clock_config(uint32_t i2s_clock_source) void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) { uint32_t reg; - + reg = RCU_ADDCTL; /* reset the CK48MSEL bit and set according to i2s_clock_source */ reg &= ~RCU_ADDCTL_CK48MSEL; @@ -687,7 +685,7 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) { uint32_t reg; - + reg = RCU_ADDCTL; /* reset the PLL48MSEL bit and set according to pll48m_clock_source */ reg &= ~RCU_ADDCTL_PLL48MSEL; @@ -698,13 +696,13 @@ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) \brief configure the TIMER clock prescaler selection \param[in] timer_clock_prescaler: TIMER clock selection only one parameter can be selected which is shown as below: - \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) - \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) \param[out] none \retval none @@ -712,9 +710,9 @@ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) { /* configure the TIMERSEL bit and select the TIMER clock prescaler */ - if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2){ + if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2) { RCU_CFG1 &= timer_clock_prescaler; - }else{ + } else { RCU_CFG1 |= timer_clock_prescaler; } } @@ -730,144 +728,13 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) void rcu_tli_clock_div_config(uint32_t pllsai_r_div) { uint32_t reg; - + reg = RCU_CFG1; /* reset the PLLSAIRDIV bit and set according to pllsai_r_div */ reg &= ~RCU_CFG1_PLLSAIRDIV; RCU_CFG1 = (reg | pllsai_r_div); } -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag - \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_BORRST: BOR reset flags - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: Power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) -{ - RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); -} - /*! \brief configure the LXTAL drive capability \param[in] lxtal_dricap: drive capability of LXTAL @@ -880,9 +747,9 @@ void rcu_interrupt_disable(rcu_int_enum interrupt) void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) { uint32_t reg; - + reg = RCU_BDCTL; - + /* reset the LXTALDRI bits and set according to lxtal_dricap */ reg &= ~RCU_BDCTL_LXTALDRI; RCU_BDCTL = (reg | lxtal_dricap); @@ -908,109 +775,109 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) uint32_t stb_cnt = 0U; ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; - - switch(osci){ + + switch(osci) { /* wait HXTAL stable */ case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { reval = SUCCESS; } break; /* wait LXTAL stable */ case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { reval = SUCCESS; } break; - /* wait IRC16M stable */ + /* wait IRC16M stable */ case RCU_IRC16M: - while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)) { reval = SUCCESS; } break; - /* wait IRC48M stable */ + /* wait IRC48M stable */ case RCU_IRC48M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); stb_cnt++; } - + /* check whether flag is set */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { reval = SUCCESS; } break; /* wait IRC32K stable */ case RCU_IRC32K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)) { reval = SUCCESS; } break; - /* wait PLL stable */ + /* wait PLL stable */ case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { reval = SUCCESS; } break; /* wait PLLI2S stable */ case RCU_PLLI2S_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)) { reval = SUCCESS; } break; - /* wait PLLSAI stable */ + /* wait PLLSAI stable */ case RCU_PLLSAI_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); stb_cnt++; } - + /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)) { reval = SUCCESS; } break; - + default: break; } - + /* return value */ return reval; } @@ -1068,8 +935,8 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) { uint32_t reg; - switch(osci){ - /* enable HXTAL to bypass mode */ + switch(osci) { + /* enable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; @@ -1086,7 +953,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) case RCU_IRC32K: case RCU_PLL_CK: case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: + case RCU_PLLSAI_CK: break; default: break; @@ -1105,9 +972,9 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; - - switch(osci){ - /* disable HXTAL to bypass mode */ + + switch(osci) { + /* disable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; @@ -1124,36 +991,13 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) case RCU_IRC32K: case RCU_PLL_CK: case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: + case RCU_PLLSAI_CK: break; default: break; } } -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - /*! \brief set the IRC16M adjust value \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F @@ -1164,41 +1008,13 @@ void rcu_hxtal_clock_monitor_disable(void) void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) { uint32_t reg; - + reg = RCU_CTL; /* reset the IRC16MADJ bits and set according to irc16m_adjval */ reg &= ~RCU_CTL_IRC16MADJ; RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); } -/*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - RCU_VKEY = RCU_VKEY_UNLOCK; -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - /*! \brief configure the spread spectrum modulation for the main PLL clock \param[in] spread_spectrum_type: PLL spread spectrum modulation type select @@ -1214,7 +1030,7 @@ void rcu_deepsleep_voltage_set(uint32_t dsvol) void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt) { uint32_t reg; - + reg = RCU_PLLSSCTL; /* reset the RCU_PLLSSCTL register bits */ reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE); @@ -1243,6 +1059,57 @@ void rcu_spread_spectrum_disable(void) RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON; } +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + RCU_VKEY = RCU_VKEY_UNLOCK; +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0: the core voltage is default value + \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it) + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + /*! \brief get the system clock, bus and peripheral clock frequency \param[in] clock: the clock frequency which to get @@ -1259,14 +1126,14 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) uint32_t sws, ck_freq = 0U; uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ + switch(sws) { /* IRC16M is selected as CK_SYS */ case SEL_IRC16M: cksys_freq = IRC16M_VALUE; @@ -1283,12 +1150,12 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; /* PLL clock source selection, HXTAL or IRC16M/2 */ pllsel = (RCU_PLL & RCU_PLL_PLLSEL); - if (RCU_PLLSRC_HXTAL == pllsel) { + if(RCU_PLLSRC_HXTAL == pllsel) { ck_src = HXTAL_VALUE; } else { ck_src = IRC16M_VALUE; } - cksys_freq = ((ck_src / pllpsc) * plln)/pllp; + cksys_freq = ((ck_src / pllpsc) * plln) / pllp; break; /* IRC16M is selected as CK_SYS */ default: @@ -1299,19 +1166,19 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) idx = GET_BITS(RCU_CFG0, 4, 7); clk_exp = ahb_exp[idx]; ahb_freq = cksys_freq >> clk_exp; - + /* calculate APB1 clock frequency */ idx = GET_BITS(RCU_CFG0, 10, 12); clk_exp = apb1_exp[idx]; apb1_freq = ahb_freq >> clk_exp; - + /* calculate APB2 clock frequency */ idx = GET_BITS(RCU_CFG0, 13, 15); clk_exp = apb2_exp[idx]; apb2_freq = ahb_freq >> clk_exp; - + /* return the clocks frequency */ - switch(clock){ + switch(clock) { case CK_SYS: ck_freq = cksys_freq; break; @@ -1329,3 +1196,134 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) } return ck_freq; } + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag + \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_BORRST: BOR reset flags + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: Power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) +{ + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); +} diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c index 207d445..b7baf3a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c @@ -2,35 +2,33 @@ \file gd32f4xx_rtc.c \brief RTC driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -45,7 +43,6 @@ OF SUCH DAMAGE. #define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ #define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ - /*! \brief reset most of the RTC registers \param[in] none @@ -67,7 +64,7 @@ ErrStatus rtc_deinit(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { /* reset RTC_CTL register, but RTC_CTL[2��0] */ RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. @@ -78,18 +75,18 @@ ErrStatus rtc_deinit(void) RTC_PSC = RTC_PSC_RESET; /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { RTC_CTL &= RTC_REGISTER_RESET; RTC_WUT = RTC_WUT_RESET; RTC_COSC = RTC_REGISTER_RESET; /* to write RTC_ALRMxSS register, ALRMxEN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM0TD = RTC_REGISTER_RESET; RTC_ALRM1TD = RTC_REGISTER_RESET; RTC_ALRM0SS = RTC_REGISTER_RESET; RTC_ALRM1SS = RTC_REGISTER_RESET; @@ -97,9 +94,9 @@ ErrStatus rtc_deinit(void) at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ RTC_STAT = RTC_STAT_RESET; /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_SHIFTCTL = RTC_REGISTER_RESET; RTC_HRFC = RTC_REGISTER_RESET; - error_status = rtc_register_sync_wait(); + error_status = rtc_register_sync_wait(); } } @@ -111,7 +108,7 @@ ErrStatus rtc_deinit(void) /*! \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: year: 0x0 - 0x99(BCD format) @@ -130,7 +127,7 @@ ErrStatus rtc_deinit(void) \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) { ErrStatus error_status = ERROR; uint32_t reg_time = 0U, reg_date = 0U; @@ -138,13 +135,13 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) reg_date = (DATE_YR(rtc_initpara_struct->year) | \ DATE_DOW(rtc_initpara_struct->day_of_week) | \ DATE_MON(rtc_initpara_struct->month) | \ - DATE_DAY(rtc_initpara_struct->date)); - - reg_time = (rtc_initpara_struct->am_pm| \ + DATE_DAY(rtc_initpara_struct->date)); + + reg_time = (rtc_initpara_struct->am_pm | \ TIME_HR(rtc_initpara_struct->hour) | \ TIME_MN(rtc_initpara_struct->minute) | \ - TIME_SC(rtc_initpara_struct->second)); - + TIME_SC(rtc_initpara_struct->second)); + /* 1st: disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -152,8 +149,8 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) /* 2nd: enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ - RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn)| \ + if(ERROR != error_status) { + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \ PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); RTC_TIME = (uint32_t)reg_time; @@ -161,10 +158,10 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) RTC_CTL &= (uint32_t)(~RTC_CTL_CS); RTC_CTL |= rtc_initpara_struct->display_format; - - /* 3rd: exit init mode */ + + /* 3rd: exit init mode */ rtc_init_mode_exit(); - + /* 4th: wait the RSYNF flag to set */ error_status = rtc_register_sync_wait(); } @@ -188,18 +185,18 @@ ErrStatus rtc_init_mode_enter(void) ErrStatus error_status = ERROR; /* check whether it has been in init mode */ - if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ + if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { RTC_STAT |= RTC_STAT_INITM; - + /* wait until the INITF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_INITF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + do { + flag_status = RTC_STAT & RTC_STAT_INITF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if((uint32_t)RESET != flag_status) { error_status = SUCCESS; } - }else{ + } else { error_status = SUCCESS; } return error_status; @@ -217,7 +214,7 @@ void rtc_init_mode_exit(void) } /*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated \param[in] none \param[out] none @@ -229,7 +226,7 @@ ErrStatus rtc_register_sync_wait(void) uint32_t flag_status = RESET; ErrStatus error_status = ERROR; - if ((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ + if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -238,17 +235,17 @@ ErrStatus rtc_register_sync_wait(void) RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); /* wait until RSYNF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_RSYNF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if((uint32_t)RESET != flag_status) { error_status = SUCCESS; } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - }else{ + } else { error_status = SUCCESS; } @@ -258,7 +255,7 @@ ErrStatus rtc_register_sync_wait(void) /*! \brief get current time and date \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: year: 0x0 - 0x99(BCD format) @@ -276,26 +273,26 @@ ErrStatus rtc_register_sync_wait(void) display_format: RTC_24HOUR, RTC_12HOUR \retval none */ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) { uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; - temp_tr = (uint32_t)RTC_TIME; + temp_tr = (uint32_t)RTC_TIME; temp_dr = (uint32_t)RTC_DATE; temp_pscr = (uint32_t)RTC_PSC; temp_ctlr = (uint32_t)RTC_CTL; - + /* get current time and construct rtc_parameter_struct structure */ rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr); rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr); rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr); rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr); rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); } @@ -311,7 +308,7 @@ uint32_t rtc_subsecond_get(void) /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ reg = (uint32_t)RTC_SS; /* read RTC_DATE to unlock the 3 shadow registers */ - (void) (RTC_DATE); + (void)(RTC_DATE); return reg; } @@ -319,7 +316,7 @@ uint32_t rtc_subsecond_get(void) /*! \brief configure RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK @@ -335,26 +332,26 @@ uint32_t rtc_subsecond_get(void) \param[out] none \retval none */ -void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) +void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) { uint32_t reg_alrmtd = 0U; - reg_alrmtd =(rtc_alarm_time->alarm_mask | \ - rtc_alarm_time->weekday_or_date | \ - rtc_alarm_time->am_pm | \ - ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ - ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ - ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ - ALRMTD_SC(rtc_alarm_time->alarm_second)); + reg_alrmtd = (rtc_alarm_time->alarm_mask | \ + rtc_alarm_time->weekday_or_date | \ + rtc_alarm_time->am_pm | \ + ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ + ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ + ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ + ALRMTD_SC(rtc_alarm_time->alarm_second)); /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { RTC_ALRM0TD = (uint32_t)reg_alrmtd; - - }else{ + + } else { RTC_ALRM1TD = (uint32_t)reg_alrmtd; } /* enable the write protection */ @@ -389,12 +386,12 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; - if(RTC_ALARM0 == rtc_alarm){ - RTC_ALRM0SS = mask_subsecond | subsecond; - }else{ - RTC_ALRM1SS = mask_subsecond | subsecond; + if(RTC_ALARM0 == rtc_alarm) { + RTC_ALRM0SS = mask_subsecond | subsecond; + } else { + RTC_ALRM1SS = mask_subsecond | subsecond; } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; @@ -403,7 +400,7 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint /*! \brief get RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK @@ -418,24 +415,24 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint am_pm: RTC_AM, RTC_PM \retval none */ -void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) +void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) { uint32_t reg_alrmtd = 0U; /* get the value of RTC_ALRM0TD register */ - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { reg_alrmtd = RTC_ALRM0TD; - }else{ + } else { reg_alrmtd = RTC_ALRM1TD; } /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; + rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM); rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS); rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd); rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd); rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd); - rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); + rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); } /*! @@ -446,9 +443,9 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) */ uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm) { - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); - }else{ + } else { return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC)); } } @@ -465,9 +462,9 @@ void rtc_alarm_enable(uint8_t rtc_alarm) RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { RTC_CTL |= RTC_CTL_ALRM0EN; - }else{ + } else { RTC_CTL |= RTC_CTL_ALRM1EN; } /* enable the write protection */ @@ -489,23 +486,23 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* clear the state of alarm */ - if(RTC_ALARM0 == rtc_alarm){ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + if(RTC_ALARM0 == rtc_alarm) { + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); /* wait until ALRM0WF flag to be set after the alarm is disabled */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - }else{ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } else { + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); /* wait until ALRM1WF flag to be set after the alarm is disabled */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_ALRM1WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } - - if ((uint32_t)RESET != flag_status){ + + if((uint32_t)RESET != flag_status) { error_status = SUCCESS; } @@ -532,7 +529,7 @@ void rtc_timestamp_enable(uint32_t edge) /* new configuration */ reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -554,7 +551,7 @@ void rtc_timestamp_disable(void) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* clear the TSEN bit */ RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); @@ -565,7 +562,7 @@ void rtc_timestamp_disable(void) /*! \brief get RTC timestamp time and date \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains parameters for RTC time-stamp configuration members of the structure and the member values are shown as below: timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, @@ -579,14 +576,14 @@ void rtc_timestamp_disable(void) am_pm: RTC_AM, RTC_PM \retval none */ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) { uint32_t temp_tts = 0U, temp_dts = 0U; /* get the value of time_stamp registers */ temp_tts = (uint32_t)RTC_TTS; temp_dts = (uint32_t)RTC_DTS; - + /* get timestamp time and construct the rtc_timestamp_struct structure */ rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); @@ -609,7 +606,7 @@ uint32_t rtc_timestamp_subsecond_get(void) } /*! - \brief RTC time-stamp mapping + \brief RTC time-stamp mapping \param[in] rtc_af: \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp @@ -624,7 +621,7 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) /*! \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains parameters for RTC tamper configuration members of the structure and the member values are shown as below: detecting tamper event can using edge mode or level mode @@ -646,49 +643,49 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) \param[out] none \retval none */ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) { /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); + RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); /* tamper filter must be used when the tamper source is voltage level detection */ RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - + /* the tamper source is voltage level detection */ - if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ + if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE) { RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); /* check if the tamper pin need precharge, if need, then configure the precharge time */ - if(DISABLE == rtc_tamper->tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; - }else{ + if(DISABLE == rtc_tamper->tamper_precharge_enable) { + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + } else { RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); } RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency); RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter); - + /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); } - }else{ - + } else { + /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); } } - - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - if(DISABLE != rtc_tamper->tamper_with_timestamp){ + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + if(DISABLE != rtc_tamper->tamper_with_timestamp) { /* the tamper event also cause a time-stamp event */ RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } + } /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); } /*! @@ -702,12 +699,12 @@ void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) void rtc_tamper_disable(uint32_t source) { /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; + RTC_TAMP &= (uint32_t)~source; } /*! - \brief RTC tamper0 mapping + \brief RTC tamper0 mapping \param[in] rtc_af: \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 @@ -732,18 +729,18 @@ void rtc_tamper0_pin_map(uint32_t rtc_af) \retval none */ void rtc_interrupt_enable(uint32_t interrupt) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* enable the interrupts in RTC_CTL register */ RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); /* enable the interrupts in RTC_TAMP register */ RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - + /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; + RTC_WPK = RTC_LOCK_KEY; } /*! @@ -758,11 +755,11 @@ void rtc_interrupt_enable(uint32_t interrupt) \retval none */ void rtc_interrupt_disable(uint32_t interrupt) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* disable the interrupts in RTC_CTL register */ RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); /* disable the interrupts in RTC_TAMP register */ @@ -779,7 +776,7 @@ void rtc_interrupt_disable(uint32_t interrupt) \arg RTC_FLAG_TP1: RTC tamper 1 detected flag \arg RTC_FLAG_TP0: RTC tamper 0 detected flag \arg RTC_FLAG_TSOVR: time-stamp overflow flag - \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_TS: time-stamp flag \arg RTC_FLAG_ALRM0: alarm0 occurs flag \arg RTC_FLAG_ALRM1: alarm1 occurs flag \arg RTC_FLAG_WT: wakeup timer occurs flag @@ -796,8 +793,8 @@ void rtc_interrupt_disable(uint32_t interrupt) FlagStatus rtc_flag_get(uint32_t flag) { FlagStatus flag_state = RESET; - - if ((uint32_t)RESET != (RTC_STAT & flag)){ + + if((uint32_t)RESET != (RTC_STAT & flag)) { flag_state = SET; } return flag_state; @@ -818,7 +815,7 @@ FlagStatus rtc_flag_get(uint32_t flag) */ void rtc_flag_clear(uint32_t flag) { - RTC_STAT &= (uint32_t)(~flag); + RTC_STAT &= (uint32_t)(~flag); } /*! @@ -856,9 +853,9 @@ void rtc_alarm_output_config(uint32_t source, uint32_t mode) /*! \brief configure rtc calibration output source \param[in] source: specify signal to output - \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 1Hz signal \param[out] none \retval none @@ -876,7 +873,6 @@ void rtc_calibration_output_config(uint32_t source) RTC_WPK = RTC_LOCK_KEY; } - /*! \brief adjust the daylight saving time by adding or substracting one hour from the current time \param[in] operation: hour adjustment operation @@ -890,7 +886,7 @@ void rtc_hour_adjust(uint32_t operation) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + RTC_CTL |= (uint32_t)(operation); /* enable the write protection */ @@ -911,21 +907,21 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) volatile uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; ErrStatus error_status = ERROR; uint32_t flag_status = RESET; - uint32_t temp=0U; + uint32_t temp = 0U; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ - do{ + + /* check if a shift operation is ongoing */ + do { flag_status = RTC_STAT & RTC_STAT_SOPF; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + /* check if the function of reference clock detection is disabled */ temp = RTC_CTL & RTC_CTL_REFEN; - if((RESET == flag_status) && (RESET == temp)){ + if((RESET == flag_status) && (RESET == temp)) { RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); + error_status = rtc_register_sync_wait(); } /* enable the write protection */ @@ -941,7 +937,7 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) \retval none */ void rtc_bypass_shadow_enable(void) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -959,7 +955,7 @@ void rtc_bypass_shadow_enable(void) \retval none */ void rtc_bypass_shadow_disable(void) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -979,7 +975,7 @@ void rtc_bypass_shadow_disable(void) ErrStatus rtc_refclock_detection_enable(void) { ErrStatus error_status = ERROR; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -987,7 +983,7 @@ ErrStatus rtc_refclock_detection_enable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL |= (uint32_t)RTC_CTL_REFEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1008,7 +1004,7 @@ ErrStatus rtc_refclock_detection_enable(void) ErrStatus rtc_refclock_detection_disable(void) { ErrStatus error_status = ERROR; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -1016,7 +1012,7 @@ ErrStatus rtc_refclock_detection_disable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1038,7 +1034,7 @@ void rtc_wakeup_enable(void) { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; RTC_CTL |= RTC_CTL_WTEN; @@ -1062,13 +1058,13 @@ ErrStatus rtc_wakeup_disable(void) RTC_WPK = RTC_UNLOCK_KEY2; RTC_CTL &= ~RTC_CTL_WTEN; /* wait until the WTWF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { error_status = SUCCESS; } /* enable the write protection */ @@ -1079,12 +1075,12 @@ ErrStatus rtc_wakeup_disable(void) /*! \brief set RTC auto wakeup timer clock \param[in] wakeup_clock: - \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 - \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 - \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 - \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 + \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 + \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 + \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 + \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 \arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre - \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 + \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 \param[out] none \retval ErrStatus: ERROR or SUCCESS */ @@ -1095,23 +1091,23 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) uint32_t flag_status = RESET; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS; RTC_CTL |= (uint32_t)wakeup_clock; error_status = SUCCESS; } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - + return error_status; } @@ -1130,13 +1126,13 @@ ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; /* wait until the WTWF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { RTC_WUT = (uint32_t)wakeup_timer; error_status = SUCCESS; } @@ -1151,7 +1147,7 @@ ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) \param[out] none \retval wakeup timer value */ - uint16_t rtc_wakeup_timer_get(void) +uint16_t rtc_wakeup_timer_get(void) { return (uint16_t)RTC_WUT; } @@ -1174,17 +1170,17 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t volatile uint32_t time_index = RTC_HRFC_TIMEOUT; ErrStatus error_status = ERROR; uint32_t flag_status = RESET; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a smooth calibration operation is ongoing */ - do{ + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a smooth calibration operation is ongoing */ + do { flag_status = RTC_STAT & RTC_STAT_SCPF; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET == flag_status){ + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET == flag_status) { RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); error_status = SUCCESS; } @@ -1210,12 +1206,12 @@ ErrStatus rtc_coarse_calibration_enable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL |= (uint32_t)RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; return error_status; @@ -1232,24 +1228,24 @@ ErrStatus rtc_coarse_calibration_disable(void) ErrStatus error_status = ERROR; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; + RTC_WPK = RTC_LOCK_KEY; return error_status; } /*! \brief config coarse calibration direction and step - \param[in] direction: CALIB_INCREASE or CALIB_DECREASE + \param[in] direction: CALIB_INCREASE or CALIB_DECREASE \param[in] step: 0x00-0x1F COSD=0: 0x00:+0 PPM @@ -1272,14 +1268,14 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ - if(CALIB_DECREASE == direction){ + if(ERROR != error_status) { + if(CALIB_DECREASE == direction) { RTC_COSC |= (uint32_t)RTC_COSC_COSD; - }else{ + } else { RTC_COSC &= (uint32_t)~RTC_COSC_COSD; } RTC_COSC &= ~RTC_COSC_COSS; @@ -1287,9 +1283,9 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - + return error_status; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c index fdaae06..a17a56c 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_sdio.c \brief SDIO driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -73,7 +71,7 @@ void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t cloc /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); /* if the clock division is greater or equal to 256, set the DIV[8] */ - if(clock_division >= 256U){ + if(clock_division >= 256U) { clock_config |= SDIO_CLKCTL_DIV8; clock_division -= 256U; } @@ -262,7 +260,7 @@ uint8_t sdio_command_index_get(void) uint32_t sdio_response_get(uint32_t sdio_responsex) { uint32_t resp_content = 0U; - switch(sdio_responsex){ + switch(sdio_responsex) { case SDIO_RESPONSE0: resp_content = SDIO_RESP0; break; @@ -462,7 +460,7 @@ void sdio_dma_disable(void) FlagStatus sdio_flag_get(uint32_t flag) { FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ + if(RESET != (SDIO_STAT & flag)) { temp_flag = SET; } return temp_flag; @@ -599,7 +597,7 @@ void sdio_interrupt_disable(uint32_t int_flag) FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) { FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & int_flag)){ + if(RESET != (SDIO_STAT & int_flag)) { temp_flag = SET; } return temp_flag; @@ -685,9 +683,9 @@ void sdio_stop_readwait_disable(void) */ void sdio_readwait_type_set(uint32_t readwait_type) { - if(SDIO_READWAITTYPE_CLK == readwait_type){ + if(SDIO_READWAITTYPE_CLK == readwait_type) { SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ + } else { SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c index 2ee9c86..456ae2a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c @@ -2,35 +2,33 @@ \file gd32f4xx_spi.c \brief SPI driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -47,14 +45,14 @@ OF SUCH DAMAGE. #define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ /*! - \brief deinitialize SPI and I2S + \brief deinitialize SPI and I2S \param[in] spi_periph: SPIx(x=0,1,2,3,4,5),include I2S1_ADD and I2S2_ADD \param[out] none \retval none */ void spi_i2s_deinit(uint32_t spi_periph) { - switch(spi_periph){ + switch(spi_periph) { case SPI0: /* reset SPI0 */ rcu_periph_reset_enable(RCU_SPI0RST); @@ -91,7 +89,7 @@ void spi_i2s_deinit(uint32_t spi_periph) } /*! - \brief initialize the parameters of SPI struct with default values + \brief initialize the parameters of SPI struct with default values \param[in] none \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer \retval none @@ -108,7 +106,7 @@ void spi_struct_para_init(spi_parameter_struct *spi_struct) spi_struct->endian = SPI_ENDIAN_MSB; } /*! - \brief initialize SPI parameter + \brief initialize SPI parameter \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_struct: SPI parameter initialization stuct members of the structure and the member values are shown as below: @@ -124,8 +122,8 @@ void spi_struct_para_init(spi_parameter_struct *spi_struct) \param[out] none \retval none */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +{ uint32_t reg = 0U; reg = SPI_CTL0(spi_periph); reg &= SPI_INIT_MASK; @@ -152,7 +150,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) } /*! - \brief enable SPI + \brief enable SPI \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -163,7 +161,7 @@ void spi_enable(uint32_t spi_periph) } /*! - \brief disable SPI + \brief disable SPI \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -174,7 +172,7 @@ void spi_disable(uint32_t spi_periph) } /*! - \brief initialize I2S parameter + \brief initialize I2S parameter \param[in] spi_periph: SPIx(x=1,2) \param[in] i2s_mode: I2S operation mode only one parameter can be selected which is shown as below: @@ -198,12 +196,12 @@ void spi_disable(uint32_t spi_periph) */ void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) { - uint32_t reg= 0U; + uint32_t reg = 0U; reg = SPI_I2SCTL(spi_periph); reg &= I2S_INIT_MASK; /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; /* select I2S mode */ reg |= (uint32_t)i2s_mode; /* select I2S standard */ @@ -216,7 +214,7 @@ void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uin } /*! - \brief configure I2S prescale + \brief configure I2S prescale \param[in] spi_periph: SPIx(x=1,2) \param[in] i2s_audiosample: I2S audio sample rate only one parameter can be selected which is shown as below: @@ -249,7 +247,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ uint32_t i2sclock = 0U; #ifndef I2S_EXTERNAL_CLOCK_IN - uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; + uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; #endif /* I2S_EXTERNAL_CLOCK_IN */ /* deinit SPI_I2SPSC register */ @@ -280,25 +278,23 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ /* get the RCU_PLLI2S_PLLI2SR value */ plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28); - if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) - { - /* get the I2S source clock value */ - i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); - } - else - { /* get the I2S source clock value */ - i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); + if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); + } else { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); } #endif /* I2S_EXTERNAL_CLOCK_IN */ /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == i2s_mckout){ + if(I2S_MCKOUT_ENABLE == i2s_mckout) { clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / i2s_audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / i2s_audiosample); } } /* remove the floating point */ @@ -308,7 +304,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ i2sof = (i2sof << 8U); /* set the default values */ - if((i2sdiv< 2U) || (i2sdiv > 255U)){ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { i2sdiv = 2U; i2sof = 0U; } @@ -317,13 +313,13 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN|SPI_I2SCTL_CHLEN)); + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); /* configure data frame format */ SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; } /*! - \brief enable I2S + \brief enable I2S \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none @@ -334,7 +330,7 @@ void i2s_enable(uint32_t spi_periph) } /*! - \brief disable I2S + \brief disable I2S \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none @@ -345,7 +341,7 @@ void i2s_disable(uint32_t spi_periph) } /*! - \brief enable SPI nss output + \brief enable SPI nss output \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -356,7 +352,7 @@ void spi_nss_output_enable(uint32_t spi_periph) } /*! - \brief disable SPI nss output + \brief disable SPI nss output \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -367,7 +363,7 @@ void spi_nss_output_disable(uint32_t spi_periph) } /*! - \brief SPI nss pin high level in software mode + \brief SPI nss pin high level in software mode \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -378,7 +374,7 @@ void spi_nss_internal_high(uint32_t spi_periph) } /*! - \brief SPI nss pin low level in software mode + \brief SPI nss pin low level in software mode \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -389,7 +385,7 @@ void spi_nss_internal_low(uint32_t spi_periph) } /*! - \brief enable SPI DMA send or receive + \brief enable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_dma: SPI DMA mode only one parameter can be selected which is shown as below: @@ -400,15 +396,15 @@ void spi_nss_internal_low(uint32_t spi_periph) */ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) { - if(SPI_DMA_TRANSMIT == spi_dma){ + if(SPI_DMA_TRANSMIT == spi_dma) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ + } else { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; } } /*! - \brief diable SPI DMA send or receive + \brief diable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_dma: SPI DMA mode only one parameter can be selected which is shown as below: @@ -419,15 +415,15 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) */ void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) { - if(SPI_DMA_TRANSMIT == spi_dma){ + if(SPI_DMA_TRANSMIT == spi_dma) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ + } else { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); } } /*! - \brief configure SPI/I2S data frame format + \brief configure SPI/I2S data frame format \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] frame_format: SPI frame size only one parameter can be selected which is shown as below: @@ -445,7 +441,7 @@ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format } /*! - \brief SPI transmit data + \brief SPI transmit data \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] data: 16-bit data \param[out] none @@ -457,7 +453,7 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) } /*! - \brief SPI receive data + \brief SPI receive data \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval 16-bit data @@ -468,7 +464,7 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) } /*! - \brief configure SPI bidirectional transfer direction + \brief configure SPI bidirectional transfer direction \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] transfer_direction: SPI transfer direction only one parameter can be selected which is shown as below: @@ -478,30 +474,99 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) { - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { /* set the transmit only mode */ SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ + } else { /* set the receive only mode */ SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; } } /*! - \brief set SPI CRC polynomial + \brief configure i2s full duplex mode + \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) + \param[in] i2s_mode: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[in] i2s_frameformat: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[out] none + \retval none +*/ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, + uint32_t i2s_ckpl, uint32_t i2s_frameformat) +{ + uint32_t reg = 0U, tmp = 0U; + + reg = I2S_ADD_I2SCTL(i2s_add_periph); + reg &= I2S_FULL_DUPLEX_MASK; + + /* get the mode of the extra I2S module I2Sx_ADD */ + if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)) { + tmp = I2S_MODE_SLAVERX; + } else { + tmp = I2S_MODE_SLAVETX; + } + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)tmp; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + /* configure data frame format */ + reg |= (uint32_t)i2s_frameformat; + + /* write to SPI_I2SCTL register */ + I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; +} + +/*! + \brief clear SPI/I2S format error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] flag: SPI/I2S frame format error flag + \arg SPI_FLAG_FERR: only for SPI work in TI mode + \arg I2S_FLAG_FERR: for I2S + \param[out] none + \retval none +*/ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag) +{ + SPI_STAT(spi_periph) = (uint32_t)(~flag); +} + +/*! + \brief set SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] crc_poly: CRC polynomial value \param[out] none \retval none */ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) { /* set SPI CRC polynomial */ SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; } /*! - \brief get SPI CRC polynomial + \brief get SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval 16-bit CRC polynomial @@ -512,7 +577,7 @@ uint16_t spi_crc_polynomial_get(uint32_t spi_periph) } /*! - \brief turn on CRC function + \brief turn on SPI CRC function \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -523,7 +588,7 @@ void spi_crc_on(uint32_t spi_periph) } /*! - \brief turn off CRC function + \brief turn off SPI CRC function \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -534,7 +599,7 @@ void spi_crc_off(uint32_t spi_periph) } /*! - \brief SPI next data is CRC value + \brief SPI next data is CRC value \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -545,7 +610,7 @@ void spi_crc_next(uint32_t spi_periph) } /*! - \brief get SPI CRC send value or receive value + \brief get SPI CRC send value or receive value \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_crc: SPI crc value only one parameter can be selected which is shown as below: @@ -554,160 +619,147 @@ void spi_crc_next(uint32_t spi_periph) \param[out] none \retval 16-bit CRC value */ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc) +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc) { - if(SPI_CRC_TX == spi_crc){ + if(SPI_CRC_TX == spi_crc) { return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ + } else { return ((uint16_t)(SPI_RCRC(spi_periph))); } } /*! - \brief enable SPI TI mode + \brief clear SPI CRC error flag status \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none */ -void spi_ti_mode_enable(uint32_t spi_periph) +void spi_crc_error_clear(uint32_t spi_periph) { - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; + SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR); } /*! - \brief disable SPI TI mode + \brief enable SPI TI mode \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none */ -void spi_ti_mode_disable(uint32_t spi_periph) +void spi_ti_mode_enable(uint32_t spi_periph) { - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; } /*! - \brief configure i2s full duplex mode - \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) - \param[in] i2s_mode: - \arg I2S_MODE_SLAVETX : I2S slave transmit mode - \arg I2S_MODE_SLAVERX : I2S slave receive mode - \arg I2S_MODE_MASTERTX : I2S master transmit mode - \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_standard: - \arg I2S_STD_PHILLIPS : I2S phillips standard - \arg I2S_STD_MSB : I2S MSB standard - \arg I2S_STD_LSB : I2S LSB standard - \arg I2S_STD_PCMSHORT : I2S PCM short standard - \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: - \arg I2S_CKPL_LOW : I2S clock polarity low level - \arg I2S_CKPL_HIGH : I2S clock polarity high level - \param[in] i2s_frameformat: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, - uint32_t i2s_ckpl, uint32_t i2s_frameformat) +void spi_ti_mode_disable(uint32_t spi_periph) { - uint32_t reg = 0U, tmp = 0U; - - reg = I2S_ADD_I2SCTL(i2s_add_periph); - reg &= I2S_FULL_DUPLEX_MASK; - - /* get the mode of the extra I2S module I2Sx_ADD */ - if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){ - tmp = I2S_MODE_SLAVERX; - }else{ - tmp = I2S_MODE_SLAVETX; - } - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)tmp; - /* select I2S standard */ - reg |= (uint32_t)i2s_standard; - /* select I2S polarity */ - reg |= (uint32_t)i2s_ckpl; - /* configure data frame format */ - reg |= (uint32_t)i2s_frameformat; - - /* write to SPI_I2SCTL register */ - I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); } /*! - \brief enable quad wire SPI + \brief enable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none */ -void qspi_enable(uint32_t spi_periph) +void spi_quad_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; } /*! - \brief disable quad wire SPI + \brief disable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none */ -void qspi_disable(uint32_t spi_periph) +void spi_quad_disable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); } /*! - \brief enable quad wire SPI write + \brief enable quad wire SPI write \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none */ -void qspi_write_enable(uint32_t spi_periph) +void spi_quad_write_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); } /*! - \brief enable quad wire SPI read + \brief enable quad wire SPI read \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none */ -void qspi_read_enable(uint32_t spi_periph) +void spi_quad_read_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; } /*! - \brief enable SPI_IO2 and SPI_IO3 pin output + \brief enable SPI_IO2 and SPI_IO3 pin output \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none */ -void qspi_io23_output_enable(uint32_t spi_periph) +void spi_quad_io23_output_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; } - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none */ - void qspi_io23_output_disable(uint32_t spi_periph) +void spi_quad_io23_output_disable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); } /*! - \brief enable SPI and I2S interrupt + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + only one parameter can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(SPI_STAT(spi_periph) & flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief enable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_i2s_int: SPI/I2S interrupt only one parameter can be selected which is shown as below: @@ -718,9 +770,9 @@ void qspi_io23_output_enable(uint32_t spi_periph) \param[out] none \retval none */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) { - switch(spi_i2s_int){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE: SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; @@ -739,7 +791,7 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) } /*! - \brief disable SPI and I2S interrupt + \brief disable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_i2s_int: SPI/I2S interrupt only one parameter can be selected which is shown as below: @@ -750,9 +802,9 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) \param[out] none \retval none */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) { - switch(spi_i2s_int){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE : SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); @@ -771,9 +823,10 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) } /*! - \brief get SPI and I2S interrupt flag status + \brief get SPI and I2S interrupt flag status \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_i2s_int: SPI/I2S interrupt flag status + only one parameter can be selected which are shown as below: \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag @@ -784,12 +837,12 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) { uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph); - switch(spi_i2s_int){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_FLAG_TBE : reg1 = reg1 & SPI_STAT_TBE; @@ -829,51 +882,9 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) break; } /*get SPI/I2S interrupt flag status */ - if(reg1 && reg2){ + if(reg1 && reg2) { return SET; - }else{ + } else { return RESET; } } - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_flag: SPI/I2S flag status - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) -{ - if(SPI_STAT(spi_periph) & spi_i2s_flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c index 4bd5bf8..bd16d61 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_syscfg.c \brief SYSCFG driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -49,7 +47,7 @@ void syscfg_deinit(void) } /*! - \brief configure the boot mode + \brief configure the boot mode \param[in] syscfg_bootmode: selects the memory remapping only one parameter can be selected which is shown as below: \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 @@ -120,7 +118,7 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); - switch(exti_pin/EXTI_SS_JSTEP){ + switch(exti_pin / EXTI_SS_JSTEP) { case EXTISS0: /* clear EXTI source line(0..3) */ SYSCFG_EXTISS0 &= clear_exti_mask; @@ -155,14 +153,14 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) \param[in] syscfg_enet_phy_interface: specifies the media interface mode. only one parameter can be selected which is shown as below: \arg SYSCFG_ENET_PHY_MII: MII mode is selected - \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected + \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected \param[out] none \retval none */ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) -{ +{ uint32_t reg; - + reg = SYSCFG_CFG1; /* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */ reg &= ~SYSCFG_CFG1_ENET_PHY_SEL; @@ -178,7 +176,7 @@ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) \param[out] none \retval none */ -void syscfg_compensation_config(uint32_t syscfg_compensation) +void syscfg_compensation_config(uint32_t syscfg_compensation) { uint32_t reg; @@ -196,9 +194,9 @@ void syscfg_compensation_config(uint32_t syscfg_compensation) */ FlagStatus syscfg_flag_get(void) { - if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){ + if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) { return SET; - }else{ + } else { return RESET; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c index 02b5194..a25e7b1 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c @@ -2,35 +2,33 @@ \file gd32f4xx_timer.c \brief TIMER driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -38,14 +36,14 @@ OF SUCH DAMAGE. #include "gd32f4xx_timer.h" /*! - \brief deinit a TIMER + \brief deinit a TIMER \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none */ void timer_deinit(uint32_t timer_periph) { - switch(timer_periph){ + switch(timer_periph) { case TIMER0: /* reset TIMER0 */ rcu_periph_reset_enable(RCU_TIMER0RST); @@ -122,12 +120,12 @@ void timer_deinit(uint32_t timer_periph) } /*! - \brief initialize TIMER init parameter struct with a default value + \brief initialize TIMER init parameter struct with a default value \param[in] initpara: init parameter struct \param[out] none \retval none */ -void timer_struct_para_init(timer_parameter_struct* initpara) +void timer_struct_para_init(timer_parameter_struct *initpara) { /* initialize the init parameter struct member with the default value */ initpara->prescaler = 0U; @@ -139,7 +137,7 @@ void timer_struct_para_init(timer_parameter_struct* initpara) } /*! - \brief initialize TIMER counter + \brief initialize TIMER counter \param[in] timer_periph: TIMERx(x=0..13) \param[in] initpara: init parameter struct prescaler: prescaler value of the counter clock,0~65535 @@ -151,15 +149,15 @@ void timer_struct_para_init(timer_parameter_struct* initpara) \param[out] none \retval none */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) { /* configure the counter prescaler value */ TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; /* configure the counter direction and aligned mode */ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) - || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; } @@ -167,13 +165,13 @@ void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) /* configure the autoreload value */ TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { /* reset the CKDIV bit */ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; } - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* configure the repetition counter value */ TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; } @@ -183,7 +181,7 @@ void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) } /*! - \brief enable a TIMER + \brief enable a TIMER \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none @@ -194,7 +192,7 @@ void timer_enable(uint32_t timer_periph) } /*! - \brief disable a TIMER + \brief disable a TIMER \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none @@ -205,7 +203,7 @@ void timer_disable(uint32_t timer_periph) } /*! - \brief enable the auto reload shadow function + \brief enable the auto reload shadow function \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none @@ -216,7 +214,7 @@ void timer_auto_reload_shadow_enable(uint32_t timer_periph) } /*! - \brief disable the auto reload shadow function + \brief disable the auto reload shadow function \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none @@ -227,7 +225,7 @@ void timer_auto_reload_shadow_disable(uint32_t timer_periph) } /*! - \brief enable the update event + \brief enable the update event \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none @@ -238,7 +236,7 @@ void timer_update_event_enable(uint32_t timer_periph) } /*! - \brief disable the update event + \brief disable the update event \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval none @@ -249,7 +247,7 @@ void timer_update_event_disable(uint32_t timer_periph) } /*! - \brief set TIMER counter alignment mode + \brief set TIMER counter alignment mode \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] aligned: only one parameter can be selected which is shown as below: @@ -267,7 +265,7 @@ void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) } /*! - \brief set TIMER counter up direction + \brief set TIMER counter up direction \param[in] timer_periph: TIMERx(x=0..4,7) \param[out] none \retval none @@ -278,7 +276,7 @@ void timer_counter_up_direction(uint32_t timer_periph) } /*! - \brief set TIMER counter down direction + \brief set TIMER counter down direction \param[in] timer_periph: TIMERx(x=0..4,7) \param[out] none \retval none @@ -289,7 +287,7 @@ void timer_counter_down_direction(uint32_t timer_periph) } /*! - \brief configure TIMER prescaler + \brief configure TIMER prescaler \param[in] timer_periph: TIMERx(x=0..13) \param[in] prescaler: prescaler value,0~65535 \param[in] pscreload: prescaler reload mode @@ -302,14 +300,14 @@ void timer_counter_down_direction(uint32_t timer_periph) void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) { TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ + + if(TIMER_PSC_RELOAD_NOW == pscreload) { TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } } /*! - \brief configure TIMER repetition register value + \brief configure TIMER repetition register value \param[in] timer_periph: TIMERx(x=0,7) \param[in] repetition: the counter repetition value,0~255 \param[out] none @@ -318,38 +316,38 @@ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t p void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) { TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - +} + /*! - \brief configure TIMER autoreload register value + \brief configure TIMER autoreload register value \param[in] timer_periph: TIMERx(x=0..13) \param[in] autoreload: the counter auto-reload value \param[out] none \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) { TIMER_CAR(timer_periph) = (uint32_t)autoreload; } /*! - \brief configure TIMER counter register value + \brief configure TIMER counter register value \param[in] timer_periph: TIMERx(x=0..13) \param[in] counter: the counter value,0~65535 \param[out] none \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) { TIMER_CNT(timer_periph) = (uint32_t)counter; } /*! - \brief read TIMER counter value + \brief read TIMER counter value \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval counter value -*/ +*/ uint32_t timer_counter_read(uint32_t timer_periph) { uint32_t count_value = 0U; @@ -358,11 +356,11 @@ uint32_t timer_counter_read(uint32_t timer_periph) } /*! - \brief read TIMER prescaler value + \brief read TIMER prescaler value \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval prescaler register value -*/ +*/ uint16_t timer_prescaler_read(uint32_t timer_periph) { uint16_t prescaler_value = 0U; @@ -371,7 +369,7 @@ uint16_t timer_prescaler_read(uint32_t timer_periph) } /*! - \brief configure TIMER single pulse mode + \brief configure TIMER single pulse mode \param[in] timer_periph: TIMERx(x=0..8,11) \param[in] spmode: only one parameter can be selected which is shown as below: @@ -382,17 +380,17 @@ uint16_t timer_prescaler_read(uint32_t timer_periph) */ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) { - if(TIMER_SP_MODE_SINGLE == spmode){ + if(TIMER_SP_MODE_SINGLE == spmode) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ + } else { /* illegal parameters */ } } /*! - \brief configure TIMER update source + \brief configure TIMER update source \param[in] timer_periph: TIMERx(x=0..13) \param[in] update: only one parameter can be selected which is shown as below: @@ -403,161 +401,17 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) */ void timer_update_source_config(uint32_t timer_periph, uint32_t update) { - if(TIMER_UPDATE_SRC_REGULAR == update){ + if(TIMER_UPDATE_SRC_REGULAR == update) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ + } else { /* illegal parameters */ } } /*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source enable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); -} - -/*! - \brief enable the TIMER DMA + \brief enable the TIMER DMA \param[in] timer_periph: please refer to the following parameters \param[in] dma: specify which DMA to enable one or more parameters can be selected which is shown as below: @@ -573,11 +427,11 @@ void timer_flag_clear(uint32_t timer_periph, uint32_t flag) */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; } /*! - \brief disable the TIMER DMA + \brief disable the TIMER DMA \param[in] timer_periph: please refer to the following parameters \param[in] dma: specify which DMA to disable one or more parameters can be selected which are shown as below: @@ -593,32 +447,32 @@ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) */ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); } /*! - \brief channel DMA request source selection + \brief channel DMA request source selection \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] dma_request: channel DMA request source selection only one parameter can be selected which is shown as below: \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs \param[out] none \retval none */ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) { - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ + } else { /* illegal parameters */ } } /*! - \brief configure the TIMER DMA transfer + \brief configure the TIMER DMA transfer \param[in] timer_periph: please refer to the following parameters \param[in] dma_baseaddr: only one parameter can be selected which is shown as below: @@ -655,16 +509,16 @@ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uin } /*! - \brief software generate events + \brief software generate events \param[in] timer_periph: please refer to the following parameters \param[in] event: the timer software event generation sources one or more parameters can be selected which are shown as below: \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) \param[out] none @@ -676,12 +530,12 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event) } /*! - \brief initialize TIMER break parameter struct with a default value + \brief initialize TIMER break parameter struct \param[in] breakpara: TIMER break parameter struct \param[out] none \retval none */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) { /* initialize the break parameter struct member with the default value */ breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; @@ -694,7 +548,7 @@ void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) } /*! - \brief configure TIMER break function + \brief configure TIMER break function \param[in] timer_periph: TIMERx(x=0,7) \param[in] breakpara: TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE @@ -707,19 +561,19 @@ void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) \param[out] none \retval none */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) { - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime))| - ((uint32_t)(breakpara->breakpolarity))| + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode))| + ((uint32_t)(breakpara->protectmode)) | ((uint32_t)(breakpara->breakstate))) ; } /*! - \brief enable TIMER break function + \brief enable TIMER break function \param[in] timer_periph: TIMERx(x=0,7) \param[out] none \retval none @@ -730,7 +584,7 @@ void timer_break_enable(uint32_t timer_periph) } /*! - \brief disable TIMER break function + \brief disable TIMER break function \param[in] timer_periph: TIMERx(x=0,7) \param[out] none \retval none @@ -741,7 +595,7 @@ void timer_break_disable(uint32_t timer_periph) } /*! - \brief enable TIMER output automatic function + \brief enable TIMER output automatic function \param[in] timer_periph: TIMERx(x=0,7) \param[out] none \retval none @@ -752,7 +606,7 @@ void timer_automatic_output_enable(uint32_t timer_periph) } /*! - \brief disable TIMER output automatic function + \brief disable TIMER output automatic function \param[in] timer_periph: TIMERx(x=0,7) \param[out] none \retval none @@ -763,7 +617,7 @@ void timer_automatic_output_disable(uint32_t timer_periph) } /*! - \brief configure TIMER primary output function + \brief configure TIMER primary output function \param[in] timer_periph: TIMERx(x=0,7) \param[in] newvalue: ENABLE or DISABLE \param[out] none @@ -771,57 +625,57 @@ void timer_automatic_output_disable(uint32_t timer_periph) */ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ + } else { TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); } } /*! - \brief enable or disable channel capture/compare control shadow register + \brief enable or disable channel capture/compare control shadow register \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE + \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ + } else { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); } } /*! - \brief configure TIMER channel control shadow register update control + \brief configure TIMER channel control shadow register update control \param[in] timer_periph: TIMERx(x=0,7) \param[in] ccuctl: channel control shadow register update control only one parameter can be selected which is shown as below: \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs \param[out] none \retval none -*/ +*/ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) { - if(TIMER_UPDATECTL_CCU == ccuctl){ + if(TIMER_UPDATECTL_CCU == ccuctl) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ + } else { /* illegal parameters */ } } /*! - \brief initialize TIMER channel output parameter struct with a default value + \brief initialize TIMER channel output parameter struct with a default value \param[in] ocpara: TIMER channel n output parameter struct \param[out] none \retval none */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) { /* initialize the channel output parameter struct member with the default value */ ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; @@ -833,7 +687,7 @@ void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) } /*! - \brief configure TIMER channel output function + \brief configure TIMER channel output function \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -851,9 +705,9 @@ void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) \param[out] none \retval none */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -866,7 +720,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH0P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH0NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); /* set the CH0NEN bit */ @@ -897,7 +751,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH1P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH1NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); /* set the CH1NEN bit */ @@ -928,7 +782,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH2P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH2NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); /* set the CH2NEN bit */ @@ -950,7 +804,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); @@ -959,7 +813,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH3P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the ISO3 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); /* set the ISO3 bit */ @@ -972,7 +826,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ } /*! - \brief configure TIMER channel output compare mode + \brief configure TIMER channel output compare mode \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -995,7 +849,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ */ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); @@ -1022,7 +876,7 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u } /*! - \brief configure TIMER channel output pulse value + \brief configure TIMER channel output pulse value \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -1036,7 +890,7 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u */ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CH0CV(timer_periph) = (uint32_t)pulse; @@ -1051,7 +905,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha break; /* configure TIMER_CH_3 */ case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; break; default: break; @@ -1059,7 +913,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha } /*! - \brief configure TIMER channel output shadow function + \brief configure TIMER channel output shadow function \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -1076,7 +930,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha */ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); @@ -1103,7 +957,7 @@ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, } /*! - \brief configure TIMER channel output fast function + \brief configure TIMER channel output fast function \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -1120,7 +974,7 @@ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); @@ -1147,9 +1001,9 @@ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, u } /*! - \brief configure TIMER channel output clear function + \brief configure TIMER channel output clear function \param[in] timer_periph: please refer to the following parameters - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7)) @@ -1164,7 +1018,7 @@ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, u */ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); @@ -1191,15 +1045,15 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, } /*! - \brief configure TIMER channel output polarity + \brief configure TIMER channel output polarity \param[in] timer_periph: please refer to the following parameters - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocpolarity: channel output polarity + \param[in] ocpolarity: channel output polarity only one parameter can be selected which is shown as below: \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high \arg TIMER_OC_POLARITY_LOW: channel output polarity is low @@ -1208,7 +1062,7 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); @@ -1235,14 +1089,14 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe } /*! - \brief configure TIMER channel complementary output polarity + \brief configure TIMER channel complementary output polarity \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] ocnpolarity: channel complementary output polarity + \param[in] ocnpolarity: channel complementary output polarity only one parameter can be selected which is shown as below: \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low @@ -1251,7 +1105,7 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe */ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); @@ -1273,9 +1127,9 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, u } /*! - \brief configure TIMER channel enable state + \brief configure TIMER channel enable state \param[in] timer_periph: please refer to the following parameters - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) @@ -1283,14 +1137,14 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, u \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) \param[in] state: TIMER channel enable state only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable \param[out] none \retval none */ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); @@ -1317,23 +1171,23 @@ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, } /*! - \brief configure TIMER channel complementary output enable state + \brief configure TIMER channel complementary output enable state \param[in] timer_periph: TIMERx(x=0,7) - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 \arg TIMER_CH_2: TIMER channel2 \param[in] ocnstate: TIMER channel complementary output enable state only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable \param[out] none \retval none */ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); @@ -1355,12 +1209,12 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint } /*! - \brief initialize TIMER channel input parameter struct with a default value + \brief initialize TIMER channel input parameter struct \param[in] icpara: TIMER channel intput parameter struct \param[out] none \retval none */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) { /* initialize the channel input parameter struct member with the default value */ icpara->icpolarity = TIMER_IC_POLARITY_RISING; @@ -1370,9 +1224,9 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) } /*! - \brief configure TIMER input capture parameter + \brief configure TIMER input capture parameter \param[in] timer_periph: please refer to the following parameters - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) @@ -1386,9 +1240,9 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) \param[out] none \retval none */ -void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -1407,7 +1261,7 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; break; - + /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ @@ -1432,7 +1286,7 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); /* reset the CH2MS bit */ @@ -1474,9 +1328,9 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic } /*! - \brief configure TIMER channel input capture prescaler value + \brief configure TIMER channel input capture prescaler value \param[in] timer_periph: please refer to the following parameters - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) @@ -1493,7 +1347,7 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic */ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); @@ -1520,9 +1374,9 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_ } /*! - \brief read TIMER channel capture compare register value + \brief read TIMER channel capture compare register value \param[in] timer_periph: please refer to the following parameters - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) @@ -1535,7 +1389,7 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 { uint32_t count_value = 0U; - switch(channel){ + switch(channel) { /* read TIMER channel 0 capture compare register value */ case TIMER_CH_0: count_value = TIMER_CH0CV(timer_periph); @@ -1559,9 +1413,9 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 } /*! - \brief configure TIMER input pwm capture function + \brief configure TIMER input pwm capture function \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 @@ -1573,30 +1427,30 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 \param[out] none \retval none */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) { uint16_t icpolarity = 0x0U; uint16_t icselection = 0x0U; /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ + } else { icpolarity = TIMER_IC_POLARITY_RISING; } /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ + } else { icselection = TIMER_IC_SELECTION_DIRECTTI; } - if(TIMER_CH_0 == channel){ + if(TIMER_CH_0 == channel) { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); /* reset the CH0MS bit */ @@ -1610,12 +1464,12 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); /* reset the CH1MS bit */ @@ -1629,12 +1483,12 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); /* reset the CH1MS bit */ @@ -1653,7 +1507,7 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; /* reset the CH0MS bit */ @@ -1672,9 +1526,9 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim } /*! - \brief configure TIMER hall sensor mode + \brief configure TIMER hall sensor mode \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] hallmode: + \param[in] hallmode: only one parameter can be selected which is shown as below: \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable @@ -1683,17 +1537,17 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim */ void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) { - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ + } else { /* illegal parameters */ } } /*! - \brief select TIMER input trigger source + \brief select TIMER input trigger source \param[in] timer_periph: please refer to the following parameters \param[in] intrigger: only one parameter can be selected which is shown as below: @@ -1715,7 +1569,7 @@ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger } /*! - \brief select TIMER master mode output trigger source + \brief select TIMER master mode output trigger source \param[in] timer_periph: TIMERx(x=0..7) \param[in] outrigger: only one parameter can be selected which is shown as below: @@ -1737,14 +1591,14 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o } /*! - \brief select TIMER slave mode + \brief select TIMER slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] slavemode: only one parameter can be selected which is shown as below: \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) - \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2(TIMERx(x=0..4,7)) \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) @@ -1761,7 +1615,7 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) } /*! - \brief configure TIMER master slave mode + \brief configure TIMER master slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] masterslave: only one parameter can be selected which is shown as below: @@ -1769,20 +1623,20 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable \param[out] none \retval none -*/ +*/ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ + } else { /* illegal parameters */ } } /*! - \brief configure TIMER external trigger input + \brief configure TIMER external trigger input \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] extprescaler: only one parameter can be selected which is shown as below: @@ -1807,14 +1661,14 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, } /*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] decomode: + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] decomode: only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: + \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge @@ -1826,21 +1680,21 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, \retval none */ void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, - uint16_t ic0polarity, uint16_t ic1polarity) + uint16_t ic0polarity, uint16_t ic1polarity) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); } /*! - \brief configure TIMER internal clock mode + \brief configure TIMER internal clock mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[out] none \retval none @@ -1851,9 +1705,9 @@ void timer_internal_clock_config(uint32_t timer_periph) } /*! - \brief configure TIMER the internal trigger as external clock input + \brief configure TIMER the internal trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: + \param[in] intrigger: only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 @@ -1870,14 +1724,14 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint } /*! - \brief configure TIMER the external trigger as external clock input + \brief configure TIMER the external trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extrigger: + \param[in] extrigger: only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: + \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: active high or rising edge active \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active @@ -1886,13 +1740,13 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint \retval none */ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, - uint16_t extpolarity, uint32_t extfilter) + uint16_t extpolarity, uint32_t extfilter) { - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); /* reset the CH1MS bit */ @@ -1905,11 +1759,11 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ + } else { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; /* reset the CH0MS bit */ @@ -1924,7 +1778,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; } /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); + timer_input_trigger_source_select(timer_periph, extrigger); /* reset the SMC bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); /* set the SMC bit */ @@ -1932,15 +1786,15 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint } /*! - \brief configure TIMER the external clock mode0 + \brief configure TIMER the external clock mode0 \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extprescaler: + \param[in] extprescaler: only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: + \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active @@ -1961,15 +1815,15 @@ void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extpresca } /*! - \brief configure TIMER the external clock mode1 + \brief configure TIMER the external clock mode1 \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: + \param[in] extprescaler: only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: + \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active @@ -1987,7 +1841,7 @@ void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extpresca } /*! - \brief disable TIMER the external clock mode1 + \brief disable TIMER the external clock mode1 \param[in] timer_periph: TIMERx(x=0..4,7) \param[out] none \retval none @@ -1998,9 +1852,9 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) } /*! - \brief configure TIMER channel remap function + \brief configure TIMER channel remap function \param[in] timer_periph: TIMERx(x=1,4,10) - \param[in] remap: + \param[in] remap: only one parameter can be selected which is shown as below: \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP @@ -2009,7 +1863,7 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL - \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt + \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) \param[out] none @@ -2021,9 +1875,9 @@ void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) } /*! - \brief configure TIMER write CHxVAL register selection + \brief configure TIMER write CHxVAL register selection \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) - \param[in] ccsel: + \param[in] ccsel: only one parameter can be selected which is shown as below: \arg TIMER_CHVSEL_DISABLE: no effect \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored @@ -2032,17 +1886,17 @@ void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) */ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) { - if(TIMER_CHVSEL_ENABLE == ccsel){ + if(TIMER_CHVSEL_ENABLE == ccsel) { TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CHVSEL_DISABLE == ccsel){ + } else if(TIMER_CHVSEL_DISABLE == ccsel) { TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - }else{ + } else { /* illegal parameters */ } } /*! - \brief configure TIMER output value selection + \brief configure TIMER output value selection \param[in] timer_periph: TIMERx(x=0,7) \param[in] outsel: only one parameter can be selected which is shown as below: @@ -2053,11 +1907,155 @@ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) */ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) { - if(TIMER_OUTSEL_ENABLE == outsel){ + if(TIMER_OUTSEL_ENABLE == outsel) { TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == outsel){ + } else if(TIMER_OUTSEL_DISABLE == outsel) { TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - }else{ + } else { /* illegal parameters */ } } + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source enable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c index 437df1c..18ed843 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c @@ -1,36 +1,34 @@ /*! \file gd32f4xx_tli.c \brief TLI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,7 +38,7 @@ OF SUCH DAMAGE. #define TLI_OPAQUE_VALUE 0x000000FFU /*! - \brief deinitialize TLI registers + \brief deinitialize TLI registers \param[in] none \param[out] none \retval none @@ -52,7 +50,7 @@ void tli_deinit(void) } /*! - \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested that call this function after a tli_parameter_struct structure is defined \param[in] none \param[out] tli_struct: the data needed to initialize TLI @@ -67,9 +65,9 @@ void tli_deinit(void) backcolor_red: background value red backcolor_green: background value green backcolor_blue: background value blue - signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT - signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT - signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGH + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGH + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGH signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI \retval none */ @@ -94,7 +92,7 @@ void tli_struct_para_init(tli_parameter_struct *tli_struct) } /*! - \brief initialize TLI display timing parameters + \brief initialize TLI display timing parameters \param[in] tli_struct: the data needed to initialize TLI synpsz_vpsz: size of the vertical synchronous pulse synpsz_hpsz: size of the horizontal synchronous pulse @@ -107,9 +105,9 @@ void tli_struct_para_init(tli_parameter_struct *tli_struct) backcolor_red: background value red backcolor_green: background value green backcolor_blue: background value blue - signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT - signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT - signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGH + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGH + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGH signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI \param[out] none \retval none @@ -117,28 +115,28 @@ void tli_struct_para_init(tli_parameter_struct *tli_struct) void tli_init(tli_parameter_struct *tli_struct) { /* synchronous pulse size configuration */ - TLI_SPSZ &= ~(TLI_SPSZ_VPSZ|TLI_SPSZ_HPSZ); - TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz|((uint32_t)tli_struct->synpsz_hpsz<<16U)); + TLI_SPSZ &= ~(TLI_SPSZ_VPSZ | TLI_SPSZ_HPSZ); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz | ((uint32_t)tli_struct->synpsz_hpsz << 16U)); /* back-porch size configuration */ - TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ|TLI_BPSZ_HBPSZ); - TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz|((uint32_t)tli_struct->backpsz_hbpsz<<16U)); - /* active size configuration */ - TLI_ASZ &= ~(TLI_ASZ_VASZ|TLI_ASZ_HASZ); - TLI_ASZ = (tli_struct->activesz_vasz|(tli_struct->activesz_hasz<<16U)); - /* total size configuration */ - TLI_TSZ &= ~(TLI_TSZ_VTSZ|TLI_TSZ_HTSZ); - TLI_TSZ = (tli_struct->totalsz_vtsz|(tli_struct->totalsz_htsz<<16U)); - /* background color configuration */ - TLI_BGC &= ~(TLI_BGC_BVB|(TLI_BGC_BVG)|(TLI_BGC_BVR)); - TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); - TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS|TLI_CTL_DEPS|TLI_CTL_CLKPS); - TLI_CTL |= (tli_struct->signalpolarity_hs|tli_struct->signalpolarity_vs|\ - tli_struct->signalpolarity_de|tli_struct->signalpolarity_pixelck); + TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ); + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U)); + /* active size configuration */ + TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ); + TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U)); + /* total size configuration */ + TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ); + TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U)); + /* background color configuration */ + TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR)); + TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U)); + TLI_CTL &= ~(TLI_CTL_HPPS | TLI_CTL_VPPS | TLI_CTL_DEPS | TLI_CTL_CLKPS); + TLI_CTL |= (tli_struct->signalpolarity_hs | tli_struct->signalpolarity_vs | \ + tli_struct->signalpolarity_de | tli_struct->signalpolarity_pixelck); } /*! - \brief configure TLI dither function + \brief configure TLI dither function \param[in] dither_stat only one parameter can be selected which is shown as below: \arg TLI_DITHER_ENABLE @@ -148,15 +146,15 @@ void tli_init(tli_parameter_struct *tli_struct) */ void tli_dither_config(uint8_t dither_stat) { - if(TLI_DITHER_ENABLE == dither_stat){ + if(TLI_DITHER_ENABLE == dither_stat) { TLI_CTL |= TLI_CTL_DFEN; - }else{ + } else { TLI_CTL &= ~(TLI_CTL_DFEN); } } /*! - \brief enable TLI + \brief enable TLI \param[in] none \param[out] none \retval none @@ -167,7 +165,7 @@ void tli_enable(void) } /*! - \brief disable TLI + \brief disable TLI \param[in] none \param[out] none \retval none @@ -178,7 +176,7 @@ void tli_disable(void) } /*! - \brief configure TLI reload mode + \brief configure TLI reload mode \param[in] reload_mod only one parameter can be selected which is shown as below: \arg TLI_FRAME_BLANK_RELOAD_EN @@ -188,23 +186,23 @@ void tli_disable(void) */ void tli_reload_config(uint8_t reload_mod) { - if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod) { /* the layer configuration will be reloaded at frame blank */ TLI_RL |= TLI_RL_FBR; - }else{ + } else { /* the layer configuration will be reloaded after this bit sets */ TLI_RL |= TLI_RL_RQR; } } /*! - \brief initialize the parameters of TLI layer structure with the default values, it is suggested + \brief initialize the parameters of TLI layer structure with the default values, it is suggested that call this function after a tli_layer_parameter_struct structure is defined \param[in] none \param[out] layer_struct: TLI Layer parameter struct layer_window_rightpos: window right position layer_window_leftpos: window left position - layer_window_bottompos: window bottom position + layer_window_bottompos: window bottom position layer_window_toppos: window top position layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, @@ -244,12 +242,12 @@ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) } /*! - \brief initialize TLI layer + \brief initialize TLI layer \param[in] layerx: LAYERx(x=0,1) \param[in] layer_struct: TLI Layer parameter struct layer_window_rightpos: window right position layer_window_leftpos: window left position - layer_window_bottompos: window bottom position + layer_window_bottompos: window bottom position layer_window_toppos: window top position layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, @@ -268,14 +266,14 @@ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) \param[out] none \retval none */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct) { /* configure layer window horizontal position */ - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos|((uint32_t)layer_struct->layer_window_rightpos<<16U)); + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos | ((uint32_t)layer_struct->layer_window_rightpos << 16U)); /* configure layer window vertical position */ - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos|((uint32_t)layer_struct->layer_window_bottompos<<16U)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos | ((uint32_t)layer_struct->layer_window_bottompos << 16U)); /* configure layer packeted pixel format */ TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); TLI_LxPPF(layerx) = layer_struct->layer_ppf; @@ -283,20 +281,20 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); TLI_LxSA(layerx) = layer_struct->layer_sa; /* configure layer default color */ - TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); - TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue|((uint32_t)layer_struct->layer_default_green<<8U) - |((uint32_t)layer_struct->layer_default_red<<16U) - |((uint32_t)layer_struct->layer_default_alpha<<24U)); + TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB | (TLI_LxDC_DCG) | (TLI_LxDC_DCR) | (TLI_LxDC_DCA)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue | ((uint32_t)layer_struct->layer_default_green << 8U) + | ((uint32_t)layer_struct->layer_default_red << 16U) + | ((uint32_t)layer_struct->layer_default_alpha << 24U)); /* configure layer alpha calculation factors */ - TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); - TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2)|(layer_struct->layer_acf1)); + TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2 | (TLI_LxBLEND_ACF1)); + TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2) | (layer_struct->layer_acf1)); /* configure layer frame buffer base address */ TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); /* configure layer frame line length */ - TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); - TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length|((uint32_t)layer_struct->layer_frame_buf_stride_offset<<16U)); + TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL | (TLI_LxFLLEN_STDOFF)); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length | ((uint32_t)layer_struct->layer_frame_buf_stride_offset << 16U)); /* configure layer frame total line number */ TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); @@ -304,56 +302,56 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) } /*! - \brief reconfigure window position + \brief reconfigure window position \param[in] layerx: LAYERx(x=0,1) \param[in] offset_x: new horizontal offset \param[in] offset_y: new vertical offset \param[out] none \retval none */ -void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y) +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y) { /* configure window start position */ uint32_t layer_ppf, line_num, hstart, vstart; uint32_t line_length = 0U; - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - hstart = (uint32_t)offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); - vstart = (uint32_t)offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + hstart = (uint32_t)offset_x + (((TLI_BPSZ & TLI_BPSZ_HBPSZ) >> 16U) + 1U); + vstart = (uint32_t)offset_y + ((TLI_BPSZ & TLI_BPSZ_VBPSZ) + 1U); line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ - switch(layer_ppf){ + switch(layer_ppf) { case LAYER_PPF_ARGB8888: /* each pixel includes 4bytes, when pixel format is ARGB8888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 4U); break; case LAYER_PPF_RGB888: /* each pixel includes 3bytes, when pixel format is RGB888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 3U); break; case LAYER_PPF_RGB565: case LAYER_PPF_ARGB1555: case LAYER_PPF_ARGB4444: case LAYER_PPF_AL88: /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 2U); break; case LAYER_PPF_L8: case LAYER_PPF_AL44: /* each pixel includes 1byte, when pixel format is L8 or AL44 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U)); break; default: break; } /* reconfigure window position */ - TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); - TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); + TLI_LxHPOS(layerx) = (hstart | ((hstart + line_length - 1U) << 16U)); + TLI_LxVPOS(layerx) = (vstart | ((vstart + line_num - 1U) << 16U)); } /*! - \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested that call this function after a tli_layer_lut_parameter_struct structure is defined \param[in] none \param[out] lut_struct: TLI layer LUT parameter struct @@ -373,7 +371,7 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) } /*! - \brief initialize TLI layer LUT + \brief initialize TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[in] lut_struct: TLI layer LUT parameter struct layer_table_addr: look up table write address @@ -383,29 +381,29 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) \param[out] none \retval none */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct) { - TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue)|((uint32_t)lut_struct->layer_lut_channel_green<<8U) - |((uint32_t)lut_struct->layer_lut_channel_red<<16U - |((uint32_t)lut_struct->layer_table_addr<<24U))); + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U) + | ((uint32_t)lut_struct->layer_lut_channel_red << 16U + | ((uint32_t)lut_struct->layer_table_addr << 24U))); } /*! - \brief initialize TLI layer color key + \brief initialize TLI layer color key \param[in] layerx: LAYERx(x=0,1) \param[in] redkey: color key red - \param[in] greenkey: color key green + \param[in] greenkey: color key green \param[in] bluekey: color key blue \param[out] none \retval none */ -void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey) +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey) { - TLI_LxCKEY(layerx) = (((uint32_t)bluekey)|((uint32_t)greenkey<<8U)|((uint32_t)redkey<<16U)); + TLI_LxCKEY(layerx) = (((uint32_t)bluekey) | ((uint32_t)greenkey << 8U) | ((uint32_t)redkey << 16U)); } /*! - \brief enable TLI layer + \brief enable TLI layer \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -416,7 +414,7 @@ void tli_layer_enable(uint32_t layerx) } /*! - \brief disable TLI layer + \brief disable TLI layer \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -427,7 +425,7 @@ void tli_layer_disable(uint32_t layerx) } /*! - \brief enable TLI layer color keying + \brief enable TLI layer color keying \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -438,7 +436,7 @@ void tli_color_key_enable(uint32_t layerx) } /*! - \brief disable TLI layer color keying + \brief disable TLI layer color keying \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -449,7 +447,7 @@ void tli_color_key_disable(uint32_t layerx) } /*! - \brief enable TLI layer LUT + \brief enable TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -460,7 +458,7 @@ void tli_lut_enable(uint32_t layerx) } /*! - \brief disable TLI layer LUT + \brief disable TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -471,8 +469,8 @@ void tli_lut_disable(uint32_t layerx) } /*! - \brief set line mark value - \param[in] line_num: line number + \brief set line mark value + \param[in] line_num: line number \param[out] none \retval none */ @@ -483,7 +481,7 @@ void tli_line_mark_set(uint16_t line_num) } /*! - \brief get current displayed position + \brief get current displayed position \param[in] none \param[out] none \retval position of current pixel @@ -494,13 +492,13 @@ uint32_t tli_current_pos_get(void) } /*! - \brief enable TLI interrupt + \brief enable TLI interrupt \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: - \arg TLI_INT_LM: line mark interrupt - \arg TLI_INT_FE: FIFO error interrupt - \arg TLI_INT_TE: transaction error interrupt - \arg TLI_INT_LCR: layer configuration reloaded interrupt + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt \param[out] none \retval none */ @@ -510,13 +508,13 @@ void tli_interrupt_enable(uint32_t int_flag) } /*! - \brief disable TLI interrupt + \brief disable TLI interrupt \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: - \arg TLI_INT_LM: line mark interrupt - \arg TLI_INT_FE: FIFO error interrupt - \arg TLI_INT_TE: transaction error interrupt - \arg TLI_INT_LCR: layer configuration reloaded interrupt + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt \param[out] none \retval none */ @@ -526,7 +524,7 @@ void tli_interrupt_disable(uint32_t int_flag) } /*! - \brief get TLI interrupt flag + \brief get TLI interrupt flag \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: \arg TLI_INT_FLAG_LM: line mark interrupt flag @@ -540,9 +538,10 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag) { uint32_t state; state = TLI_INTF; - if(state & int_flag){ + if(state & int_flag) { state = TLI_INTEN; - if(state & int_flag){ + /* check whether the corresponding bit in TLI_INTEN is set or not */ + if(state & int_flag) { return SET; } } @@ -550,7 +549,7 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag) } /*! - \brief clear TLI interrupt flag + \brief clear TLI interrupt flag \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: \arg TLI_INT_FLAG_LM: line mark interrupt flag @@ -566,17 +565,17 @@ void tli_interrupt_flag_clear(uint32_t int_flag) } /*! - \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register \param[in] flag: TLI flags or states only one parameter can be selected which is shown as below: - \arg TLI_FLAG_VDE: current VDE state + \arg TLI_FLAG_VDE: current VDE state \arg TLI_FLAG_HDE: current HDE state \arg TLI_FLAG_VS: current VS status of the TLI \arg TLI_FLAG_HS: current HS status of the TLI \arg TLI_FLAG_LM: line mark interrupt flag \arg TLI_FLAG_FE: FIFO error interrupt flag - \arg TLI_FLAG_TE: transaction error interrupt flag - \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag + \arg TLI_FLAG_TE: transaction error interrupt flag + \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ @@ -584,14 +583,14 @@ FlagStatus tli_flag_get(uint32_t flag) { uint32_t stat; /* choose which register to get flag or state */ - if(flag >> 31U){ + if(flag >> 31U) { stat = TLI_INTF; - }else{ + } else { stat = TLI_STAT; } - if(flag & stat){ + if(flag & stat) { return SET; - }else{ + } else { return RESET; } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c index 040add4..502e97e 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c @@ -2,42 +2,40 @@ \file gd32f4xx_trng.c \brief TRNG driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_trng.h" /*! - \brief deinitialize the TRNG + \brief reset TRNG \param[in] none \param[out] none \retval none @@ -49,7 +47,7 @@ void trng_deinit(void) } /*! - \brief enable the TRNG interface + \brief enable TRNG \param[in] none \param[out] none \retval none @@ -60,7 +58,7 @@ void trng_enable(void) } /*! - \brief disable the TRNG interface + \brief disable TRNG \param[in] none \param[out] none \retval none @@ -71,10 +69,10 @@ void trng_disable(void) } /*! - \brief get the true random data + \brief get the true random data \param[in] none \param[out] none - \retval the generated random data + \retval uint32_t: 0x0-0xFFFFFFFF */ uint32_t trng_get_true_random_data(void) { @@ -82,70 +80,70 @@ uint32_t trng_get_true_random_data(void) } /*! - \brief enable the TRNG interrupt + \brief enable TRNG interrupt \param[in] none \param[out] none \retval none */ -void trng_interrupt_enable(void) +void trng_interrupt_enable(void) { - TRNG_CTL |= TRNG_CTL_IE; + TRNG_CTL |= TRNG_CTL_TRNGIE; } /*! - \brief disable the TRNG interrupt + \brief disable TRNG interrupt \param[in] none \param[out] none \retval none */ void trng_interrupt_disable(void) { - TRNG_CTL &= ~TRNG_CTL_IE; + TRNG_CTL &= ~TRNG_CTL_TRNGIE; } /*! - \brief get the trng status flags - \param[in] flag: trng status flag, refer to trng_flag_enum + \brief get TRNG flag status + \param[in] flag: TRNG flag only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_DRDY: Random Data ready status - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status + \arg TRNG_FLAG_DRDY: random Data ready status + \arg TRNG_FLAG_CECS: clock error current status + \arg TRNG_FLAG_SECS: seed error current status \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus trng_flag_get(trng_flag_enum flag) { - if(RESET != (TRNG_STAT & flag)){ + if(RESET != (TRNG_STAT & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief get the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum + \brief get TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) { - if(RESET != (TRNG_STAT & int_flag)){ + if(RESET != (TRNG_STAT & int_flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum + \brief clear TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag \param[out] none \retval none */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c index 35ab1fd..e69999e 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c @@ -1,40 +1,37 @@ /*! \file gd32f4xx_usart.c \brief USART driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx + + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - #include "gd32f4xx_usart.h" /* USART register bit offset */ @@ -43,14 +40,14 @@ OF SUCH DAMAGE. #define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ /*! - \brief reset USART/UART + \brief reset USART/UART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none */ void usart_deinit(uint32_t usart_periph) { - switch(usart_periph){ + switch(usart_periph) { case USART0: rcu_periph_reset_enable(RCU_USART0RST); rcu_periph_reset_disable(RCU_USART0RST); @@ -94,52 +91,52 @@ void usart_deinit(uint32_t usart_periph) \param[in] baudval: baud rate value \param[out] none \retval none -*/ +*/ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ case USART0: - uclk=rcu_clock_freq_get(CK_APB2); - break; + uclk = rcu_clock_freq_get(CK_APB2); + break; case USART5: - uclk=rcu_clock_freq_get(CK_APB2); - break; + uclk = rcu_clock_freq_get(CK_APB2); + break; case USART1: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case USART2: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART3: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART4: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART6: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART7: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; default: - break; + break; } - if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { /* when oversampling by 8, configure the value of USART_BAUD */ - udiv = ((2U*uclk) + baudval/2U)/baudval; + udiv = ((2U * uclk) + baudval / 2U) / baudval; intdiv = udiv & 0xfff0U; - fradiv = (udiv>>1U) & 0x7U; + fradiv = (udiv >> 1U) & 0x7U; USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - }else{ + } else { /* when oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; + udiv = (uclk + baudval / 2U) / baudval; intdiv = udiv & 0xfff0U; fradiv = udiv & 0xfU; USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } + } } /*! @@ -148,7 +145,7 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) \param[in] paritycfg: configure USART parity only one parameter can be selected which is shown as below: \arg USART_PM_NONE: no parity - \arg USART_PM_EVEN: even parity + \arg USART_PM_EVEN: even parity \arg USART_PM_ODD: odd parity \param[out] none \retval none @@ -157,7 +154,7 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) { /* clear USART_CTL0 PM,PCEN Bits */ USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ + /* configure USART parity mode */ USART_CTL0(usart_periph) |= paritycfg ; } @@ -194,7 +191,7 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) { /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; /* configure USART stop bits */ USART_CTL1(usart_periph) |= stblen; } @@ -233,7 +230,7 @@ void usart_disable(uint32_t usart_periph) void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_TEN; ctl |= txconfig; @@ -254,7 +251,7 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_REN; ctl |= rxconfig; @@ -275,12 +272,12 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) { uint32_t ctl = 0U; - + ctl = USART_CTL3(usart_periph); - ctl &= ~(USART_CTL3_MSBF); + ctl &= ~(USART_CTL3_MSBF); ctl |= msbf; /* configure data transmitted/received mode */ - USART_CTL3(usart_periph) = ctl; + USART_CTL3(usart_periph) = ctl; } /*! @@ -299,8 +296,8 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) */ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) { - /* inverted or not the specified siginal */ - switch(invertpara){ + /* inverted or not the specified siginal */ + switch(invertpara) { case USART_DINV_ENABLE: USART_CTL3(usart_periph) |= USART_CTL3_DINV; break; @@ -325,7 +322,7 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) } /*! - \brief configure the USART oversample mode + \brief configure the USART oversample mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] oversamp: oversample value only one parameter can be selected which is shown as below: @@ -353,7 +350,7 @@ void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) */ void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) { - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); USART_CTL2(usart_periph) |= obsm; } @@ -395,13 +392,13 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti /*! \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) +void usart_data_transmit(uint32_t usart_periph, uint16_t data) { - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); + USART_DATA(usart_periph) = USART_DATA_DATA & (uint32_t)data; } /*! @@ -425,7 +422,7 @@ uint16_t usart_data_receive(uint32_t usart_periph) void usart_address_config(uint32_t usart_periph, uint8_t addr) { USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (uint32_t)addr); } /*! @@ -473,7 +470,7 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) \retval none */ void usart_lin_mode_enable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) |= USART_CTL1_LMEN; } @@ -484,7 +481,7 @@ void usart_lin_mode_enable(uint32_t usart_periph) \retval none */ void usart_lin_mode_disable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); } @@ -522,7 +519,7 @@ void usart_send_break(uint32_t usart_periph) \retval none */ void usart_halfduplex_enable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) |= USART_CTL2_HDEN; } @@ -533,7 +530,7 @@ void usart_halfduplex_enable(uint32_t usart_periph) \retval none */ void usart_halfduplex_disable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); } @@ -564,30 +561,23 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] clen: CK length only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame \param[in] cph: clock phase only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_1CK: first clock transition is the first data capture edge \arg USART_CPH_2CK: second clock transition is the first data capture edge \param[in] cpl: clock polarity only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_LOW: steady low value on CK pin \arg USART_CPL_HIGH: steady high value on CK pin \param[out] none \retval none */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); } /*! @@ -597,10 +587,10 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32 \param[out] none \retval none */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<packet_receive = 0U; cdc->packet_sent = 0U; - usbd_ep_recev(udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + usbd_ep_recev (udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); } /*! @@ -343,13 +342,13 @@ static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) { static __ALIGN_BEGIN usb_cdc_handler cdc_handler __ALIGN_END; - /* initialize the data TX endpoint */ + /* initialize the data Tx endpoint */ usbd_ep_setup (udev, &(cdc_config_desc.cdc_in_endpoint)); - /* initialize the data RX endpoint */ + /* initialize the data Rx endpoint */ usbd_ep_setup (udev, &(cdc_config_desc.cdc_out_endpoint)); - /* initialize the command TX endpoint */ + /* initialize the command Tx endpoint */ usbd_ep_setup (udev, &(cdc_config_desc.cdc_cmd_endpoint)); /* initialize CDC handler structure */ @@ -378,11 +377,11 @@ static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) */ static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index) { - /* deinitialize the data TX/RX endpoint */ + /* deinitialize the data Tx/Rx endpoint */ usbd_ep_clear (udev, CDC_DATA_IN_EP); usbd_ep_clear (udev, CDC_DATA_OUT_EP); - /* deinitialize the command TX endpoint */ + /* deinitialize the command Tx endpoint */ usbd_ep_clear (udev, CDC_CMD_EP); return USBD_OK; @@ -463,7 +462,13 @@ static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) return USBD_OK; } -static uint8_t cdc_ctlx_out (usb_dev *udev) +/*! + \brief command data received on control endpoint + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_ctlx_out (usb_dev *udev) { usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; @@ -485,7 +490,7 @@ static uint8_t cdc_ctlx_out (usb_dev *udev) } /*! - \brief handle CDC ACM data + \brief handle CDC ACM data in \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint identifier \param[out] none @@ -507,7 +512,7 @@ static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num) } /*! - \brief handle CDC ACM data + \brief handle CDC ACM data out \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint identifier \param[out] none diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h index 4aa4afc..da1a75b 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h @@ -2,12 +2,11 @@ \file dfu_core.h \brief the header file of USB DFU device class core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -77,10 +76,6 @@ OF SUCH DAMAGE. /* bit detach capable = bit 3 in bmAttributes field */ #define DFU_DETACH_MASK (uint8_t)(0x10U) -#define USB_SERIAL_STR_LEN 0x06U - -#define USB_DFU_CONFIG_DESC_SIZE 27U - #define DFU_DESC_TYPE 0x21U /* DFU device state defines */ @@ -139,7 +134,7 @@ typedef struct uint8_t bmAttributes; /*!< DFU attributes */ uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */ - uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU Specification release. */ + uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU specification release. */ } usb_desc_dfu_func; #pragma pack() @@ -148,10 +143,13 @@ typedef struct typedef struct { usb_desc_config config; - usb_desc_itf dfu_itf; + usb_desc_itf dfu_itf0; + usb_desc_itf dfu_itf1; + usb_desc_itf dfu_itf2; usb_desc_dfu_func dfu_func; } usb_dfu_desc_config_set; +/* USB DFU handler structure */ typedef struct { uint8_t bStatus; @@ -174,4 +172,4 @@ typedef void (*app_func) (void); extern usb_desc dfu_desc; extern usb_class_core dfu_class; -#endif /* DFU_CORE_H */ +#endif /* DFU_CORE_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h index 117efa6..9e8a850 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h @@ -2,12 +2,11 @@ \file dfu_mem.h \brief USB DFU device media access layer header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -36,7 +35,7 @@ OF SUCH DAMAGE. #ifndef __DFU_MEM_H #define __DFU_MEM_H -#include "usbd_conf.h" +#include "usb_conf.h" typedef struct _dfu_mem_prop { @@ -82,4 +81,3 @@ uint8_t* dfu_mem_read(uint8_t *buf, uint32_t addr, uint32_t len); uint8_t dfu_mem_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer); #endif /* __DFU_MEM_H */ - diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c index 412935d..ef34272 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c @@ -2,12 +2,11 @@ \file dfu_core.c \brief USB DFU device class core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -36,7 +35,6 @@ OF SUCH DAMAGE. #include "dfu_core.h" #include "dfu_mem.h" #include "drv_usb_hw.h" -#include "flash_if.h" #include #define USBD_VID 0x28E9U @@ -48,6 +46,10 @@ static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index); static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req); static uint8_t dfu_ctlx_in(usb_dev *udev); +static void dfu_mode_leave(usb_dev *udev); +static uint8_t dfu_getstatus_complete (usb_dev *udev); + +/* DFU requests management functions */ static void dfu_detach(usb_dev *udev, usb_req *req); static void dfu_dnload(usb_dev *udev, usb_req *req); static void dfu_upload(usb_dev *udev, usb_req *req); @@ -55,8 +57,8 @@ static void dfu_getstatus(usb_dev *udev, usb_req *req); static void dfu_clrstatus(usb_dev *udev, usb_req *req); static void dfu_getstate(usb_dev *udev, usb_req *req); static void dfu_abort(usb_dev *udev, usb_req *req); -static void dfu_mode_leave(usb_dev *udev); -static uint8_t dfu_getstatus_complete (usb_dev *udev); + +static void string_to_unicode (uint8_t *str, uint16_t *pbuf); static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = { @@ -102,7 +104,7 @@ __ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = .bLength = sizeof(usb_desc_config), .bDescriptorType = USB_DESCTYPE_CONFIG }, - .wTotalLength = USB_DFU_CONFIG_DESC_SIZE, + .wTotalLength = sizeof(usb_dfu_desc_config_set), .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, .iConfiguration = 0x00U, @@ -110,7 +112,7 @@ __ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .dfu_itf = + .dfu_itf0 = { .header = { @@ -123,10 +125,42 @@ __ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = .bInterfaceClass = USB_DFU_CLASS, .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, - .iInterface = 0x05U + .iInterface = STR_IDX_ALT_ITF0 + }, + + .dfu_itf1 = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF1 + }, + + .dfu_itf2 = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x02U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF2 }, - .dfu_func = + .dfu_func= { .header = { @@ -136,17 +170,18 @@ __ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_CAN_UPLOAD | USB_DFU_WILL_DETACH, .wDetachTimeOut = 0x00FFU, .wTransferSize = TRANSFER_SIZE, - .bcdDFUVersion = 0x011AU, + .bcdDFUVersion = 0x0110U, }, }; -/* USB language ID Descriptor */ +/* USB language ID descriptor */ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = { + .header = + { .bLength = sizeof(usb_desc_LANGID), .bDescriptorType = USB_DESCTYPE_STR - }, + }, .wLANGID = ENG_LANGID }; @@ -154,7 +189,7 @@ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { + { .bLength = USB_STRING_LEN(10U), .bDescriptorType = USB_DESCTYPE_STR, }, @@ -165,53 +200,74 @@ static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { + { .bLength = USB_STRING_LEN(12U), .bDescriptorType = USB_DESCTYPE_STR, - }, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'D', 'F', 'U'} }; -/* USBD serial string */ +/* USB serial string */ static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { + { .bLength = USB_STRING_LEN(2U), .bDescriptorType = USB_DESCTYPE_STR, - } + } }; /* USB configure string */ static __ALIGN_BEGIN const usb_desc_str config_string __ALIGN_END = { .header = - { + { .bLength = USB_STRING_LEN(15U), .bDescriptorType = USB_DESCTYPE_STR, - }, + }, .unicode_string = {'G', 'D', '3', '2', ' ', 'U', 'S', 'B', ' ', 'C', 'O', 'N', 'F', 'I', 'G'} }; -static __ALIGN_BEGIN const usb_desc_str interface_string __ALIGN_END = +/* alternate interface 0 string */ +static __ALIGN_BEGIN usb_desc_str interface_string0 __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(44U), + { + .bLength = USB_STRING_LEN(2U), .bDescriptorType = USB_DESCTYPE_STR, - }, - .unicode_string = {'@', 'I', 'n', 't', 'e', 'r', 'n', 'a', 'l', 'F', 'l', 'a', 's', 'h', ' ', '/', '0', 'x', '0', '8', '0', '0', - '0', '0', '0', '0', '/', '1', '6', '*', '0', '0', '1', 'K', 'a', ',', '4', '8', '*', '0', '0', '1', 'K', 'g'} + }, +}; + +/* alternate interface 1 string */ +static __ALIGN_BEGIN usb_desc_str interface_string1 __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, +}; + +/* alternate interface 2 string */ +static __ALIGN_BEGIN usb_desc_str interface_string2 __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, }; void *const usbd_dfu_strings[] = { - [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, - [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, - [STR_IDX_PRODUCT] = (uint8_t *)&product_string, - [STR_IDX_SERIAL] = (uint8_t *)&serial_string, - [STR_IDX_CONFIG] = (uint8_t *)&config_string, - [STR_IDX_ITF] = (uint8_t *)&interface_string + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string, + [STR_IDX_CONFIG] = (uint8_t *)&config_string, + [STR_IDX_ALT_ITF0] = (uint8_t *)&interface_string0, + [STR_IDX_ALT_ITF1] = (uint8_t *)&interface_string1, + [STR_IDX_ALT_ITF2] = (uint8_t *)&interface_string2, }; usb_desc dfu_desc = { @@ -243,13 +299,17 @@ static uint8_t dfu_init (usb_dev *udev, uint8_t config_index) memset((void *)&dfu_handler, 0, sizeof(usbd_dfu_handler)); - dfu_handler.base_addr = APP_LOADED_ADDR; dfu_handler.manifest_state = MANIFEST_COMPLETE; dfu_handler.bState = STATE_DFU_IDLE; dfu_handler.bStatus = STATUS_OK; udev->dev.class_data[USBD_DFU_INTERFACE] = (void *)&dfu_handler; + /* create interface string */ + string_to_unicode((uint8_t *)dfu_inter_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF0]); + string_to_unicode((uint8_t *)dfu_nor_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF1]); + string_to_unicode((uint8_t *)dfu_nand_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF2]); + return USBD_OK; } @@ -270,7 +330,7 @@ static uint8_t dfu_deinit (usb_dev *udev, uint8_t config_index) dfu->bState = STATE_DFU_IDLE; dfu->bStatus = STATUS_OK; - /* lock the internal flash */ + /* deinit the memory */ dfu_mem_deinit(); return USBD_OK; @@ -295,9 +355,8 @@ static uint8_t dfu_req_handler (usb_dev *udev, usb_req *req) } /*! - \brief handle data Stage + \brief handle data stage \param[in] udev: pointer to USB device instance - \param[in] ep_num: the endpoint number \param[out] none \retval USB device operation status */ @@ -325,7 +384,7 @@ static void dfu_mode_leave (usb_dev *udev) } else { dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET; - /* lock the internal flash */ + /* deinit the memory */ dfu_mem_deinit(); /* generate system reset to allow jumping to the user code */ @@ -539,11 +598,10 @@ static void dfu_upload (usb_dev *udev, usb_req *req) \param[out] none \retval none */ -static void dfu_getstatus (usb_dev *udev, usb_req *req) +static void dfu_getstatus (usb_dev *udev, usb_req *req) { - usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; - usb_transc *transc = &udev->dev.transc_in[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; switch (dfu->bState) { case STATE_DFU_DNLOAD_SYNC: @@ -586,7 +644,8 @@ static void dfu_getstatus (usb_dev *udev, usb_req *req) /*! \brief handle the DFU_CLRSTATUS request - \param udev: pointer to USB device instance + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request \param[out] none \retval none */ @@ -609,14 +668,14 @@ static void dfu_clrstatus (usb_dev *udev, usb_req *req) /*! \brief handle the DFU_GETSTATE request \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request \param[out] none \retval none */ static void dfu_getstate (usb_dev *udev, usb_req *req) { - usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; - usb_transc *transc = &udev->dev.transc_in[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; /* send the current state of the DFU interface to host */ transc->xfer_buf = &(dfu->bState); @@ -626,6 +685,7 @@ static void dfu_getstate (usb_dev *udev, usb_req *req) /*! \brief handle the DFU_ABORT request \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request \param[out] none \retval none */ @@ -651,3 +711,23 @@ static void dfu_abort (usb_dev *udev, usb_req *req) break; } } + +/*! + \brief convert string value into unicode char + \param[in] str: pointer to plain string + \param[in] pbuf: buffer pointer to store unicode char + \param[out] none + \retval none +*/ +static void string_to_unicode (uint8_t *str, uint16_t *pbuf) +{ + uint8_t index = 0; + + if (str != NULL) { + pbuf[index++] = ((strlen((const char *)str) * 2U + 2U) & 0x00FFU) | ((USB_DESCTYPE_STR << 8U) & 0xFF00); + + while (*str != '\0') { + pbuf[index++] = *str++; + } + } +} diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c index 33be15a..223afe6 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c @@ -2,12 +2,11 @@ \file dfu_mem.c \brief USB DFU device media access layer functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -34,7 +33,6 @@ OF SUCH DAMAGE. */ #include "dfu_mem.h" -#include "flash_if.h" #include "drv_usb_hw.h" #include "usbd_transc.h" @@ -48,14 +46,18 @@ extern struct { } prog; dfu_mem_prop* mem_tab[MAX_USED_MEMORY_MEDIA] = { - &dfu_flash_cb + &dfu_inter_flash_cb, + &dfu_nor_flash_cb, + &dfu_nand_flash_cb, }; /* The list of memory interface string descriptor pointers. This list can be updated whenever a memory has to be added or removed */ const uint8_t* USBD_DFU_StringDesc[MAX_USED_MEMORY_MEDIA] = { - (const uint8_t *)FLASH_IF_STRING + (const uint8_t *)INTER_FLASH_IF_STR, + (const uint8_t *)NOR_FLASH_IF_STR, + (const uint8_t *)NAND_FLASH_IF_STR }; static uint8_t dfu_mem_checkaddr (uint32_t addr); @@ -146,9 +148,8 @@ uint8_t dfu_mem_write (uint8_t *buf, uint32_t addr, uint32_t len) return MEM_FAIL; } - if ((addr & MAL_MASK_OB) == OB_RDPT) { + if ((addr & MAL_MASK_OB) == OB_RDPT0) { option_byte_write(addr, buf); - NVIC_SystemReset(); return MEM_OK; @@ -178,7 +179,7 @@ uint8_t* dfu_mem_read (uint8_t *buf, uint32_t addr, uint32_t len) { uint32_t mem_index = 0U; - if (OB_RDPT != addr) { + if ((OB_RDPT0 != addr) && (OB_RDPT1 != addr)) { mem_index = dfu_mem_checkaddr(addr); } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h index 0db20f7..f577813 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h @@ -2,12 +2,11 @@ \file custom_hid_core.h \brief definitions for HID core - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h index 10b5c3e..503430f 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h @@ -2,12 +2,11 @@ \file standard_hid_core.h \brief definitions for HID core - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c index b707aa3..3368576 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c @@ -2,12 +2,11 @@ \file custom_hid_core.c \brief custom HID class driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -44,11 +43,11 @@ OF SUCH DAMAGE. /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev custom_hid_dev_desc __ALIGN_END = { - .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV, - }, + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -66,13 +65,13 @@ __ALIGN_BEGIN const usb_desc_dev custom_hid_dev_desc __ALIGN_END = /* USB device configuration descriptor */ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = { - .config = + .config = { - .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = DESC_LEN_CONFIG, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -81,13 +80,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .hid_itf = + .hid_itf = { - .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -97,13 +96,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .iInterface = 0x00U }, - .hid_vendor = + .hid_vendor = { - .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -111,26 +110,26 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .wDescriptorLength = DESC_LEN_REPORT, }, - .hid_epin = + .hid_epin = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = CUSTOMHID_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = CUSTOMHID_IN_PACKET, .bInterval = 0x20U }, - .hid_epout = + .hid_epout = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = CUSTOMHID_OUT_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = CUSTOMHID_OUT_PACKET, @@ -141,44 +140,44 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = /* USB language ID descriptor */ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(14U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(14U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'u', 's', 't', 'o', 'm', 'H', 'I', 'D'} }; /* USBD serial string */ static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor set */ @@ -331,10 +330,10 @@ static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index) memset((void *)&hid_handler, 0U, sizeof(custom_hid_handler)); - /* initialize the data TX endpoint */ + /* initialize the data Tx endpoint */ usbd_ep_setup (udev, &(custom_hid_config_desc.hid_epin)); - /* Initialize the data RX endpoint */ + /* initialize the data Rx endpoint */ usbd_ep_setup (udev, &(custom_hid_config_desc.hid_epout)); /* prepare receive data */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c index bce9646..ce057e7 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c @@ -2,12 +2,11 @@ \file standard_hid_core.c \brief HID class driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -43,11 +42,11 @@ OF SUCH DAMAGE. /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev hid_dev_desc __ALIGN_END = { - .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV - }, + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -64,13 +63,13 @@ __ALIGN_BEGIN const usb_desc_dev hid_dev_desc __ALIGN_END = __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = { - .config = + .config = { - .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = USB_HID_CONFIG_DESC_LEN, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -79,13 +78,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .hid_itf = + .hid_itf = { - .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x01U, @@ -95,13 +94,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = .iInterface = 0x00U }, - .hid_vendor = + .hid_vendor = { - .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -109,13 +108,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = .wDescriptorLength = USB_HID_REPORT_DESC_LEN, }, - .hid_epin = + .hid_epin = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = HID_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = HID_IN_PACKET, @@ -128,10 +127,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set other_speed_hid_config_desc __ALIGN_ .config = { .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_OTHER_SPD_CONFIG - }, + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_OTHER_SPD_CONFIG + }, .wTotalLength = USB_HID_CONFIG_DESC_LEN, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -143,10 +142,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set other_speed_hid_config_desc __ALIGN_ .hid_itf = { .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x01U, @@ -159,10 +158,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set other_speed_hid_config_desc __ALIGN_ .hid_vendor = { .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -173,10 +172,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set other_speed_hid_config_desc __ALIGN_ .hid_epin = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = HID_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = HID_IN_PACKET, @@ -201,44 +200,44 @@ __ALIGN_BEGIN const uint8_t usbd_qualifier_desc[10] __ALIGN_END = /* USB language ID Descriptor */ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(17U), - .bDescriptorType = USB_DESCTYPE_STR, - }, - .unicode_string = {'G', 'D', '3', '2', '-','U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'} + .header = + { + .bLength = USB_STRING_LEN(17U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'} }; /* USBD serial string */ static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; void *const usbd_hid_strings[] = diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h index 28258cc..6b46c0d 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h @@ -2,12 +2,11 @@ \file usb_iap_core.h \brief the header file of IAP driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c index 8e4d8ab..6bfe231 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c @@ -2,12 +2,11 @@ \file usb_iap_core.c \brief IAP driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -44,11 +43,11 @@ OF SUCH DAMAGE. /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev iap_dev_desc __ALIGN_END = { - .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV - }, + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -65,13 +64,13 @@ __ALIGN_BEGIN const usb_desc_dev iap_dev_desc __ALIGN_END = __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = { - .config = + .config = { - .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = USB_DESC_LEN_IAP_CONFIG_SET, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -80,13 +79,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .hid_itf = + .hid_itf = { - .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -96,13 +95,13 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .iInterface = 0x00U }, - .hid_vendor = + .hid_vendor = { - .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -110,26 +109,26 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .wDescriptorLength = USB_DESC_LEN_IAP_REPORT, }, - .hid_epin = + .hid_epin = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = IAP_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = IAP_IN_PACKET, .bInterval = 0x01U }, - .hid_epout = + .hid_epout = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = IAP_OUT_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = IAP_OUT_PACKET, @@ -140,44 +139,44 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = /* USB language ID Descriptor */ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'I', 'A', 'P'} }; /* USBD serial string */ static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(2U), - .bDescriptorType = USB_DESCTYPE_STR, - } + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; void *const usbd_iap_strings[] = @@ -195,17 +194,17 @@ usb_desc iap_desc = { }; /* local function prototypes ('static') */ -static uint8_t iap_init (usb_dev *udev, uint8_t config_index); -static uint8_t iap_deinit (usb_dev *udev, uint8_t config_index); -static uint8_t iap_req_handler (usb_dev *udev, usb_req *req); -static uint8_t iap_data_out (usb_dev *udev, uint8_t ep_num); +static uint8_t iap_init (usb_dev *udev, uint8_t config_index); +static uint8_t iap_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t iap_req_handler (usb_dev *udev, usb_req *req); +static uint8_t iap_data_out (usb_dev *udev, uint8_t ep_num); /* IAP requests management functions */ -static void iap_req_erase (usb_dev *udev); -static void iap_req_dnload (usb_dev *udev); -static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num); -static void iap_req_leave (usb_dev *udev); -static void iap_address_send (usb_dev *udev); +static void iap_req_erase (usb_dev *udev); +static void iap_req_dnload (usb_dev *udev); +static void iap_req_optionbyte (usb_dev *udev, uint8_t option_num); +static void iap_req_leave (usb_dev *udev); +static void iap_address_send (usb_dev *udev); usb_class_core iap_class = { .init = iap_init, @@ -238,7 +237,7 @@ __ALIGN_BEGIN const uint8_t iap_report_desc[USB_DESC_LEN_IAP_REPORT] __ALIGN_END #endif 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ - /* device status and option byte */ + /* device status and option byte */ 0x85, 0x02, /* REPORT_ID (0x02) */ 0x09, 0x02, /* USAGE (Status and option byte) */ 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ @@ -276,10 +275,10 @@ static uint8_t iap_init (usb_dev *udev, uint8_t config_index) { static __ALIGN_BEGIN usbd_iap_handler iap_handler __ALIGN_END; - /* initialize TX endpoint */ + /* initialize Tx endpoint */ usbd_ep_setup(udev, &(iap_config_desc.hid_epin)); - /* initialize RX endpoint */ + /* initialize Rx endpoint */ usbd_ep_setup(udev, &(iap_config_desc.hid_epout)); /* unlock the internal flash */ @@ -419,7 +418,7 @@ static uint8_t iap_data_out (usb_dev *udev ,uint8_t ep_num) /*! \brief handle the IAP_DNLOAD request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ @@ -451,7 +450,7 @@ static void iap_req_dnload(usb_dev *udev) /*! \brief handle the IAP_ERASE request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ @@ -491,7 +490,7 @@ static void iap_req_erase(usb_dev *udev) fmc_unlock(); flash_erase(addr, iap->file_length, iap->report_buf); - + fmc_lock(); iap->dev_status[0] = 0x02U; @@ -514,7 +513,7 @@ static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num) usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; - iap->option_byte[0]= 0x02U; + iap->option_byte[0] = 0x02U; if (0x01U == option_num) { address = OPT_BYTE_ADDR1; @@ -536,7 +535,7 @@ static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num) /*! \brief handle the IAP_LEAVE request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ @@ -551,7 +550,7 @@ static void iap_req_leave(usb_dev *udev) /*! \brief handle the IAP_SEND_ADDRESS request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h index 13b69fb..8d60d97 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h @@ -1,13 +1,12 @@ /*! \file usbd_msc_bbb.h - \brief the header file of the usbd_msc_bot.c file + \brief the header file of the usbd_msc_bbb.c file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -84,7 +83,7 @@ typedef struct } usbd_msc_handler; /* function declarations */ -/* initialize the bbb process */ +/* initialize the BBB process */ void msc_bbb_init (usb_core_driver *udev); /* reset the BBB machine */ void msc_bbb_reset (usb_core_driver *udev); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h index b9e5f37..237d871 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h @@ -2,12 +2,11 @@ \file usbd_msc_core.h \brief the header file of USB MSC device class core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h index 0065f37..12ac3c5 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h @@ -2,12 +2,11 @@ \file usbd_msc_mem.h \brief header file for storage memory - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -53,7 +52,7 @@ typedef struct uint8_t *mem_inquiry_data[MEM_LUN_NUM]; uint32_t mem_block_size[MEM_LUN_NUM]; uint32_t mem_block_len[MEM_LUN_NUM]; -}usbd_mem_cb; +} usbd_mem_cb; extern usbd_mem_cb *usbd_mem_fops; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h index fd034f4..ddfe478 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h @@ -2,12 +2,11 @@ \file usbd_msc_scsi.h \brief the header file of the usbd_msc_scsi.c file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c index 537b996..22ca5e2 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c @@ -3,12 +3,11 @@ \brief USB BBB(Bulk/Bulk/Bulk) protocol core functions \note BBB means Bulk-only transport protocol for USB MSC - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -39,11 +38,11 @@ OF SUCH DAMAGE. /* local function prototypes ('static') */ static void msc_bbb_cbw_decode (usb_core_driver *udev); -static void msc_bbb_data_send (usb_core_driver *udev, uint8_t *pbuf, uint32_t Len); -static void msc_bbb_abort (usb_core_driver *udev); +static void msc_bbb_data_send (usb_core_driver *udev, uint8_t *pbuf, uint32_t Len); +static void msc_bbb_abort (usb_core_driver *udev); /*! - \brief initialize the bbb process + \brief initialize the BBB process \param[in] udev: pointer to USB device instance \param[out] none \retval none @@ -62,10 +61,10 @@ void msc_bbb_init (usb_core_driver *udev) usbd_mem_fops->mem_init(lun_num); } - /* flush the RX FIFO */ + /* flush the Rx FIFO */ usbd_fifo_flush (udev, MSC_OUT_EP); - /* flush the TX FIFO */ + /* flush the Tx FIFO */ usbd_fifo_flush (udev, MSC_IN_EP); /* prepare endpoint to receive the first BBB CBW */ @@ -189,14 +188,14 @@ void msc_bbb_clrfeature (usb_core_driver *udev, uint8_t ep_num) { usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; - if (msc->bbb_status == BBB_STATUS_ERROR)/* bad CBW signature */ { + if (msc->bbb_status == BBB_STATUS_ERROR) { /* bad CBW signature */ usbd_ep_stall(udev, MSC_IN_EP); msc->bbb_status = BBB_STATUS_NORMAL; } else if(((ep_num & 0x80U) == 0x80U) && (msc->bbb_status != BBB_STATUS_RECOVERY)) { msc_bbb_csw_send (udev, CSW_CMD_FAILED); } else { - + } } @@ -213,11 +212,11 @@ static void msc_bbb_cbw_decode (usb_core_driver *udev) msc->bbb_csw.dCSWTag = msc->bbb_cbw.dCBWTag; msc->bbb_csw.dCSWDataResidue = msc->bbb_cbw.dCBWDataTransferLength; - if ((BBB_CBW_LENGTH != usbd_rxcount_get (udev, MSC_OUT_EP)) || - (BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature)|| - (msc->bbb_cbw.bCBWLUN > 1U) || - (msc->bbb_cbw.bCBWCBLength < 1U) || - (msc->bbb_cbw.bCBWCBLength > 16U)) { + if((BBB_CBW_LENGTH != usbd_rxcount_get(udev, MSC_OUT_EP)) || + (BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature) || + (msc->bbb_cbw.bCBWLUN > 1U) || + (msc->bbb_cbw.bCBWCBLength < 1U) || + (msc->bbb_cbw.bCBWCBLength > 16U)) { /* illegal command handler */ scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); @@ -235,10 +234,10 @@ static void msc_bbb_cbw_decode (usb_core_driver *udev) } else if (0U == msc->bbb_datalen) { msc_bbb_csw_send (udev, CSW_CMD_PASSED); } else { - + } } else { - + } } } @@ -275,8 +274,8 @@ static void msc_bbb_abort (usb_core_driver *udev) usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; if ((0U == msc->bbb_cbw.bmCBWFlags) && - (0U != msc->bbb_cbw.dCBWDataTransferLength) && - (BBB_STATUS_NORMAL == msc->bbb_status)) { + (0U != msc->bbb_cbw.dCBWDataTransferLength) && + (BBB_STATUS_NORMAL == msc->bbb_status)) { usbd_ep_stall(udev, MSC_OUT_EP); } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c index c66f11e..7516773 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c @@ -2,12 +2,11 @@ \file usbd_msc_core.c \brief USB MSC device class core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -63,7 +62,8 @@ usb_class_core msc_class = /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev msc_dev_desc __ALIGN_END = { - .header = { + .header = + { .bLength = USB_DEV_DESC_LEN, .bDescriptorType = USB_DESCTYPE_DEV }, @@ -86,7 +86,8 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = { .config = { - .header = { + .header = + { .bLength = sizeof(usb_desc_config), .bDescriptorType = USB_DESCTYPE_CONFIG }, @@ -100,7 +101,8 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = .msc_itf = { - .header = { + .header = + { .bLength = sizeof(usb_desc_itf), .bDescriptorType = USB_DESCTYPE_ITF }, @@ -115,7 +117,8 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = .msc_epin = { - .header = { + .header = + { .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP }, @@ -127,7 +130,8 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = .msc_epout = { - .header = { + .header = + { .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP }, @@ -143,7 +147,8 @@ __ALIGN_BEGIN const usb_desc_config_set other_speed_msc_config_desc __ALIGN_END { .config = { - .header = { + .header = + { .bLength = sizeof(usb_desc_config), .bDescriptorType = USB_DESCTYPE_OTHER_SPD_CONFIG }, @@ -157,7 +162,8 @@ __ALIGN_BEGIN const usb_desc_config_set other_speed_msc_config_desc __ALIGN_END .msc_itf = { - .header = { + .header = + { .bLength = sizeof(usb_desc_itf), .bDescriptorType = USB_DESCTYPE_ITF }, @@ -172,7 +178,8 @@ __ALIGN_BEGIN const usb_desc_config_set other_speed_msc_config_desc __ALIGN_END .msc_epin = { - .header = { + .header = + { .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP }, @@ -184,7 +191,8 @@ __ALIGN_BEGIN const usb_desc_config_set other_speed_msc_config_desc __ALIGN_END .msc_epout = { - .header = { + .header = + { .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP }, @@ -213,43 +221,43 @@ __ALIGN_BEGIN const uint8_t usbd_qualifier_desc[10] __ALIGN_END = static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'M', 'S', 'C'} }; /* USBD serial string */ static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor */ @@ -290,10 +298,10 @@ static uint8_t msc_core_init (usb_dev *udev, uint8_t config_index) udev->dev.class_data[USBD_MSC_INTERFACE] = (void *)&msc_handler; - /* configure MSC TX endpoint */ + /* configure MSC Tx endpoint */ usbd_ep_setup (udev, &(msc_config_desc.msc_epin)); - /* configure MSC RX endpoint */ + /* configure MSC Rx endpoint */ usbd_ep_setup (udev, &(msc_config_desc.msc_epout)); /* initialize the BBB layer */ @@ -342,7 +350,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req) transc->xfer_buf = &usbd_msc_maxlun; transc->remain_len = 1U; } else { - return USBD_FAIL; + return USBD_FAIL; } break; @@ -352,7 +360,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req) (0x80U != (req->bmRequestType & 0x80U))) { msc_bbb_reset(udev); } else { - return USBD_FAIL; + return USBD_FAIL; } break; @@ -376,7 +384,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req) */ static uint8_t msc_core_in (usb_dev *udev, uint8_t ep_num) { - msc_bbb_data_in(udev, ep_num); + msc_bbb_data_in (udev, ep_num); return USBD_OK; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c index 6a45803..ffd07c9 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c @@ -2,12 +2,11 @@ \file usbd_msc_scsi.c \brief USB SCSI layer functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -177,7 +176,7 @@ void scsi_sense_code (usb_core_driver *udev, uint8_t lun, uint8_t skey, uint8_t usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; msc->scsi_sense[msc->scsi_sense_tail].SenseKey = skey; - msc->scsi_sense[msc->scsi_sense_tail].ASC = asc << 8U; + msc->scsi_sense[msc->scsi_sense_tail].ASC = asc; msc->scsi_sense_tail++; if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail) { @@ -209,7 +208,7 @@ static int8_t scsi_test_unit_ready (usb_core_driver *udev, uint8_t lun, uint8_t return -1; } - + msc->bbb_datalen = 0U; return 0; @@ -424,8 +423,8 @@ static int8_t scsi_request_sense (usb_core_driver *udev, uint8_t lun, uint8_t *p if ((msc->scsi_sense_head != msc->scsi_sense_tail)) { msc->bbb_data[2] = msc->scsi_sense[msc->scsi_sense_head].SenseKey; - msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASCQ; - msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASC; + msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASC; + msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASCQ; msc->scsi_sense_head++; if (msc->scsi_sense_head == SENSE_LIST_DEEPTH) { diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h index 31916ea..9045bfe 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h @@ -2,12 +2,11 @@ \file printer_core.h \brief the header file of USB printer device class core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c index 3692f49..c90d8be 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c @@ -2,12 +2,11 @@ \file printer_core.c \brief USB printer device class core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -61,11 +60,11 @@ __ALIGN_BEGIN uint8_t PRINTER_DEVICE_ID[DEVICE_ID_LEN] __ALIGN_END = /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev printer_dev_desc __ALIGN_END = { - .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV, - }, + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -85,11 +84,11 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END { .config = { - .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = USB_PRINTER_CONFIG_DESC_LEN, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -98,13 +97,13 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END .bMaxPower = 0x32U }, - .printer_itf = + .printer_itf = { - .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -114,26 +113,26 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END .iInterface = 0x00U }, - .printer_epin = + .printer_epin = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = PRINTER_IN_EP, .bmAttributes = USB_EP_ATTR_BULK, .wMaxPacketSize = PRINTER_IN_PACKET, .bInterval = 0x00U }, - .printer_epout = + .printer_epout = { - .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = PRINTER_OUT_EP, .bmAttributes = USB_EP_ATTR_BULK, .wMaxPacketSize = PRINTER_OUT_PACKET, @@ -145,10 +144,10 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, .wLANGID = ENG_LANGID }; @@ -156,10 +155,10 @@ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; @@ -167,10 +166,10 @@ static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(16U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(16U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'P', 'r', 'i', 'n', 't', 'e', 'r'} }; @@ -178,10 +177,10 @@ static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor */ @@ -218,17 +217,17 @@ usb_class_core usbd_printer_cb = { /*! \brief initialize the printer device - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[in] config_index: configuration index \param[out] none - \retval USB device operation status + \retval usb device operation status */ static uint8_t printer_init (usb_dev *udev, uint8_t config_index) { - /* initialize the data TX endpoint */ + /* initialize the data Tx endpoint */ usbd_ep_setup (udev, &(printer_config_desc.printer_epin)); - /* initialize the data RX endpoint */ + /* initialize the data Rx endpoint */ usbd_ep_setup (udev, &(printer_config_desc.printer_epout)); /* prepare to receive data */ @@ -239,14 +238,14 @@ static uint8_t printer_init (usb_dev *udev, uint8_t config_index) /*! \brief deinitialize the printer device - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[in] config_index: configuration index \param[out] none - \retval USB device operation status + \retval usb device operation status */ static uint8_t printer_deinit (usb_dev *udev, uint8_t config_index) { - /* deinitialize the data TX/RX endpoint */ + /* deinitialize the data Tx/Rx endpoint */ usbd_ep_clear (udev, PRINTER_IN_EP); usbd_ep_clear (udev, PRINTER_OUT_EP); @@ -255,10 +254,10 @@ static uint8_t printer_deinit (usb_dev *udev, uint8_t config_index) /*! \brief handle the printer class-specific requests - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[in] req: device class-specific request \param[out] none - \retval USB device operation status + \retval usb device operation status */ static uint8_t printer_req(usb_dev *udev, usb_req *req) { @@ -280,7 +279,7 @@ static uint8_t printer_req(usb_dev *udev, usb_req *req) break; default: - return USBD_FAIL; + return USBD_FAIL; } return USBD_OK; @@ -293,9 +292,9 @@ static uint8_t printer_req(usb_dev *udev, usb_req *req) \param[out] none \retval USB device operation status */ -static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) +static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) { - return USBD_OK; + return USBD_OK; } /*! @@ -305,7 +304,7 @@ static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) \param[out] none \retval USB device operation status */ -static uint8_t printer_out (usb_dev *udev, uint8_t ep_num) +static uint8_t printer_out (usb_dev *udev, uint8_t ep_num) { - return USBD_OK; + return USBD_OK; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_core.h index dcad1fb..6815271 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_core.h @@ -2,12 +2,11 @@ \file usbd_core.h \brief USB device mode core functions prototype - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -43,7 +42,7 @@ typedef enum { USBD_OK = 0U, /*!< status OK */ USBD_BUSY, /*!< status busy */ - USBD_FAIL, /*!< status fail */ + USBD_FAIL /*!< status fail */ } usbd_status; enum _usbd_status { diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_enum.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_enum.h index da6833a..ada7b4b 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_enum.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_enum.h @@ -2,12 +2,11 @@ \file usbd_enum.h \brief USB enumeration definitions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -59,7 +58,7 @@ enum _str_index STR_IDX_CONFIG = 0x4U, /* configuration string index */ STR_IDX_ITF = 0x5U, /* interface string index */ #ifndef WINUSB_EXEMPT_DRIVER - STR_IDX_MAX = 0x6U, /* string maximum index */ + STR_IDX_MAX = 0xAU, /* string maximum index */ #else STR_IDX_MAX = 0xEFU, /* string maximum index */ #endif /* WINUSB_EXEMPT_DRIVER */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_transc.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_transc.h index 91fd548..0e494f6 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_transc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Include/usbd_transc.h @@ -2,12 +2,11 @@ \file usbd_transc.h \brief USB transaction core functions prototype - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_core.c index c706860..fb212ff 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_core.c @@ -2,12 +2,11 @@ \file usbd_core.c \brief USB device mode core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -77,7 +76,7 @@ void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_c #ifndef USE_OTG_MODE usb_curmode_set(&udev->regs, DEVICE_MODE); -#endif +#endif /* USE_OTG_MODE */ /* initializes device mode */ (void)usb_devcore_init (udev); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_enum.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_enum.c index da245c5..9af9ecc 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_enum.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_enum.c @@ -2,12 +2,11 @@ \file usbd_enum.c \brief USB enumeration function - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -538,7 +537,7 @@ static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req) { uint8_t desc_type = 0U; uint8_t desc_index = 0U; - + usb_reqsta status = REQ_NOTSUPP; usb_transc *transc = &udev->dev.transc_in[0]; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_transc.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_transc.c index 8e10110..6d8880c 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_transc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/device/core/Source/usbd_transc.c @@ -2,12 +2,11 @@ \file usbd_transc.c \brief USB transaction core functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_core.h index d51d823..8395720 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_core.h @@ -2,12 +2,11 @@ \file drv_usb_core.h \brief USB core low level driver header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -261,7 +260,7 @@ typedef struct _usb_host_drv { __IO uint32_t connect_status; __IO uint32_t port_enabled; - __IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; usb_pipe pipe[USBFS_MAX_TX_FIFOS]; void *data; @@ -293,7 +292,11 @@ typedef struct _usb_core_driver */ __STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) { - return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; + uint32_t reg_data = usb_regs->gr->GINTEN; + + reg_data &= usb_regs->gr->GINTF; + + return reg_data; } /*! @@ -337,13 +340,13 @@ __STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); /* initializes the USB controller registers and prepares the core device mode or host mode operation */ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); -/* write a packet into the TX FIFO associated with the endpoint */ +/* write a packet into the Tx FIFO associated with the endpoint */ usb_status usb_txfifo_write (usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); -/* read a packet from the RX FIFO associated with the endpoint */ +/* read a packet from the Rx FIFO associated with the endpoint */ void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); -/* flush a TX FIFO or all TX FIFOs */ +/* flush a Tx FIFO or all Tx FIFOs */ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); -/* flush the entire RX FIFO */ +/* flush the entire Rx FIFO */ usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); /* set endpoint or channel TX FIFO size */ void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h index a95a5ed..4e2b9a3 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h @@ -2,12 +2,11 @@ \file drv_usb_dev.h \brief USB device low level driver header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_host.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_host.h index b74dd1c..e11f4e9 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_host.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_host.h @@ -2,12 +2,11 @@ \file drv_usb_host.h \brief USB host mode low level driver header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -121,4 +120,4 @@ usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num); /* stop the USB host and clean up FIFO */ void usb_host_stop (usb_core_driver *udev); -#endif /* __DRV_USB_HOST_H */ +#endif /* __DRV_USB_HOST_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h index 8b874cb..7d365e8 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h @@ -2,12 +2,11 @@ \file drv_usb_hw.h \brief usb hardware configuration header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -53,20 +52,11 @@ void usb_udelay (const uint32_t usec); void usb_mdelay (const uint32_t msec); /* configures system clock after wakeup from STOP mode */ void system_clk_config_stop(void); - -/* configure the CTC peripheral */ -#ifdef USE_IRC48M - void ctc_config(void); -#endif /* USE_IRC48M */ - #ifdef USE_HOST_MODE - void systick_config(void); - - /* configure USB VBus */ - void usb_vbus_config (void); - - /* drive USB VBus */ - void usb_vbus_drive (uint8_t State); +/* configure USB VBus */ +void usb_vbus_config (void); +/* drive USB VBus */ +void usb_vbus_drive (uint8_t State); #endif /* USE_HOST_MODE */ #endif /* __DRV_USB_HW_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h index a59ab90..837070e 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h @@ -2,12 +2,11 @@ \file drv_usb_regs.h \brief USB cell registers definition and handle macros - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -182,7 +181,7 @@ typedef struct _usb_regs usb_pr *pr[15]; /*!< USB Host channel-x control register */ __IO uint32_t *HPCS; /*!< USB host port control and status register */ - __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ } usb_core_regs; @@ -303,9 +302,7 @@ typedef struct _usb_regs #define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ #define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ -/** - * @brief USB IN endpoint 0 transmit FIFO length register bits definitions - */ +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ #define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ #define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ @@ -357,7 +354,6 @@ typedef struct _usb_regs #define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - #define TFQSTAT_TXFS BITS(0, 15) #define TFQSTAT_CNUM BITS(27, 30) @@ -433,12 +429,11 @@ typedef struct _usb_regs /* host channel-x DMA address register bits definitions */ #define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ -#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ - -#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ -#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ -#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ #define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ #define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ @@ -486,7 +481,7 @@ extern const uint32_t PIPE_DPID[2]; #define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ #define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ #define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ /* device OUT endpoint common interrupt enable registers bits definitions */ #define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ @@ -622,13 +617,13 @@ extern const uint32_t PIPE_DPID[2]; #define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ #define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ #define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ #define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ #define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ -#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ #define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ #define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h index 24d0571..573d3c4 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h @@ -2,12 +2,11 @@ \file drv_usbd_int.h \brief USB device mode interrupt header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h index 8e7195e..1259806 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h @@ -2,12 +2,11 @@ \file drv_usbh_int.h.h \brief USB host mode interrupt management header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_core.c index 9e7653e..4df90d6 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_core.c @@ -2,12 +2,11 @@ \file drv_usb_core.c \brief USB core driver which can operate in host and device mode - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -78,8 +77,14 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, #ifdef USB_HS_INTERNAL_DMA_ENABLED usb_basic->transfer_mode = USB_USE_DMA; #endif /* USB_HS_INTERNAL_DMA_ENABLED */ + +#ifdef USB_HS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBHS_SOF_OUTPUT; + usb_basic->low_power = USBHS_LOW_POWER; +#endif /* USB_HS_CORE */ break; - + case USB_CORE_ENUM_FS: usb_basic->base_reg = (uint32_t)USBFS_REG_BASE; @@ -91,15 +96,18 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, /* USBFS core use embedded physical layer */ usb_basic->phy_itf = USB_EMBEDDED_PHY; + +#ifdef USB_FS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBFS_SOF_OUTPUT; + usb_basic->low_power = USBFS_LOW_POWER; +#endif /* USB_FS_CORE */ break; default: return USB_FAIL; } - usb_basic->sof_enable = USB_SOF_OUTPUT; - usb_basic->low_power = USB_LOW_POWER; - /* assign main registers address */ *usb_regs = (usb_core_regs) { .gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE), @@ -196,7 +204,7 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) usb_regs->gr->GINTF = 0xBFFFFFFFU; usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ - GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; #endif /* USE_OTG_MODE */ @@ -204,10 +212,10 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) } /*! - \brief write a packet into the TX FIFO associated with the endpoint + \brief write a packet into the Tx FIFO associated with the endpoint \param[in] usb_regs: pointer to USB core registers \param[in] src_buf: pointer to source buffer - \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) \param[in] byte_count: packet byte count \param[out] none \retval operation status @@ -254,9 +262,9 @@ void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte } /*! - \brief flush a TX FIFO or all TX FIFOs + \brief flush a Tx FIFO or all Tx FIFOs \param[in] usb_regs: pointer to USB core registers - \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) \param[out] none \retval operation status */ @@ -264,7 +272,7 @@ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) { usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - /* wait for TX FIFO flush bit is set */ + /* wait for Tx FIFO flush bit is set */ while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { /* no operation */ } @@ -285,7 +293,7 @@ usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) { usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; - /* wait for RX FIFO flush bit is set */ + /* wait for Rx FIFO flush bit is set */ while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { /* no operation */ } @@ -310,7 +318,7 @@ void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) tx_offset = usb_regs->gr->GRFLEN; - if (fifo == 0U) { + if(0U == fifo) { usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; } else { tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c index 7f9ea6e..c58a17a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c @@ -2,12 +2,11 @@ \file drv_usb_dev.c \brief USB device mode low level driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -99,7 +98,7 @@ usb_status usb_devcore_init (usb_core_driver *udev) /* set Rx FIFO size */ usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); - /* set endpoint 0 to 3's TX FIFO length and RAM address */ + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) { usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); } @@ -126,10 +125,10 @@ usb_status usb_devcore_init (usb_core_driver *udev) /* make sure all FIFOs are flushed */ - /* flush all TX FIFOs */ + /* flush all Tx FIFOs */ (void)usb_txfifo_flush (&udev->regs, 0x10U); - /* flush entire RX FIFO */ + /* flush entire Rx FIFO */ (void)usb_rxfifo_flush (&udev->regs); /* clear all pending device interrupts */ @@ -214,6 +213,8 @@ usb_status usb_devint_enable (usb_core_driver *udev) usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; + + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; /* get the endpoint number */ uint8_t ep_num = transc->ep_addr.num; @@ -230,11 +231,10 @@ usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) } /* endpoint 0 is activated after USB clock is enabled */ - *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); /* set endpoint 0 maximum packet length */ - *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + *reg_addr |= EP0_MAXLEN[enum_speed]; /* activate endpoint */ *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; @@ -252,7 +252,8 @@ usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; - __IO uint32_t epinten = 0U; + uint32_t epinten = 0U; + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; /* get the endpoint number */ uint8_t ep_num = transc->ep_addr.num; @@ -274,7 +275,7 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) /* set endpoint maximum packet length */ if (0U == ep_num) { - *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + *reg_addr |= EP0_MAXLEN[enum_speed]; } else { *reg_addr |= transc->max_len; } @@ -396,7 +397,7 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { - /* enable the TX FIFO empty interrupt for this endpoint */ + /* enable the Tx FIFO empty interrupt for this endpoint */ if (transc->xfer_len > 0U) { udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; } @@ -630,7 +631,7 @@ void usb_dev_suspend (usb_core_driver *udev) *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER,PMU_LOWDRIVER_DISABLE,WFI_CMD); + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER,PMU_LOWDRIVER_DISABLE,WFI_CMD); } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_host.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_host.c index d25bfb2..d86c23a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_host.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_host.c @@ -2,12 +2,11 @@ \file drv_usb_host.c \brief USB host mode low level driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,12 +73,12 @@ usb_status usb_host_init (usb_core_driver *udev) /* set Rx FIFO size */ udev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; - /* set non-periodic TX FIFO size and address */ + /* set non-periodic Tx FIFO size and address */ nptxfifolen |= USB_RX_FIFO_FS_SIZE; nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; udev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; - /* set periodic TX FIFO size and address */ + /* set periodic Tx FIFO size and address */ ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_NPFIFO_FS_SIZE; ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; udev->regs.gr->HPTFLEN = ptxfifolen; @@ -112,7 +111,7 @@ usb_status usb_host_init (usb_core_driver *udev) /* make sure the FIFOs are flushed */ - /* flush all TX FIFOs in device or host mode */ + /* flush all Tx FIFOs in device or host mode */ usb_txfifo_flush (&udev->regs, 0x10U); /* flush the entire Rx FIFO */ @@ -376,7 +375,7 @@ usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num) break; } - /* write packet into the TX fifo. */ + /* write packet into the Tx fifo. */ usb_txfifo_write (&udev->regs, pp->xfer_buf, pipe_num, (uint16_t)pp->xfer_len); } } @@ -434,10 +433,10 @@ usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num) { uint32_t pp_ctl = 0U; - udev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); + udev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING; pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; - + pp_ctl |= HCHCTL_CEN; pp_ctl &= ~HCHCTL_CDIS; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c index 3335f72..222516c 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c @@ -2,12 +2,11 @@ \file drv_usbd_int.c \brief USB device mode interrupt routines - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,13 +36,13 @@ OF SUCH DAMAGE. #include "drv_usbd_int.h" #include "usbd_transc.h" +/* local function prototypes ('static') */ static uint32_t usbd_int_epout (usb_core_driver *udev); static uint32_t usbd_int_epin (usb_core_driver *udev); static uint32_t usbd_int_rxfifo (usb_core_driver *udev); static uint32_t usbd_int_reset (usb_core_driver *udev); static uint32_t usbd_int_enumfinish (usb_core_driver *udev); static uint32_t usbd_int_suspend (usb_core_driver *udev); - static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); static const uint8_t USB_SPEED[4] = { @@ -62,7 +61,8 @@ static const uint8_t USB_SPEED[4] = { void usbd_isr (usb_core_driver *udev) { if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { - uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN; + uint32_t intr = udev->regs.gr->GINTF; + intr &= udev->regs.gr->GINTEN; /* there are no interrupts, avoid spurious interrupt */ if (!intr) { @@ -86,8 +86,10 @@ void usbd_isr (usb_core_driver *udev) /* wakeup interrupt */ if (intr & GINTF_WKUPIF) { - /* inform upper layer by the resume event */ - udev->dev.cur_status = USBD_CONFIGURED; + if(USBD_SUSPENDED == udev->dev.cur_status){ + /* inform upper layer by the resume event */ + udev->dev.cur_status = udev->dev.backup_status; + } /* clear interrupt */ udev->regs.gr->GINTF = GINTF_WKUPIF; @@ -96,7 +98,7 @@ void usbd_isr (usb_core_driver *udev) /* start of frame interrupt */ if (intr & GINTF_SOF) { if (udev->dev.class_core->SOF) { - (void)udev->dev.class_core->SOF(udev); + (void)udev->dev.class_core->SOF(udev); } /* clear interrupt */ @@ -180,11 +182,12 @@ uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev) udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF; if(USB_USE_DMA == udev->bp.transfer_mode){ + usb_transc *transc = &udev->dev.transc_out[1]; + uint32_t set_len = ((transc->xfer_len + transc->max_len - 1U) / transc->max_len) * transc->max_len; oeplen = udev->regs.er_out[1]->DOEPLEN; /* to do : handle more than one single max packet size packet */ - udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].max_len - \ - (oeplen & DEPLEN_TLEN); + udev->dev.transc_out[1].xfer_count = set_len - (oeplen & DEPLEN_TLEN); } /* rx complete */ @@ -252,10 +255,11 @@ static uint32_t usbd_int_epout (usb_core_driver *udev) udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + usb_transc *transc = &udev->dev.transc_out[ep_num]; __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + uint32_t set_len = ((transc->xfer_len + transc->max_len - 1U) / transc->max_len) * transc->max_len; - udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \ - (eplen & DEPLEN_TLEN); + udev->dev.transc_out[ep_num].xfer_count = set_len - (eplen & DEPLEN_TLEN); } /* inform upper layer: data ready */ @@ -416,7 +420,7 @@ static uint32_t usbd_int_reset (usb_core_driver *udev) /* clear the remote wakeup signaling */ udev->regs.dr->DCTL &= ~DCTL_RWKUP; - /* flush the TX FIFO */ + /* flush the Tx FIFO */ (void)usb_txfifo_flush (&udev->regs, 0U); for (i = 0U; i < udev->bp.num_ep; i++) { @@ -519,7 +523,7 @@ static uint32_t usbd_int_suspend (usb_core_driver *udev) { __IO uint8_t low_power = udev->bp.low_power; __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)? 1U : 0U; + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; udev->dev.backup_status = udev->dev.cur_status; udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; @@ -529,7 +533,7 @@ static uint32_t usbd_int_suspend (usb_core_driver *udev) *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); } /* clear interrupt */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c index a0b89a9..e480408 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c @@ -2,12 +2,11 @@ \file drv_usbh_int.c \brief USB host mode interrupt handler file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -98,11 +97,6 @@ uint32_t usbh_isr (usb_core_driver *udev) retval |= usbh_int_port (udev); } - if (intr & GINTF_WKUPIF) { - /* clear interrupt */ - udev->regs.gr->GINTF = GINTF_WKUPIF; - } - if (intr & GINTF_DISCIF) { usbh_int_fop->disconnect(udev->host.data); @@ -173,7 +167,7 @@ static uint32_t usbh_int_port (usb_core_driver *udev) __IO uint32_t port_state = *udev->regs.HPCS; - /* clear the interrupt bits in GINTSTS */ + /* clear the interrupt bit in GINTF */ port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); /* port connect detected */ @@ -278,7 +272,8 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num) usb_pipe *pp = &udev->host.pipe[pp_num]; - __IO uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; uint8_t ep_type = (uint8_t)((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U); @@ -405,17 +400,17 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num) #endif /* __ICCARM */ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) { + usbh_host *uhost = udev->host.data; usb_pr *pp_reg = udev->regs.pr[pp_num]; - usb_pipe *pp = &udev->host.pipe[pp_num]; - - uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; if (intr_pp & HCHINTF_ACK) { if (1U == udev->host.pipe[pp_num].do_ping) { udev->host.pipe[pp_num].do_ping = 0; pp->err_count = 0U; - usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_ACK, pp->pp_status); + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_ACK, PIPE_NAK); } pp_reg->HCHINTF = HCHINTF_ACK; @@ -437,19 +432,29 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) } pp->err_count = 0U; + if(USB_USE_FIFO == udev->bp.transfer_mode) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK); + } else { + pp_reg->HCHINTF = HCHINTF_NAK; + } usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK); } else if (intr_pp & HCHINTF_USBER) { pp->err_count++; usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); } else if (intr_pp & HCHINTF_NYET) { - if (0U == udev->host.pipe[pp_num].do_ping) { - if (1U == udev->host.pipe[pp_num].supp_ping) { - udev->host.pipe[pp_num].do_ping = 1; + if (CTL_STATUS_OUT != uhost->control.ctl_state) { + if (0U == udev->host.pipe[pp_num].do_ping) { + if (1U == udev->host.pipe[pp_num].supp_ping) { + udev->host.pipe[pp_num].do_ping = 1; + } } + + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); + } else { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_XF); } pp->err_count = 0U; - usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); } else if (intr_pp & HCHINTF_CH) { udev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; @@ -463,8 +468,14 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) break; case PIPE_NAK: + pp->urb_state = URB_NOTREADY; + break; case PIPE_NYET: - pp->urb_state = URB_NOTREADY; + pp->urb_state = URB_DONE; + + if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { + pp->data_toggle_out ^= 1U; + } break; case PIPE_STALL: @@ -506,7 +517,7 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) #endif /* __ICCARM */ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) { - uint32_t count = 0U; + uint32_t count = 0U, xfer_count = 0U; __IO uint8_t pp_num = 0U; __IO uint32_t rx_stat = 0U; @@ -528,12 +539,14 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) /* manage multiple transfer packet */ udev->host.pipe[pp_num].xfer_buf += count; udev->host.pipe[pp_num].xfer_count += count; + + xfer_count = udev->host.pipe[pp_num].xfer_count; - udev->host.backup_xfercount[pp_num] = udev->host.pipe[pp_num].xfer_count; + udev->host.backup_xfercount[pp_num] = xfer_count; if (udev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { /* re-activate the channel when more packets are expected */ - __IO uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL; + uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL; pp_ctl |= HCHCTL_CEN; pp_ctl &= ~HCHCTL_CDIS; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h index f8a1391..1813fc3 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h @@ -2,12 +2,11 @@ \file usbh_hid_core.h \brief header file for the usbh_hid_core.c - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -100,7 +99,7 @@ typedef struct _hid_process __IO uint32_t timer; usb_desc_hid hid_desc; - hid_state state; + hid_state state; hid_ctlstate ctl_state; usbh_status (*init)(usb_core_driver *udev, usbh_host *uhost); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h index a901e5f..e89f449 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h @@ -2,12 +2,11 @@ \file usbh_standard_hid.h \brief header file for usbh_standard_hid.c - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c index 9bb2dd8..5610069 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c @@ -2,12 +2,11 @@ \file usbh_hid_core.c \brief USB host HID class driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -255,7 +254,7 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost) hid_handler.poll = HID_MIN_POLL; } - /* check fifo available number of endpoints */ + /* check for available number of endpoints */ /* find the number of endpoints in the interface descriptor */ /* choose the lower number in order not to overrun the buffer allocated */ ep_num = USB_MIN(uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bNumEndpoints, USBH_MAX_EP_NUM); @@ -365,7 +364,7 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost) } /*! - \brief manage state machine for HID data transfers + \brief manage state machine for HID data transfers \param[in] uhost: pointer to USB host \param[out] none \retval operation status @@ -409,7 +408,8 @@ static usbh_status usbh_hid_handle (usbh_host *uhost) hid->decode(hid->pdata); } } else { - if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in)) { /* IN endpoint stalled */ + /* check IN endpoint stall status */ + if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in)) { /* issue clear feature on interrupt in endpoint */ if (USBH_OK == (usbh_clrfeature (uhost, hid->ep_addr, hid->pipe_in))) { /* change state to issue next in token */ @@ -570,7 +570,7 @@ static usbh_status usbh_set_protocol (usbh_host *uhost, uint8_t protocol) \param[out] none \retval none */ -static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf) +static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf) { hid_desc->header.bLength = *(uint8_t *)(buf + 0U); hid_desc->header.bDescriptorType = *(uint8_t *)(buf + 1U); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c index fd26b91..b2fabf9 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c @@ -2,12 +2,11 @@ \file usbh_standard_hid.c \brief USB host HID keyboard and mouse driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -39,8 +38,8 @@ OF SUCH DAMAGE. hid_mouse_info mouse_info; hid_keybd_info keybd_info; -uint8_t mouse_report_data[4] = {0U}; -uint32_t keybd_report_data[2]; +__ALIGN_BEGIN uint8_t mouse_report_data[8] __ALIGN_END = {0U}; +__ALIGN_BEGIN uint32_t keybd_report_data[2] __ALIGN_END; /* local constants */ static const uint8_t kbd_codes[] = @@ -49,15 +48,15 @@ static const uint8_t kbd_codes[] = 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ 52, 51, 25, 26, 17, 20, 32, 21, 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ - 4, 5, 6, 7, 8, 9, 10, 11, + 4, 5, 6, 7, 8, 9, 10, 11, 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ - 28, 29, 42, 40, 41, 1, 53, 54, + 28, 29, 42, 40, 41, 1, 53, 54, 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ - 118, 119, 120, 121, 122, 123, 124, 125, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ 79, 84, 83, 90, 95, 100, 105, 106, 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ - 96, 101, 99, 104, 45, 129, 0, 0, + 96, 101, 99, 104, 45, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ @@ -67,11 +66,11 @@ static const uint8_t kbd_codes[] = 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ - 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ - 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ - 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ }; @@ -82,7 +81,7 @@ static const int8_t kbd_key[] = { '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=', '\0', '\r', - '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']', '\\', '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', '\'', '\0', '\n', @@ -90,25 +89,25 @@ static const int8_t kbd_key[] = 'm', ',', '.', '/', '\0', '\0', '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' }; static const int8_t kbd_key_shift[] = { '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', - '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', - 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', - 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' @@ -118,14 +117,14 @@ static const int8_t kbd_key_shift[] = { static const int8_t kbd_key[] = { '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', - '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', - 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', - 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', - 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', - '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', - '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' }; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h index e3444dd..eb3f9b2 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h @@ -2,12 +2,11 @@ \file usbh_msc_bbb.h \brief header file for usbh_msc_bbb.c - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -43,13 +42,13 @@ typedef union { msc_bbb_cbw field; uint8_t CBWArray[31]; -}usbh_cbw_pkt; +} usbh_cbw_pkt; typedef union { msc_bbb_csw field; uint8_t CSWArray[13]; -}usbh_csw_pkt; +} usbh_csw_pkt; enum usbh_msc_state { USBH_MSC_BBB_INIT_STATE = 0U, @@ -77,7 +76,7 @@ typedef enum { BBB_CMD_IDLE = 0U, BBB_CMD_SEND, - BBB_CMD_WAIT, + BBB_CMD_WAIT } bbb_cmd_state; /* csw status definitions */ @@ -85,7 +84,7 @@ typedef enum { BBB_CSW_CMD_PASSED = 0U, BBB_CSW_CMD_FAILED, - BBB_CSW_PHASE_ERROR, + BBB_CSW_PHASE_ERROR } bbb_csw_status; typedef enum @@ -139,11 +138,11 @@ typedef struct /* function declarations */ /* initialize the mass storage parameters */ void usbh_msc_bbb_init (usbh_host *uhost); -/* manage the different states of BOT transfer and updates the status to upper layer */ +/* manage the different states of BBB transfer and updates the status to upper layer */ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun); /* manages the different error handling for stall */ usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction); -/* reset MSC bot request structure */ +/* reset MSC BBB request structure */ usbh_status usbh_msc_bbb_reset (usbh_host *uhost); /* decode the CSW received by the device and updates the same to upper layer */ bbb_csw_status usbh_msc_csw_decode (usbh_host *uhost); diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h index cdd43c2..a72e5b2 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h @@ -2,12 +2,11 @@ \file usbh_core.h \brief header file for the usbh_core.c - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -71,7 +70,7 @@ typedef enum MSC_REQ_ERROR, } msc_req_state; -/* Structure for LUN */ +/* structure for LUN */ typedef struct { msc_state state; @@ -83,7 +82,7 @@ typedef struct uint8_t state_changed; } msc_lun; -/* structure for MSC process */ +/* structure for msc process */ typedef struct _msc_process { uint8_t pipe_in; @@ -99,7 +98,7 @@ typedef struct _msc_process msc_error error; msc_req_state req_state; msc_req_state prev_req_state; - bbb_handle bot; + bbb_handle bbb; msc_lun unit[MSC_MAX_SUPPORTED_LUN]; uint32_t timer; } usbh_msc_handler; @@ -122,4 +121,4 @@ usbh_status usbh_msc_write (usbh_host *uhost, uint8_t *pbuf, uint32_t length); -#endif /* __USBH_MSC_CORE_H */ +#endif /* __USBH_MSC_CORE_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h index 420880b..1dc2c1d 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h @@ -2,12 +2,11 @@ \file usbh_msc_scsi.h \brief header file for usbh_msc_scsi.c - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -63,7 +62,7 @@ typedef struct uint32_t msc_sense_key; uint16_t msc_page_len; uint8_t msc_write_protect; -}usbh_msc_parameter; +} usbh_msc_parameter; #define DESC_REQUEST_SENSE 0x00U #define ALLOCATION_LENGTH_REQUEST_SENSE 63U diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c index c515a60..10b2303 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c @@ -2,12 +2,11 @@ \file usbh_msc_bbb.c \brief USB MSC BBB protocol related functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,15 +49,15 @@ void usbh_msc_bbb_init (usbh_host *uhost) { usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - msc->bot.cbw.field.dCBWSignature = BBB_CBW_SIGNATURE; - msc->bot.cbw.field.dCBWTag = USBH_MSC_BBB_CBW_TAG; - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_SEND; + msc->bbb.cbw.field.dCBWSignature = BBB_CBW_SIGNATURE; + msc->bbb.cbw.field.dCBWTag = USBH_MSC_BBB_CBW_TAG; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_SEND; } /*! - \brief manage the different states of BOT transfer and updates the status to upper layer - \param[in] uhost: pointer to usb host handler + \brief manage the different states of BBB transfer and updates the status to upper layer + \param[in] uhost: pointer to USB host handler \param[in] lun: logic unit number \param[out] none \retval operation status @@ -71,13 +70,13 @@ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) usb_urb_state urb_status = URB_IDLE; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.state) { + switch (msc->bbb.state) { case BBB_SEND_CBW: - msc->bot.cbw.field.bCBWLUN = lun; - msc->bot.state = BBB_SEND_CBW_WAIT; + msc->bbb.cbw.field.bCBWLUN = lun; + msc->bbb.state = BBB_SEND_CBW_WAIT; /* send CBW */ usbh_data_send (uhost->data, - msc->bot.cbw.CBWArray, + msc->bbb.cbw.CBWArray, msc->pipe_out, BBB_CBW_LENGTH); break; @@ -86,57 +85,57 @@ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out); if (URB_DONE == urb_status) { - if (0U != msc->bot.cbw.field.dCBWDataTransferLength) { - if (USB_TRX_IN == (msc->bot.cbw.field.bmCBWFlags & USB_TRX_MASK)) { - msc->bot.state = BBB_DATA_IN; + if (0U != msc->bbb.cbw.field.dCBWDataTransferLength) { + if (USB_TRX_IN == (msc->bbb.cbw.field.bmCBWFlags & USB_TRX_MASK)) { + msc->bbb.state = BBB_DATA_IN; } else { - msc->bot.state = BBB_DATA_OUT; + msc->bbb.state = BBB_DATA_OUT; } } else { - msc->bot.state = BBB_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } } else if (URB_NOTREADY == urb_status) { - msc->bot.state = BBB_SEND_CBW; + msc->bbb.state = BBB_SEND_CBW; } else { if (URB_STALL == urb_status) { - msc->bot.state = BBB_ERROR_OUT; + msc->bbb.state = BBB_ERROR_OUT; } } break; case BBB_DATA_IN: usbh_data_recev (uhost->data, - msc->bot.pbuf, + msc->bbb.pbuf, msc->pipe_in, msc->ep_size_in); - msc->bot.state = BBB_DATA_IN_WAIT; + msc->bbb.state = BBB_DATA_IN_WAIT; break; case BBB_DATA_IN_WAIT: urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in); - /* BOT DATA IN stage */ + /* BBB DATA IN stage */ if (URB_DONE == urb_status) { - if (msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_in) { - msc->bot.pbuf += msc->ep_size_in; - msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_in; + if (msc->bbb.cbw.field.dCBWDataTransferLength > msc->ep_size_in) { + msc->bbb.pbuf += msc->ep_size_in; + msc->bbb.cbw.field.dCBWDataTransferLength -= msc->ep_size_in; } else { - msc->bot.cbw.field.dCBWDataTransferLength = 0U; + msc->bbb.cbw.field.dCBWDataTransferLength = 0U; } - if (msc->bot.cbw.field.dCBWDataTransferLength > 0U) { + if (msc->bbb.cbw.field.dCBWDataTransferLength > 0U) { usbh_data_recev (uhost->data, - msc->bot.pbuf, + msc->bbb.pbuf, msc->pipe_in, msc->ep_size_in); } else { - msc->bot.state = BBB_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } } else if(URB_STALL == urb_status) { /* this is data stage stall condition */ - msc->bot.state = BBB_ERROR_IN; + msc->bbb.state = BBB_ERROR_IN; } else { /* no operation */ } @@ -144,49 +143,49 @@ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) case BBB_DATA_OUT: usbh_data_send (uhost->data, - msc->bot.pbuf, + msc->bbb.pbuf, msc->pipe_out, msc->ep_size_out); - msc->bot.state = BBB_DATA_OUT_WAIT; + msc->bbb.state = BBB_DATA_OUT_WAIT; break; case BBB_DATA_OUT_WAIT: - /* BOT DATA OUT stage */ + /* BBB DATA OUT stage */ urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out); if (URB_DONE == urb_status) { - if (msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_out) { - msc->bot.pbuf += msc->ep_size_out; - msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_out; + if (msc->bbb.cbw.field.dCBWDataTransferLength > msc->ep_size_out) { + msc->bbb.pbuf += msc->ep_size_out; + msc->bbb.cbw.field.dCBWDataTransferLength -= msc->ep_size_out; } else { - msc->bot.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */ + msc->bbb.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */ } - if (msc->bot.cbw.field.dCBWDataTransferLength > 0) { + if (msc->bbb.cbw.field.dCBWDataTransferLength > 0) { usbh_data_send (uhost->data, - msc->bot.pbuf, + msc->bbb.pbuf, msc->pipe_out, msc->ep_size_out); } else { - msc->bot.state = BBB_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } } else if (URB_NOTREADY == urb_status) { - msc->bot.state = BBB_DATA_OUT; + msc->bbb.state = BBB_DATA_OUT; } else if (URB_STALL == urb_status) { - msc->bot.state = BBB_ERROR_OUT; + msc->bbb.state = BBB_ERROR_OUT; } else { /* no operation */ } break; case BBB_RECEIVE_CSW: - /* BOT CSW stage */ + /* BBB CSW stage */ usbh_data_recev (uhost->data, - msc->bot.csw.CSWArray, + msc->bbb.csw.CSWArray, msc->pipe_in, BBB_CSW_LENGTH); - msc->bot.state = BBB_RECEIVE_CSW_WAIT; + msc->bbb.state = BBB_RECEIVE_CSW_WAIT; break; case BBB_RECEIVE_CSW_WAIT: @@ -194,8 +193,8 @@ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) /* decode CSW */ if (URB_DONE == urb_status) { - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_SEND; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_SEND; csw_status = usbh_msc_csw_decode(uhost); if (BBB_CSW_CMD_PASSED == csw_status) { @@ -204,36 +203,36 @@ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) status = USBH_FAIL; } } else if (URB_STALL == urb_status) { - msc->bot.state = BBB_ERROR_IN; + msc->bbb.state = BBB_ERROR_IN; } else { /* no operation */ } break; - case BBB_ERROR_IN: + case BBB_ERROR_IN: error = usbh_msc_bbb_abort(uhost, USBH_MSC_DIR_IN); if (USBH_OK == error) { - msc->bot.state = BBB_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } else if (USBH_UNRECOVERED_ERROR == status) { /* this means that there is a stall error limit, do reset recovery */ - msc->bot.state = BBB_UNRECOVERED_ERROR; + msc->bbb.state = BBB_UNRECOVERED_ERROR; } else { /* no operation */ } break; - case BBB_ERROR_OUT: + case BBB_ERROR_OUT: status = usbh_msc_bbb_abort (uhost, USBH_MSC_DIR_OUT); if (USBH_OK == status) { uint8_t toggle = usbh_pipe_toggle_get(uhost->data, msc->pipe_out); usbh_pipe_toggle_set(uhost->data, msc->pipe_out, 1U - toggle); usbh_pipe_toggle_set(uhost->data, msc->pipe_in, 0U); - msc->bot.state = BBB_ERROR_IN; + msc->bbb.state = BBB_ERROR_IN; } else { if (USBH_UNRECOVERED_ERROR == status) { - msc->bot.state = BBB_UNRECOVERED_ERROR; + msc->bbb.state = BBB_UNRECOVERED_ERROR; } } break; @@ -241,7 +240,7 @@ usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) case BBB_UNRECOVERED_ERROR: status = usbh_msc_bbb_reset(uhost); if (USBH_OK == status) { - msc->bot.state = BBB_SEND_CBW; + msc->bbb.state = BBB_SEND_CBW; } break; @@ -266,7 +265,7 @@ usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction) switch (direction) { case USBH_MSC_DIR_IN : - /* send clrfeture command on bulk IN endpoint */ + /* send clrfeature command on bulk IN endpoint */ status = usbh_clrfeature(uhost, msc->ep_in, msc->pipe_in); @@ -287,7 +286,7 @@ usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction) } /*! - \brief reset MSC bot transfer + \brief reset msc bbb transfer \param[in] uhost: pointer to USB host handler \param[out] none \retval operation status @@ -319,7 +318,7 @@ usbh_status usbh_msc_bbb_reset (usbh_host *uhost) \param[out] none \retval on success USBH_MSC_OK, on failure USBH_MSC_FAIL \notes - Refer to USB Mass-Storage Class: BOT (www.usb.org) + Refer to USB Mass-Storage Class: BBB (www.usb.org) 6.3.1 Valid CSW Conditions : The host shall consider the CSW valid when: 1. dCSWSignature is equal to 53425355h @@ -338,22 +337,22 @@ bbb_csw_status usbh_msc_csw_decode (usbh_host *uhost) /* CSW length is correct */ /* check validity of the CSW Signature and CSWStatus */ - if (BBB_CSW_SIGNATURE == msc->bot.csw.field.dCSWSignature) { + if (BBB_CSW_SIGNATURE == msc->bbb.csw.field.dCSWSignature) { /* check condition 1. dCSWSignature is equal to 53425355h */ - if (msc->bot.csw.field.dCSWTag == msc->bot.cbw.field.dCBWTag) { + if (msc->bbb.csw.field.dCSWTag == msc->bbb.cbw.field.dCBWTag) { /* check condition 3. dCSWTag matches the dCBWTag from the corresponding CBW */ - if (0U == msc->bot.csw.field.bCSWStatus) { + if (0U == msc->bbb.csw.field.bCSWStatus) { status = BBB_CSW_CMD_PASSED; - } else if (1U == msc->bot.csw.field.bCSWStatus) { + } else if (1U == msc->bbb.csw.field.bCSWStatus) { status = BBB_CSW_CMD_FAILED; - } else if (2U == msc->bot.csw.field.bCSWStatus) { + } else if (2U == msc->bbb.csw.field.bCSWStatus) { status = BBB_CSW_PHASE_ERROR; } else { /* no operation */ } } } else { - /* If the CSW signature is not valid, we shall return the phase error to + /* if the CSW signature is not valid, we shall return the phase error to upper layers for reset recovery */ status = BBB_CSW_PHASE_ERROR; } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c index 862a0f0..02212c0 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c @@ -2,12 +2,11 @@ \file usbh_core.c \brief USB MSC(mass storage device) class driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -79,7 +78,7 @@ static usbh_status usbh_msc_itf_init (usbh_host *uhost) } else { static usbh_msc_handler msc_handler; - memset((void*)&msc_handler, 0, sizeof(usbh_msc_handler)); + memset((void*)&msc_handler, 0U, sizeof(usbh_msc_handler)); uhost->active_class->class_data = (void *)&msc_handler; @@ -87,7 +86,7 @@ static usbh_status usbh_msc_itf_init (usbh_host *uhost) usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0]; - if (ep_desc->bEndpointAddress & 0x80) { + if (ep_desc->bEndpointAddress & 0x80U) { msc_handler.ep_in = ep_desc->bEndpointAddress; msc_handler.ep_size_in = ep_desc->wMaxPacketSize; } else { @@ -97,7 +96,7 @@ static usbh_status usbh_msc_itf_init (usbh_host *uhost) ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[1]; - if (ep_desc->bEndpointAddress & 0x80) { + if (ep_desc->bEndpointAddress & 0x80U) { msc_handler.ep_in = ep_desc->bEndpointAddress; msc_handler.ep_size_in = ep_desc->wMaxPacketSize; } else { @@ -201,7 +200,7 @@ static usbh_status usbh_msc_req (usbh_host *uhost) break; } - return status; + return status; } /*! @@ -224,108 +223,108 @@ static usbh_status usbh_msc_handle (usbh_host *uhost) msc->unit[msc->cur_lun].error = MSC_NOT_READY; switch (msc->unit[msc->cur_lun].state) { - case MSC_INIT: - msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY; - msc->timer = uhost->control.timer; - break; - - case MSC_READ_INQUIRY: - scsi_status = usbh_msc_scsi_inquiry(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry); - - if (USBH_OK == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; - } else if (scsi_status == USBH_FAIL) { - msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; - } else { - if (scsi_status == USBH_UNRECOVERED_ERROR) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } + case MSC_INIT: + msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY; + msc->timer = uhost->control.timer; + break; + + case MSC_READ_INQUIRY: + scsi_status = usbh_msc_scsi_inquiry (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry); + + if (USBH_OK == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + } else if (scsi_status == USBH_FAIL) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if (scsi_status == USBH_UNRECOVERED_ERROR) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; } - break; - - case MSC_TEST_UNIT_READY: - /* issue SCSI command TestUnitReady */ - ready_status = usbh_msc_test_unitready(uhost, msc->cur_lun); + } + break; - if (USBH_OK == ready_status) { - if (USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) { - msc->unit[msc->cur_lun].state_changed = 1U; - } else { - msc->unit[msc->cur_lun].state_changed = 0U; - } + case MSC_TEST_UNIT_READY: + /* issue SCSI command TestUnitReady */ + ready_status = usbh_msc_test_unitready (uhost, msc->cur_lun); - msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10; - msc->unit[msc->cur_lun].error = MSC_OK; - msc->unit[msc->cur_lun].prev_ready_state = USBH_OK; - } else if (USBH_FAIL == ready_status) { - if (USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) { - msc->unit[msc->cur_lun].state_changed = 1U; - } else { - msc->unit[msc->cur_lun].state_changed = 0U; - } + if (USBH_OK == ready_status) { + if (USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } - msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; - msc->unit[msc->cur_lun].error = MSC_NOT_READY; - msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL; + msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->unit[msc->cur_lun].prev_ready_state = USBH_OK; + } else if (USBH_FAIL == ready_status) { + if (USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; } else { - if (USBH_UNRECOVERED_ERROR == ready_status) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } + msc->unit[msc->cur_lun].state_changed = 0U; } - break; - case MSC_READ_CAPACITY10: - /* issue READ_CAPACITY10 SCSI command */ - scsi_status = usbh_msc_read_capacity10(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity); + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + msc->unit[msc->cur_lun].error = MSC_NOT_READY; + msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL; + } else { + if (USBH_UNRECOVERED_ERROR == ready_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; - if (USBH_OK == scsi_status) { - if (1U == msc->unit[msc->cur_lun].state_changed) { - } + case MSC_READ_CAPACITY10: + /* issue READ_CAPACITY10 SCSI command */ + scsi_status = usbh_msc_read_capacity10 (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity); + + if (USBH_OK == scsi_status) { + if (1U == msc->unit[msc->cur_lun].state_changed) { + } + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->cur_lun ++; + } else if (USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if (USBH_UNRECOVERED_ERROR == scsi_status) { msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_OK; - msc->cur_lun ++; - } else if (USBH_FAIL == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; - } else { - if (USBH_UNRECOVERED_ERROR == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } + msc->unit[msc->cur_lun].error = MSC_ERROR; } - break; - - case MSC_REQUEST_SENSE: - /* issue RequestSense SCSI command for receive error code */ - scsi_status = usbh_msc_request_sense (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense); - if (USBH_OK == scsi_status) { - if ((msc->unit[msc->cur_lun].sense.SenseKey == UNIT_ATTENTION) || (msc->unit[msc->cur_lun].sense.SenseKey == NOT_READY)) { - if (((uhost->control.timer > msc->timer) && ((uhost->control.timer - msc->timer) < 10000U)) \ - || ((uhost->control.timer < msc->timer) && ((uhost->control.timer + 0x3FFFU - msc->timer) < 10000U))){ - msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; - break; - } + } + break; + + case MSC_REQUEST_SENSE: + /* issue RequestSense SCSI command for retrieving error code */ + scsi_status = usbh_msc_request_sense (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense); + if (USBH_OK == scsi_status) { + if ((msc->unit[msc->cur_lun].sense.SenseKey == UNIT_ATTENTION) || (msc->unit[msc->cur_lun].sense.SenseKey == NOT_READY)) { + if (((uhost->control.timer > msc->timer) && ((uhost->control.timer - msc->timer) < 10000U)) \ + || ((uhost->control.timer < msc->timer) && ((uhost->control.timer + 0x3FFFU - msc->timer) < 10000U))) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + break; } + } + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->cur_lun++; + } else if (USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR; + } else { + if (MSC_UNRECOVERED_ERROR == scsi_status) { msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->cur_lun++; - } else if (USBH_FAIL == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR; - } else { - if (MSC_UNRECOVERED_ERROR == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } + msc->unit[msc->cur_lun].error = MSC_ERROR; } - break; + } + break; - case MSC_UNRECOVERED_ERROR: - msc->cur_lun ++; - break; + case MSC_UNRECOVERED_ERROR: + msc->cur_lun++; + break; - default: - break; + default: + break; } } else { msc->cur_lun = 0U; @@ -386,7 +385,7 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun) usbh_status scsi_status = USBH_BUSY; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - /* switch MSC req state machine */ + /* switch msc req state machine */ switch (msc->unit[lun].state) { case MSC_READ: scsi_status = usbh_msc_read10(uhost, lun, NULL, 0U, 0U); @@ -410,7 +409,7 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun) if (USBH_OK == scsi_status) { msc->unit[lun].state = MSC_IDLE; error = USBH_OK; - } else if(USBH_FAIL == scsi_status) { + } else if (USBH_FAIL == scsi_status) { msc->unit[lun].state = MSC_REQUEST_SENSE; } else { if (USBH_UNRECOVERED_ERROR == scsi_status) { @@ -468,7 +467,7 @@ usbh_status usbh_msc_lun_info_get (usbh_host *uhost, uint8_t lun, msc_lun *info) } /*! - \brief handle MSC read operation + \brief handle msc read operation \param[in] uhost: pointer to USB host \param[in] lun: logic unit number \param[in] address: data address @@ -502,8 +501,8 @@ usbh_status usbh_msc_read (usbh_host *uhost, timeout = uhost->control.timer; while (USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) { - if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (1000U * length))) \ - || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (1000U * length))) \ + if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (10000U * length))) \ + || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (10000U * length))) \ || (0U == udev->host.connect_status)){ msc->state = MSC_IDLE; return USBH_FAIL; @@ -516,7 +515,7 @@ usbh_status usbh_msc_read (usbh_host *uhost, } /*! - \brief handle MSC write operation + \brief handle msc write operation \param[in] uhost: pointer to USB host \param[in] lun: logic unit number \param[in] address: data address @@ -550,8 +549,8 @@ usbh_status usbh_msc_write (usbh_host *uhost, timeout = uhost->control.timer; while (USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) { - if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (1000U * length))) \ - || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (1000U * length))) \ + if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (10000U * length))) \ + || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (10000U * length))) \ || (0U == udev->host.connect_status)){ msc->state = MSC_IDLE; return USBH_FAIL; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c index c7c9e28..f38fb9f 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c @@ -2,12 +2,11 @@ \file usbh_msc_fatfs.c \brief USB MSC host FATFS related functions - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -206,7 +205,7 @@ DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) /* get erase block size in unit of sector (dword) */ case GET_BLOCK_SIZE: - *(DWORD*)buff = 512; + *(DWORD *)buff = 512U; break; default: @@ -223,12 +222,12 @@ DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) \param[out] none \retval time value */ -DWORD get_fattime(void) { - - return ((DWORD)(2019U - 1980U) << 25U) /* year 2019 */ - | ((DWORD)1U << 21U) /* month 1 */ - | ((DWORD)1U << 16U) /* day 1 */ - | ((DWORD)0U << 11U) /* hour 0 */ - | ((DWORD)0U << 5U) /* min 0 */ - | ((DWORD)0U >> 1U); /* sec 0 */ +DWORD get_fattime (void) +{ + return ((DWORD)(2019U - 1980U) << 25U) /* year 2019 */ + | ((DWORD)1U << 21U) /* month 1 */ + | ((DWORD)1U << 16U) /* day 1 */ + | ((DWORD)0U << 11U) /* hour 0 */ + | ((DWORD)0U << 5U) /* min 0 */ + | ((DWORD)0U >> 1U); /* sec 0 */ } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c index cbd57ed..57b1077 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c @@ -2,12 +2,11 @@ \file usbh_msc_scsi.c \brief USB MSC SCSI commands implemention - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -52,22 +51,22 @@ usbh_status usbh_msc_scsi_inquiry (usbh_host *uhost, uint8_t lun, scsi_std_inqui usbh_status error = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: /* prepare the cbw and relevant field*/ - msc->bot.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_INQUIRY; - msc->bot.cbw.field.CBWCB[1] = (lun << 5U); - msc->bot.cbw.field.CBWCB[4] = 0x24U; + msc->bbb.cbw.field.CBWCB[0] = SCSI_INQUIRY; + msc->bbb.cbw.field.CBWCB[1] = (lun << 5U); + msc->bbb.cbw.field.CBWCB[4] = 0x24U; - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; error = USBH_BUSY; break; @@ -78,18 +77,18 @@ usbh_status usbh_msc_scsi_inquiry (usbh_host *uhost, uint8_t lun, scsi_std_inqui memset(inquiry, 0U, sizeof(scsi_std_inquiry_data)); /* assign inquiry data */ - inquiry->device_type = msc->bot.pbuf[0] & 0x1FU; - inquiry->peripheral_qualifier = msc->bot.pbuf[0] >> 5U; + inquiry->device_type = msc->bbb.pbuf[0] & 0x1FU; + inquiry->peripheral_qualifier = msc->bbb.pbuf[0] >> 5U; - if (0x80U == ((uint32_t)msc->bot.pbuf[1] & 0x80U)) { + if (0x80U == ((uint32_t)msc->bbb.pbuf[1] & 0x80U)) { inquiry->removable_media = 1U; } else { inquiry->removable_media = 0U; } - memcpy (inquiry->vendor_id, &msc->bot.pbuf[8], 8U); - memcpy (inquiry->product_id, &msc->bot.pbuf[16], 16U); - memcpy (inquiry->revision_id, &msc->bot.pbuf[32], 4U); + memcpy (inquiry->vendor_id, &msc->bbb.pbuf[8], 8U); + memcpy (inquiry->product_id, &msc->bbb.pbuf[16], 16U); + memcpy (inquiry->revision_id, &msc->bbb.pbuf[32], 4U); } break; @@ -113,18 +112,18 @@ usbh_status usbh_msc_test_unitready (usbh_host *uhost, uint8_t lun) usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_TEST_UNIT_READY; - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; + msc->bbb.cbw.field.CBWCB[0] = SCSI_TEST_UNIT_READY; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; status = USBH_BUSY; break; @@ -153,19 +152,19 @@ usbh_status usbh_msc_read_capacity10 (usbh_host *uhost, uint8_t lun, scsi_capaci usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_READ_CAPACITY10; - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.cbw.field.CBWCB[0] = SCSI_READ_CAPACITY10; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; status = USBH_BUSY; break; @@ -174,12 +173,12 @@ usbh_status usbh_msc_read_capacity10 (usbh_host *uhost, uint8_t lun, scsi_capaci status = usbh_msc_bbb_process(uhost, lun); if (USBH_OK == status) { - capacity->block_nbr = msc->bot.pbuf[3] | \ - ((uint32_t)msc->bot.pbuf[2] << 8U) | \ - ((uint32_t)msc->bot.pbuf[1] << 16U) | \ - ((uint32_t)msc->bot.pbuf[0] << 24U); + capacity->block_nbr = msc->bbb.pbuf[3] | \ + ((uint32_t)msc->bbb.pbuf[2] << 8U) | \ + ((uint32_t)msc->bbb.pbuf[1] << 16U) | \ + ((uint32_t)msc->bbb.pbuf[0] << 24U); - capacity->block_size = (uint16_t)(msc->bot.pbuf[7] | ((uint32_t)msc->bot.pbuf[6] << 8U)); + capacity->block_size = (uint16_t)(msc->bbb.pbuf[7] | ((uint32_t)msc->bbb.pbuf[6] << 8U)); } break; @@ -203,21 +202,21 @@ usbh_status usbh_msc_mode_sense6 (usbh_host *uhost, uint8_t lun) usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_MODE_SENSE6; - msc->bot.cbw.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; - msc->bot.cbw.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.cbw.field.CBWCB[0] = SCSI_MODE_SENSE6; + msc->bbb.cbw.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; + msc->bbb.cbw.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; status = USBH_BUSY; break; @@ -226,7 +225,7 @@ usbh_status usbh_msc_mode_sense6 (usbh_host *uhost, uint8_t lun) status = usbh_msc_bbb_process(uhost, lun); if (USBH_OK == status) { - if (msc->bot.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) { + if (msc->bbb.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) { } else { @@ -255,22 +254,22 @@ usbh_status usbh_msc_request_sense (usbh_host *uhost, uint8_t lun, msc_scsi_sens usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: /* prepare the cbw and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_REQUEST_SENSE; - msc->bot.cbw.field.CBWCB[1] = (lun << 5U); - msc->bot.cbw.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + msc->bbb.cbw.field.CBWCB[0] = SCSI_REQUEST_SENSE; + msc->bbb.cbw.field.CBWCB[1] = (lun << 5U); + msc->bbb.cbw.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; status = USBH_BUSY; break; @@ -280,9 +279,9 @@ usbh_status usbh_msc_request_sense (usbh_host *uhost, uint8_t lun, msc_scsi_sens if (status == USBH_OK) { /* get sense data */ - sense_data->SenseKey = msc->bot.pbuf[2] & 0x0FU; - sense_data->ASC = msc->bot.pbuf[12]; - sense_data->ASCQ = msc->bot.pbuf[13]; + sense_data->SenseKey = msc->bbb.pbuf[2] & 0x0FU; + sense_data->ASC = msc->bbb.pbuf[12]; + sense_data->ASCQ = msc->bbb.pbuf[13]; } break; @@ -308,29 +307,29 @@ usbh_status usbh_msc_write10 (usbh_host *uhost, uint8_t lun, uint8_t *data_buf, usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: - msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_WRITE10; + msc->bbb.cbw.field.CBWCB[0] = SCSI_WRITE10; /* logical block address */ - msc->bot.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); - msc->bot.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); - msc->bot.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); - msc->bot.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + msc->bbb.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc->bbb.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc->bbb.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc->bbb.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); /* transfer length */ - msc->bot.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); - msc->bot.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + msc->bbb.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bbb.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; - msc->bot.pbuf = data_buf; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = data_buf; status = USBH_BUSY; break; @@ -361,30 +360,30 @@ usbh_status usbh_msc_read10 (usbh_host *uhost, uint8_t lun, uint8_t *data_buf, u usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { + switch (msc->bbb.cmd_state) { case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_READ10; + msc->bbb.cbw.field.CBWCB[0] = SCSI_READ10; /* logical block address */ - msc->bot.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); - msc->bot.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); - msc->bot.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); - msc->bot.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + msc->bbb.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc->bbb.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc->bbb.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc->bbb.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); /* transfer length */ - msc->bot.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); - msc->bot.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + msc->bbb.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bbb.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); - msc->bot.state = BBB_SEND_CBW; - msc->bot.cmd_state = BBB_CMD_WAIT; - msc->bot.pbuf = data_buf; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = data_buf; status = USBH_BUSY; break; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_core.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_core.h index 47aad4a..e600e52 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_core.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_core.h @@ -2,12 +2,11 @@ \file usbh_core.h \brief USB host core state machine header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -119,6 +118,14 @@ typedef enum USR_IN_RESP_OK = 1U, } usbh_user_status; +/* USB host wakeup mode */ +typedef enum +{ + NORMAL_WORK = 0U, + GENERAL_WAKEUP = 1U, + REMOTE_WAKEUP = 2, +} usbh_wakeup_mode; + /* control transfer information */ typedef struct _usbh_control { @@ -171,7 +178,7 @@ struct _usbh_host; /* device class callbacks */ typedef struct { - uint8_t class_code; /*!< USB class type */ + uint8_t class_code; /*!< USB class type */ usbh_status (*class_init) (struct _usbh_host *phost); void (*class_deinit) (struct _usbh_host *phost); @@ -226,11 +233,9 @@ typedef struct _usbh_host void *data; /*!< used for... */ -#if USB_LOW_POWER uint8_t suspend_flag; /*!< host suspend flag */ uint8_t dev_supp_remote_wkup; /*!< record device remote wakeup function */ - uint8_t wakeup_mode; /*!< record wakeup mode */ -#endif /* USB_LOW_POWER*/ + usbh_wakeup_mode wakeup_mode; /*!< record wakeup mode */ } usbh_host; /*! @@ -268,9 +273,5 @@ usbh_status usbh_deinit (usbh_host *uhost); void usbh_core_task (usbh_host *uhost); /* handle the error on USB host side */ void usbh_error_handler (usbh_host *uhost, usbh_status err_type); -#ifdef USB_LOW_PWR_ENABLE -/* handles the USB resume from suspend mode */ -void usb_hwp_resume(usb_core_driver *udev); -#endif /* USB_LOW_PWR_ENABLE */ #endif /* __USBH_CORE_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_enum.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_enum.h index d6b21a0..8a3b02f 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_enum.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_enum.h @@ -2,12 +2,11 @@ \file usbh_enum.h \brief USB host mode USB enumeration header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h index f3d2e34..922b233 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h @@ -2,12 +2,11 @@ \file usbh_pipe.h \brief USB host mode pipe header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_transc.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_transc.h index 5b2bc91..183a092 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_transc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Include/usbh_transc.h @@ -2,12 +2,11 @@ \file usbh_transc.h \brief USB host mode transactions header file - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_core.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_core.c index 101415b..3ff8667 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_core.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_core.c @@ -2,12 +2,11 @@ \file usbh_core.c \brief USB host core state machine driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -45,10 +44,10 @@ static uint8_t usb_ev_sof (usbh_host *uhost); static uint8_t usb_ev_connect (usbh_host *uhost); static uint8_t usb_ev_disconnect (usbh_host *uhost); static usbh_status usbh_enum_task (usbh_host *uhost); -#if USB_LOW_POWER +#if USBFS_LOW_POWER || USBHS_LOW_POWER static void usb_hwp_suspend (usb_core_driver *udev); static void usb_hwp_resume (usb_core_driver *udev); -#endif /* USB_LOW_POWER */ +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ usbh_ev_cb usbh_int_op = { @@ -62,12 +61,18 @@ usbh_ev_cb *usbh_int_fop = &usbh_int_op; /*! \brief USB host stack initializations \param[in] uhost: pointer to USB host + \param[in] udev: pointer to USB device instance + \param[in] usb_core: USB core type \param[in] user_cb: pointer to user callback \param[out] none \retval none */ void usbh_init (usbh_host *uhost, usb_core_driver *udev, usb_core_enum usb_core, usbh_user_cb *user_cb) { + /* link driver to the stack */ + udev->host.data = (void *)uhost; + uhost->data = (void *)udev; + /* host deinitialization */ usbh_deinit(uhost); @@ -99,10 +104,6 @@ void usbh_init (usbh_host *uhost, usb_core_driver *udev, usb_core_enum usb_core, usb_globalint_enable(&udev->regs); #endif /* DUAL_ROLE_MODE_ENABLED */ - /* link driver to the stack */ - udev->host.data = (void *)uhost; - uhost->data = (void *)udev; - /* upon initialize call usr call back */ uhost->usr_cb->dev_init(); } @@ -132,7 +133,7 @@ usbh_status usbh_class_register (usbh_host *uhost, usbh_class *puclass) } /*! - \brief de-initialize USB host + \brief deinitialize USB host \param[in] uhost: pointer to USB host \param[out] none \retval operation status @@ -232,10 +233,10 @@ void usbh_core_task (usbh_host *uhost) /* user callback for end of device basic enumeration */ uhost->usr_cb->dev_enumerated(); -#if USB_LOW_POWER +#if USBFS_LOW_POWER || USBHS_LOW_POWER uhost->cur_state = HOST_SUSPEND; - /* judge device remote wakup function */ + /* judge device remote wakeup function */ if ((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { uhost->dev_supp_remote_wkup = 1; }else{ @@ -243,7 +244,7 @@ void usbh_core_task (usbh_host *uhost) } #else uhost->cur_state = HOST_PWR_FEATURE_SET; -#endif /* USB_LOW_POWER */ +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ } break; @@ -288,55 +289,54 @@ void usbh_core_task (usbh_host *uhost) } break; -#if USB_LOW_POWER +#if USBFS_LOW_POWER || USBHS_LOW_POWER case HOST_SUSPEND: if(uhost->dev_supp_remote_wkup){ /* send set feature command*/ - if (USBH_OK == usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U)) { + if (USBH_OK == usbh_setdevfeature (uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U)) { - usb_hwp_suspend(udev); + usb_hwp_suspend (udev); - usb_mdelay(20U); + usb_mdelay (20U); uhost->suspend_flag = 1; uhost->usr_cb->dev_user_input(); /* MCU enter deep-sleep*/ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); uhost->cur_state = HOST_WAKEUP; } - }else { + } else { /* host suspend */ - usb_hwp_suspend(udev); + usb_hwp_suspend (udev); usb_mdelay(20U); uhost->suspend_flag = 1U; uhost->usr_cb->dev_user_input(); /* MCU enter deep-sleep */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); uhost->cur_state = HOST_WAKEUP; } break; case HOST_WAKEUP: /* judge suspend status */ - if (0 == uhost->suspend_flag) { - gd_eval_lcd_init(); + if (0U == uhost->suspend_flag) { usb_hwp_resume(udev); usb_mdelay(500U); - if(uhost->dev_supp_remote_wkup){ - if (USBH_OK == usbh_clrdevfeature(uhost, FEATURE_SELECTOR_DEV, 0U)) { + if (uhost->dev_supp_remote_wkup) { + if (USBH_OK == usbh_clrdevfeature (uhost, FEATURE_SELECTOR_DEV, 0U)) { /* user callback for initialization */ uhost->usr_cb->dev_init(); uhost->cur_state = HOST_CLASS_CHECK; } - } else{ + } else { uhost->cur_state = HOST_CLASS_CHECK; } } break; -#endif /* USB_LOW_POWER */ +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ case HOST_CLASS_ENUM: /* process class standard control requests state machine */ @@ -357,7 +357,7 @@ void usbh_core_task (usbh_host *uhost) break; case HOST_ERROR: - /* initialize host for new enumeration */ + /* deinitialize host for new enumeration */ usbh_deinit (uhost); uhost->usr_cb->dev_deinit(); uhost->active_class->class_deinit(uhost); @@ -368,7 +368,7 @@ void usbh_core_task (usbh_host *uhost) uhost->usr_cb->dev_detach(); /* re-initialize host for new enumeration */ - usbh_deinit(uhost); + usbh_deinit (uhost); uhost->usr_cb->dev_deinit(); uhost->active_class->class_deinit(uhost); usbh_pipe_delete(udev); @@ -602,7 +602,7 @@ static usbh_status usbh_enum_task (usbh_host *uhost) return status; } -#if USB_LOW_POWER +#if USBFS_LOW_POWER || USBHS_LOW_POWER /*! \brief handles the USB resume from suspend mode @@ -655,4 +655,4 @@ static void usb_hwp_suspend(usb_core_driver *udev) *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; } -#endif /* USB_LOW_POWER */ +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_enum.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_enum.c index 751ca87..053cb7f 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_enum.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_enum.c @@ -2,12 +2,11 @@ \file usbh_enum.c \brief USB host mode enumeration driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -116,7 +115,7 @@ usbh_status usbh_cfgdesc_get (usbh_host *uhost, uint16_t len) pdata = uhost->dev_prop.cfgdesc_rawdata; #else pdata = uhost->dev_prop.data; -#endif /* USBH_CFG_DESC_KEEP */ +#endif /* (USBH_CFG_DESC_KEEP == 1U) */ if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req) { @@ -677,13 +676,13 @@ static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len) if (USB_DESCTYPE_STR == psrc[1]) { /* make sure the descriptor is string type */ - /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ str_len = USB_MIN((uint16_t)psrc[0] - 2U, len); - psrc += 2U; /* adjust the offset ignoring the string len and descriptor type */ + psrc += 2U; /* adjust the offset ignoring the string length and descriptor type */ - for (index = 0U; index < str_len; index += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ + for(index = 0U; index < str_len; index += 2U) { + /* copy only the string and ignore the unicode id, hence add the source */ *pdest = psrc[index]; pdest++; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c index d19edde..82d1184 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c @@ -2,12 +2,11 @@ \file usbh_pipe.c \brief USB host mode pipe operation driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -61,7 +60,7 @@ uint8_t usbh_pipe_create (usb_core_driver *udev, pp->ep.type = ep_type; pp->ep.mps = ep_mpl; - if ((USB_USE_DMA != udev->bp.transfer_mode) && ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) { + if (((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) { pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH); } @@ -95,7 +94,7 @@ uint8_t usbh_pipe_update (usb_core_driver *udev, if ((pp->dev_speed != dev_speed) && (dev_speed)) { pp->dev_speed = dev_speed; - if ((USB_USE_DMA != udev->bp.transfer_mode) && ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) { + if (((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) { pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH); } } diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_transc.c b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_transc.c index b271a2d..9b5a6fe 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_transc.c +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/host/core/Source/usbh_transc.c @@ -2,12 +2,11 @@ \file usbh_transc.c \brief USB host mode transactions driver - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -38,12 +37,12 @@ OF SUCH DAMAGE. #include "usbh_transc.h" /* local function prototypes ('static') */ -static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time); -static void usbh_setup_transc (usbh_host *uhost); -static void usbh_data_in_transc (usbh_host *uhost); -static void usbh_data_out_transc (usbh_host *uhost); -static void usbh_status_in_transc (usbh_host *uhost); -static void usbh_status_out_transc (usbh_host *uhost); +static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time); +static void usbh_setup_transc (usbh_host *uhost); +static void usbh_data_in_transc (usbh_host *uhost); +static void usbh_data_out_transc (usbh_host *uhost); +static void usbh_status_in_transc (usbh_host *uhost); +static void usbh_status_out_transc (usbh_host *uhost); static uint32_t usbh_request_submit (usb_core_driver *udev, uint8_t pp_num); /*! @@ -137,7 +136,7 @@ usbh_status usbh_data_recev (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num case USB_EPTYPE_INTR: pp->DPID = PIPE_DPID[pp->data_toggle_in]; - /* Toggle DATA PID */ + /* toggle DATA PID */ pp->data_toggle_in ^= 1U; break; @@ -234,7 +233,7 @@ static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t w } else if (URB_ERROR == urb_status) { uhost->control.ctl_state = CTL_ERROR; break; - }else if ((wait_time > 0U) && (((usb_curframe_get(uhost->data) > timeout) && ((usb_curframe_get(uhost->data) - timeout) > wait_time)) \ + } else if ((wait_time > 0U) && (((usb_curframe_get(uhost->data) > timeout) && ((usb_curframe_get(uhost->data) - timeout) > wait_time)) \ || ((usb_curframe_get(uhost->data) < timeout) && ((usb_curframe_get(uhost->data) + 0x3FFFU - timeout) > wait_time)))){ /* timeout for in transfer */ uhost->control.ctl_state = CTL_ERROR; diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h index 3e36621..1a9825a 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h @@ -2,12 +2,11 @@ \file usb_cdc.h \brief the header file of communication device class standard - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h index bfee9a5..4a2989e 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h @@ -2,12 +2,11 @@ \file usb_hid.h \brief definitions for the USB HID class - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -79,6 +78,6 @@ typedef struct usb_desc_hid hid_vendor; usb_desc_ep hid_epin; usb_desc_ep hid_epout; -}usb_hid_desc_config_set; +} usb_hid_desc_config_set; #endif /* __USB_HID_H */ diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h index 3ca8474..db8ed97 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h @@ -2,12 +2,11 @@ \file msc_bbb.h \brief definitions for the USB MSC BBB(bulk/bulk/bulk) protocol - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -51,14 +50,14 @@ typedef struct { uint8_t bCBWLUN; uint8_t bCBWCBLength; uint8_t CBWCB[16]; -}msc_bbb_cbw; +} msc_bbb_cbw; typedef struct { uint32_t dCSWSignature; uint32_t dCSWTag; uint32_t dCSWDataResidue; uint8_t bCSWStatus; -}msc_bbb_csw; +} msc_bbb_csw; /* CSW command status */ enum msc_csw_status { diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h index 9d35dd4..176b303 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h @@ -2,12 +2,11 @@ \file msc_scsi.h \brief definitions for the USB MSC SCSI commands - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h index a72d5e8..b998cc7 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h @@ -2,12 +2,11 @@ \file usb_msc.h \brief definitions for the USB MSC class - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h index 34cd326..1db0f0e 100644 --- a/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h +++ b/lib-gd32/gd32f4xx/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h @@ -2,12 +2,11 @@ \file usb_ch9_std.h \brief USB 2.0 standard defines - \version 2020-08-01, V3.0.0, firmware for GD32F4xx - \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2023-06-25, V3.1.0, firmware for GD32F4xx */ /* - Copyright (c) 2022, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -238,7 +237,7 @@ typedef struct _usb_desc_LANGID { typedef struct _usb_desc_str { usb_desc_header header; /*!< descriptor header, including type and size. */ - uint16_t unicode_string[64]; /*!< unicode string data */ + uint16_t unicode_string[128]; /*!< unicode string data */ } usb_desc_str; #pragma pack() diff --git a/lib-gd32/include/board/gd32f470z_eval.h b/lib-gd32/include/board/gd32f470z_eval.h new file mode 100644 index 0000000..9d33d62 --- /dev/null +++ b/lib-gd32/include/board/gd32f470z_eval.h @@ -0,0 +1,194 @@ +/** + * @file gd32f470z_eval.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef BOARD_GD32F470Z_EVAL_H_ +#define BOARD_GD32F470Z_EVAL_H_ + +#include + +#if !defined(BOARD_GD32F470Z_EVAL) +# error This file should not be included +#endif + +#if defined (MCU_GD32F470_MCU_H_) +# error This file should be included later +#endif + +/** + * LEDs + */ + +#define LED1_GPIO_PINx GPIO_PIN_4 +#define LED1_GPIOx GPIOD +#define LED1_RCU_GPIOx RCU_GPIOD + +#define LED2_GPIO_PINx GPIO_PIN_5 +#define LED2_GPIOx GPIOD +#define LED2_RCU_GPIOx RCU_GPIOD + +#define LED3_GPIO_PINx GPIO_PIN_3 +#define LED3_GPIOx GPIOG +#define LED3_RCU_GPIOx RCU_GPIOG + +#define LED_BLINK_PIN LED1_GPIO_PINx +#define LED_BLINK_GPIO_PORT LED1_GPIOx +#define LED_BLINK_GPIO_CLK LED1_RCU_GPIOx + +/** + * KEYs + */ + +#define KEY1_PINx GPIO_PIN_0 +#define KEY1_GPIOx GPIOA +#define KEY1_RCU_GPIOx RCU_GPIOA + +#define KEY2_PINx GPIO_PIN_13 +#define KEY2_GPIOx GPIOC +#define KEY2_RCU_GPIOx RCU_GPIOC + +#define KEY3_PINx GPIO_PIN_14 +#define KEY3_GPIOx GPIOB +#define KEY3_RCU_GPIOx RCU_GPIOB + +#define KEY_BOOTLOADER_TFTP_GPIO_PINx KEY2_PINx +#define KEY_BOOTLOADER_TFTP_GPIOx KEY2_GPIOx +#define KEY_BOOTLOADER_TFTP_RCU_GPIOx KEY2_RCU_GPIOx + +/** + * I2C + */ + +#define I2C_PERIPH I2C0_PERIPH +#define I2C_RCU_CLK I2C0_RCU_CLK +#define I2C_GPIO_SCL_PORT I2C0_SCL_GPIOx +#define I2C_GPIO_SCL_CLK I2C0_SCL_RCU_GPIOx +#define I2C_GPIO_SDA_PORT I2C0_SDA_GPIOx +#define I2C_GPIO_SDA_CLK I2C0_SDA_RCU_GPIOx +#define I2C_SCL_PIN I2C0_SCL_GPIO_PINx +#define I2C_SDA_PIN I2C0_SDA_GPIO_PINx + +/** + * SPI + */ + +#define SPI_PERIPH SPI5_PERIPH +#define SPI_NSS_GPIOx SPI5_NSS_GPIOx +#define SPI_NSS_RCU_GPIOx SPI5_NSS_RCU_GPIOx +#define SPI_NSS_GPIO_PINx SPI5_NSS_GPIO_PINx +#define SPI_RCU_CLK SPI5_RCU_CLK +#define SPI_GPIOx SPI5_GPIOx +#define SPI_RCU_GPIOx SPI5_RCU_GPIOx +#define SPI_SCK_PIN SPI5_SCK_GPIO_PINx +#define SPI_MISO_PIN SPI5_MISO_GPIO_PINx +#define SPI_MOSI_PIN SPI5_MOSI_GPIO_PINx +#define SPI_IO2_PIN SPI5_IO2_GPIO_PINx +#define SPI_IO3_PIN SPI5_IO3_GPIO_PINx +#define SPI_DMAx SPI5_DMAx +#define SPI_DMA_CHx SPI5_TX_DMA_CHx +#define SPI_DMA_SUBPERIx SPI5_TX_DMA_SUBPERIx + +/** + * U(S)ART + */ + +/** + * Panel LEDs + */ +#ifdef __cplusplus +namespace hal { +namespace panelled { +static constexpr uint32_t ACTIVITY = 0; +static constexpr uint32_t ARTNET = 0; +static constexpr uint32_t DDP = 0; +static constexpr uint32_t SACN = 0; +static constexpr uint32_t LTC_IN = 0; +static constexpr uint32_t LTC_OUT = 0; +static constexpr uint32_t MIDI_IN = 0; +static constexpr uint32_t MIDI_OUT = 0; +static constexpr uint32_t OSC_IN = 0; +static constexpr uint32_t OSC_OUT = 0; +static constexpr uint32_t TCNET = 0; +// DMX +static constexpr uint32_t PORT_A_RX = 0; +static constexpr uint32_t PORT_A_TX = 0; +} // namespace panelled +} // namespace hal +#endif + +/** + * SPI flash + */ + +#define SPI_FLASH_CS_GPIOx SPI_NSS_GPIOx +#define SPI_FLASH_CS_RCU_GPIOx SPI_NSS_RCU_GPIOx +#define SPI_FLASH_CS_GPIO_PINx SPI_NSS_GPIO_PINx + +#define SPI_FLASH_WP_GPIO_PINx SPI_IO2_PIN +#define SPI_FLASH_HOLD_GPIO_PINx SPI_IO3_PIN + +/** + * EXT PHY + */ + +#define LINK_CHECK_GPIO_CLK RCU_GPIOB +#define LINK_CHECK_GPIO_PORT GPIOB +#define LINK_CHECK_GPIO_PIN GPIO_PIN_0 +#define LINK_CHECK_EXTI_LINE EXTI_0 +#define LINK_CHECK_EXTI_IRQn EXTI0_IRQn +#define LINK_CHECK_IRQ_HANDLE EXTI0_IRQHandler + +#define LINK_CHECK_EXTI_CLK RCU_SYSCFG +#define LINK_CHECK_EXTI_PORT_SOURCE EXTI_SOURCE_GPIOB +#define LINK_CHECK_EXTI_PIN_SOURCE EXTI_SOURCE_PIN0 +#define LINK_CHECK_EXTI_SOURCE_CONFIG syscfg_exti_line_config +#define LINK_CHECK_GPIO_CONFIG gpio_mode_set(LINK_CHECK_GPIO_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, LINK_CHECK_GPIO_PIN); + +/** + * MCU and BOARD name + */ + +#define GD32_MCU_NAME "GD32F470ZK" +#define GD32_BOARD_NAME "GD32F470Z_EVAL" + +#include "mcu/gd32f470_mcu.h" +#include "gd32_gpio.h" + +#define GD32_BOARD_LED1 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 0) +#define GD32_BOARD_LED2 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 2) +#define GD32_BOARD_LED3 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 3) +#define GD32_BOARD_STATUS_LED GD32_BOARD_LED1 + +/** + * SPI LCD + */ + +#define SPI_LCD_DC_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 11) +#define SPI_LCD_BL_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 12) +#define SPI_LCD_CS_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 13) +#define SPI_LCD_RST_PIN GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 14) + +#include "gpio_header.h" + +#endif /* BOARD_GD32F470Z_EVAL_H_ */ diff --git a/lib-gd32/include/gd32.h b/lib-gd32/include/gd32.h index 7a31f20..59c74ca 100644 --- a/lib-gd32/include/gd32.h +++ b/lib-gd32/include/gd32.h @@ -2,7 +2,7 @@ * @file gd32.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,25 +42,25 @@ #ifdef __cplusplus # pragma GCC diagnostic ignored "-Wold-style-cast" # pragma GCC diagnostic ignored "-Wuseless-cast" +# if __cplusplus > 201402 +// error: compound assignment with 'volatile'-qualified left operand is deprecated +# pragma GCC diagnostic ignored "-Wvolatile" +# endif extern "C" { #endif #if defined (GD32F10X_HD) || defined (GD32F10X_CL) # define GD32F10X # include "gd32f10x.h" -# include "gd32f10x_libopt.h" #elif defined (GD32F20X_CL) # define GD32F20X # include "gd32f20x.h" -# include "gd32f20x_libopt.h" #elif defined (GD32F30X_HD) # define GD32F30X # include "gd32f30x.h" -# include "gd32f30x_libopt.h" -#elif defined (GD32F407) || defined (GD32F450) +#elif defined (GD32F407) || defined (GD32F450) || defined (GD32F470) # define GD32F4XX # include "gd32f4xx.h" -# include "gd32f4xx_libopt.h" #else # error MCU is not supported #endif diff --git a/lib-gd32/include/gd32_board.h b/lib-gd32/include/gd32_board.h index bb1ec55..8ebd8bc 100644 --- a/lib-gd32/include/gd32_board.h +++ b/lib-gd32/include/gd32_board.h @@ -2,7 +2,7 @@ * @file gd32_board.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -48,6 +48,8 @@ # include "board/16x4u-pixel.h" #elif defined (BOARD_GD32F207C_EVAL) # include "board/gd32f207c_eval.h" +#elif defined (BOARD_GD32F470Z_EVAL) +# include "board/gd32f470z_eval.h" #elif defined (BOARD_BW_OPIDMX4) # include "board/bw_opidmx4.h" #elif defined (BOARD_DMX3) diff --git a/lib-gd32/include/gd32_gpio.h b/lib-gd32/include/gd32_gpio.h index 6b784b5..bd4cee0 100644 --- a/lib-gd32/include/gd32_gpio.h +++ b/lib-gd32/include/gd32_gpio.h @@ -2,7 +2,7 @@ * @file gd32_gpio.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -52,7 +52,7 @@ typedef enum T_GD32_Port { # define GPIO_PULL_DISABLE GPIO_MODE_IN_FLOATING # define GPIO_INT_CFG_NEG_EDGE EXTI_TRIG_FALLING # define GPIO_INT_CFG_BOTH EXTI_TRIG_BOTH -#elif defined (GD32F407) || defined (GD32F450) +#elif defined (GD32F407) || defined (GD32F450) || defined (GD32F470) # define GPIO_FSEL_OUTPUT GPIO_MODE_OUTPUT # define GPIO_FSEL_INPUT GPIO_MODE_INPUT # define GPIO_PULL_UP GPIO_PUPD_PULLUP diff --git a/lib-gd32/include/mcu/gd32f4xx_mcu.h b/lib-gd32/include/mcu/gd32f4xx_mcu.h index d8babb0..39190da 100644 --- a/lib-gd32/include/mcu/gd32f4xx_mcu.h +++ b/lib-gd32/include/mcu/gd32f4xx_mcu.h @@ -2,7 +2,7 @@ * @file gd32f4xx_mcu.h * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,7 +26,7 @@ #ifndef MCU_GD32F4XX_MCU_H_ #define MCU_GD32F4XX_MCU_H_ -#if !(defined(MCU_GD32F407_MCU_H_) || defined(MCU_GD32F450_MCU_H_)) +#if !(defined(MCU_GD32F407_MCU_H_) || defined(MCU_GD32F450_MCU_H_) || defined(MCU_GD32F470_MCU_H_)) # error This file should not be included #endif @@ -247,6 +247,19 @@ # define SPI2_MOSI_GPIO_PINx GPIO_PIN_5 #endif +#define SPI5_PERIPH SPI5 +#define SPI5_RCU_CLK RCU_SPI5 +#define SPI5_NSS_GPIOx GPIOG +#define SPI5_NSS_RCU_GPIOx RCU_GPIOG +#define SPI5_NSS_GPIO_PINx GPIO_PIN_9 +#define SPI5_GPIOx GPIOG +#define SPI5_RCU_GPIOx RCU_GPIOG +#define SPI5_SCK_GPIO_PINx GPIO_PIN_13 +#define SPI5_MISO_GPIO_PINx GPIO_PIN_15 +#define SPI5_MOSI_GPIO_PINx GPIO_PIN_14 +#define SPI5_IO2_GPIO_PINx GPIO_PIN_10 +#define SPI5_IO3_GPIO_PINx GPIO_PIN_11 + /** * TIMER GPIO */ @@ -272,6 +285,10 @@ #define SPI2_TX_DMA_CHx DMA_CH5 #define SPI2_TX_DMA_SUBPERIx DMA_SUBPERI0 +#define SPI5_DMAx DMA1 +#define SPI5_TX_DMA_CHx DMA_CH5 +#define SPI5_TX_DMA_SUBPERIx DMA_SUBPERI1 + #define TIMER2_RCU_DMAx RCU_DMA0 #define TIMER2_DMAx DMA0 #define TIMER2_CH0_DMA_CHx DMA_CH4 diff --git a/lib-hal/debug/emac/gd32/emac_debug.cpp b/lib-hal/debug/emac/gd32/emac_debug.cpp old mode 100644 new mode 100755 diff --git a/lib-hal/debug/i2c/i2cdetect.cpp b/lib-hal/debug/i2c/i2cdetect.cpp old mode 100644 new mode 100755 index bdcc4c2..ed496fb --- a/lib-hal/debug/i2c/i2cdetect.cpp +++ b/lib-hal/debug/i2c/i2cdetect.cpp @@ -2,7 +2,7 @@ * @file i2cdetect.cpp * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/debug/i2c/i2cdetect.h b/lib-hal/debug/i2c/i2cdetect.h old mode 100644 new mode 100755 index f7f4449..68bf63e --- a/lib-hal/debug/i2c/i2cdetect.h +++ b/lib-hal/debug/i2c/i2cdetect.h @@ -2,7 +2,7 @@ * @file i2cdetect.h * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/debug/stack/stack_debug.cpp b/lib-hal/debug/stack/stack_debug.cpp old mode 100644 new mode 100755 index 6ed1a88..9a0dc23 --- a/lib-hal/debug/stack/stack_debug.cpp +++ b/lib-hal/debug/stack/stack_debug.cpp @@ -2,7 +2,7 @@ * @file stack_debug.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -66,6 +66,7 @@ void stack_debug_print() { if (s_nUsedBytesPrevious != nUsedBytes) { s_nUsedBytesPrevious = nUsedBytes; + if (nFreePct == 0) { printf("\x1b[31m"); } else if (nFreePct == 1) { diff --git a/lib-hal/device/usb/host/gd32/usb_host.cpp b/lib-hal/device/usb/host/gd32/usb_host.cpp index c868013..5fcdf0a 100644 --- a/lib-hal/device/usb/host/gd32/usb_host.cpp +++ b/lib-hal/device/usb/host/gd32/usb_host.cpp @@ -2,7 +2,7 @@ * usb_host.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,13 @@ #include "gd32.h" +/** + * Needed for older GD32F firmware + */ +#if !defined(GPIO_OSPEED_MAX) +# define GPIO_OSPEED_MAX GPIO_OSPEED_200MHZ +#endif + extern "C" { #include "usbh_core.h" #include "usbh_msc_core.h" @@ -43,7 +50,7 @@ static void usb_gpio_config() { /* USBFS_DM(PA11) and USBFS_DP(PA12) GPIO pin configuration */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11 | GPIO_PIN_12); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_11 | GPIO_PIN_12); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_11 | GPIO_PIN_12); gpio_af_set(GPIOA, GPIO_AF_10, GPIO_PIN_11 | GPIO_PIN_12); #endif diff --git a/lib-hal/posix/file.c b/lib-hal/posix/file.c old mode 100644 new mode 100755 index 365e240..5784d6e --- a/lib-hal/posix/file.c +++ b/lib-hal/posix/file.c @@ -30,6 +30,7 @@ #include #include "../ff12c/ff.h" +//#include "../ff14b/source/ff.h" #include /* DO NOT MOVE -> DIR is defined in ff.h */ #include "debug.h" diff --git a/lib-network/config/net_config.h b/lib-network/config/net_config.h index c9fe09f..3f37ba1 100644 --- a/lib-network/config/net_config.h +++ b/lib-network/config/net_config.h @@ -56,7 +56,10 @@ # error # endif #else -# error +# define UDP_MAX_PORTS_ALLOWED 16 +# define IGMP_MAX_JOINS_ALLOWED (4 + (8 * 4)) /* 8 outputs x 4 Universes */ +# define TCP_MAX_TCBS_ALLOWED 16 +# define TCP_MAX_PORTS_ALLOWED 2 #endif #if !defined (UDP_MAX_PORTS_ALLOWED) diff --git a/lib-network/src/apps/tftp/tftpdaemon.cpp b/lib-network/src/apps/tftp/tftpdaemon.cpp index ca31123..d16d3fe 100644 --- a/lib-network/src/apps/tftp/tftpdaemon.cpp +++ b/lib-network/src/apps/tftp/tftpdaemon.cpp @@ -259,7 +259,7 @@ void TFTPDaemon::DoRead() { FileClose(); } - DEBUG_PRINTF("m_nDataLength=%ld, m_nPacketLength=%d, m_bIsLastBlock=%d", m_nDataLength, m_nPacketLength, m_bIsLastBlock); + DEBUG_PRINTF("m_nDataLength=%u, m_nPacketLength=%d, m_bIsLastBlock=%d", static_cast(m_nDataLength), m_nPacketLength, m_bIsLastBlock); } DEBUG_PRINTF("Sending to " IPSTR ":%d", IP2STR(m_nFromIp), m_nFromPort); diff --git a/lib-network/src/emac/gd32/emac.cpp b/lib-network/src/emac/gd32/emac.cpp index 811fedf..449c63b 100644 --- a/lib-network/src/emac/gd32/emac.cpp +++ b/lib-network/src/emac/gd32/emac.cpp @@ -2,7 +2,7 @@ * emac.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,13 @@ #include "debug.h" +/** + * Needed for older GD32F firmware + */ +#if !defined(GPIO_OSPEED_MAX) +# define GPIO_OSPEED_MAX GPIO_OSPEED_200MHZ +#endif + extern enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; extern void mac_address_get(uint8_t paddr[]); @@ -85,7 +92,7 @@ static void enet_gpio_config(void) { gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8); gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_8); /* choose DIV4 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */ rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4); @@ -93,15 +100,15 @@ static void enet_gpio_config(void) { /* PA1: ETH_RMII_REF_CLK */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_1); /* PA2: ETH_MDIO */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_2); /* PA7: ETH_RMII_CRS_DV */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_7); gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1); gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2); @@ -109,15 +116,15 @@ static void enet_gpio_config(void) { /* PB11: ETH_RMII_TX_EN */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_11); /* PB12: ETH_RMII_TXD0 */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_13); /* PB13: ETH_RMII_TXD1 */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_14); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_14); gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11); gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12); @@ -125,15 +132,15 @@ static void enet_gpio_config(void) { /* PC1: ETH_MDC */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_1); /* PC4: ETH_RMII_RXD0 */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_4); /* PC5: ETH_RMII_RXD1 */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_5); gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1); gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4); diff --git a/lib-properties/include/devicesparamsconst.h b/lib-properties/include/devicesparamsconst.h index 427745e..2d65ff7 100644 --- a/lib-properties/include/devicesparamsconst.h +++ b/lib-properties/include/devicesparamsconst.h @@ -2,7 +2,7 @@ * @file devicesparamsconst.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,8 +36,6 @@ struct DevicesParamsConst { static const char LED_T1H[]; static const char COUNT[]; - - static const char GROUPING_ENABLED[]; static const char GROUPING_COUNT[]; static const char SPI_SPEED_HZ[]; diff --git a/lib-properties/src/devicesparamsconst.cpp b/lib-properties/src/devicesparamsconst.cpp index b79c99a..039acff 100644 --- a/lib-properties/src/devicesparamsconst.cpp +++ b/lib-properties/src/devicesparamsconst.cpp @@ -2,7 +2,7 @@ * @file devicesparamsconst.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,8 +35,6 @@ const char DevicesParamsConst::LED_T0H[] = "led_t0h"; const char DevicesParamsConst::LED_T1H[] = "led_t1h"; const char DevicesParamsConst::COUNT[] = "led_count"; - -const char DevicesParamsConst::GROUPING_ENABLED[] = "led_grouping"; const char DevicesParamsConst::GROUPING_COUNT[] = "led_group_count"; const char DevicesParamsConst::SPI_SPEED_HZ[] = "clock_speed_hz"; diff --git a/lib-rdm/Rules.mk b/lib-rdm/Rules.mk index 39bbbcd..59cc751 100644 --- a/lib-rdm/Rules.mk +++ b/lib-rdm/Rules.mk @@ -1,5 +1,5 @@ EXTRA_INCLUDES=../lib-rdmsensor/include ../lib-rdmsubdevice/include ../lib-dmx/include ../lib-properties/include ../lib-lightset/include -EXTRA_INCLUDES+=../lib-hal/include ../lib-network/include ../lib-display/include ../lib-configstore/include +EXTRA_INCLUDES+=../lib-network/include ../lib-display/include ifneq ($(MAKE_FLAGS),) ifeq (,$(findstring NODE_ARTNET,$(MAKE_FLAGS))) diff --git a/lib-rdmnet/Rules.mk b/lib-rdmnet/Rules.mk index ca22cfd..24887a1 100755 --- a/lib-rdmnet/Rules.mk +++ b/lib-rdmnet/Rules.mk @@ -1,2 +1 @@ -EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include ../lib-e131/include ../lib-network/include ../lib-lightset/include -EXTRA_INCLUDES+=../lib-configstore/include \ No newline at end of file +EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include ../lib-e131/include ../lib-network/include ../lib-lightset/include \ No newline at end of file diff --git a/lib-remoteconfig/Rules.mk b/lib-remoteconfig/Rules.mk index 748b69b..a1ddc32 100644 --- a/lib-remoteconfig/Rules.mk +++ b/lib-remoteconfig/Rules.mk @@ -1,6 +1,6 @@ $(info $$MAKE_FLAGS [${MAKE_FLAGS}]) -EXTRA_INCLUDES=../lib-network/include ../lib-properties/include ../lib-display/include ../lib-lightset/include ../lib-configstore/include +EXTRA_INCLUDES=../lib-network/include ../lib-properties/include ../lib-display/include ../lib-lightset/include EXTRA_INCLUDES+=../lib-flashcode/include ../lib-flashcodeinstall/include ifneq ($(MAKE_FLAGS),) @@ -25,7 +25,6 @@ ifneq ($(MAKE_FLAGS),) ifeq ($(findstring NODE_LTC_SMPTE,$(MAKE_FLAGS)), NODE_LTC_SMPTE) EXTRA_INCLUDES+=../lib-ltc/include ../lib-tcnet/include ../lib-gps/include ../lib-midi/include EXTRA_INCLUDES+=../lib-rgbpanel/include ../lib-ws28xx/include - EXTRA_INCLUDES+=../lib-device/include endif ifeq ($(findstring NODE_OSC_CLIENT,$(MAKE_FLAGS)), NODE_OSC_CLIENT) EXTRA_INCLUDES+=../lib-oscclient/include @@ -95,6 +94,5 @@ else EXTRA_INCLUDES+=../lib-rdmsensor/include ../lib-rdmsubdevice/include EXTRA_INCLUDES+=../lib-showfile/include EXTRA_INCLUDES+=../lib-dmxmonitor/include - EXTRA_INCLUDES+=../lib-device/include EXTRA_INCLUDES+=../lib-oscclient/include ../lib-oscserver/include endif diff --git a/lib-remoteconfig/include/httpd/http.h b/lib-remoteconfig/include/httpd/http.h new file mode 100755 index 0000000..323fed4 --- /dev/null +++ b/lib-remoteconfig/include/httpd/http.h @@ -0,0 +1,52 @@ +/** + * @file http.h + * + */ +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HTTPD_HTTP_H_ +#define HTTPD_HTTP_H_ + +namespace http { +static constexpr uint32_t BUFSIZE = 1440; +enum class Status { + OK = 200, + BAD_REQUEST = 400, + NOT_FOUND = 404, + REQUEST_TIMEOUT = 408, + REQUEST_ENTITY_TOO_LARGE = 413, + REQUEST_URI_TOO_LONG = 414, + INTERNAL_SERVER_ERROR = 500, + METHOD_NOT_IMPLEMENTED = 501, + VERSION_NOT_SUPPORTED = 505, + UNKNOWN_ERROR = 520 +}; +enum class RequestMethod { + GET, POST, UNKNOWN +}; + +enum class contentTypes { + TEXT_HTML, TEXT_CSS, TEXT_JS, APPLICATION_JSON, NOT_DEFINED +}; +} // namespace http + +#endif /* HTTPD_HTTP_H_ */ diff --git a/lib-remoteconfig/include/httpd/httpd.h b/lib-remoteconfig/include/httpd/httpd.h index b4479d0..8502138 100755 --- a/lib-remoteconfig/include/httpd/httpd.h +++ b/lib-remoteconfig/include/httpd/httpd.h @@ -2,7 +2,7 @@ * @file httpd.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,73 +28,35 @@ #include -#include "network.h" +#include "http.h" +#include "httpdhandlerequest.h" -namespace http { -static constexpr uint32_t BUFSIZE = 1440; -enum class Status { - OK = 200, - BAD_REQUEST = 400, - NOT_FOUND = 404, - REQUEST_TIMEOUT = 408, - REQUEST_ENTITY_TOO_LARGE = 413, - REQUEST_URI_TOO_LONG = 414, - INTERNAL_SERVER_ERROR = 500, - METHOD_NOT_IMPLEMENTED = 501, - VERSION_NOT_SUPPORTED = 505, - UNKNOWN_ERROR = 520 -}; -enum class RequestMethod { - GET, POST, UNKNOWN -}; +#include "network.h" -enum class contentTypes { - TEXT_HTML, TEXT_CSS, TEXT_JS, APPLICATION_JSON, NOT_DEFINED -}; -} // namespace http +#include "../../lib-network/config/net_config.h" class HttpDaemon { public: HttpDaemon(); + ~HttpDaemon(); + void Run() { uint32_t nConnectionHandle; - m_nBytesReceived = Network::Get()->TcpRead(m_nHandle, const_cast(reinterpret_cast(&m_RequestHeaderResponse)), nConnectionHandle); + const auto nBytesReceived = Network::Get()->TcpRead(m_nHandle, const_cast(reinterpret_cast(&m_RequestHeaderResponse)), nConnectionHandle); - if (__builtin_expect((m_nBytesReceived == 0), 1)) { + if (__builtin_expect((nBytesReceived == 0), 1)) { return; } - HandleRequest(nConnectionHandle); - } + DEBUG_PRINTF("nConnectionHandle=%u", nConnectionHandle); -private: - void HandleRequest(const uint32_t nConnectionHandle); - http::Status ParseRequest(); - http::Status ParseMethod(char *pLine); - http::Status ParseHeaderField(char *pLine); - http::Status HandleGet(); - http::Status HandlePost(bool hasDataOnly); - http::Status HandleGetTxt(); + pHandleRequest[nConnectionHandle]->HandleRequest(nBytesReceived, m_RequestHeaderResponse); + } private: - const char *m_pContentType; - char *m_pUri { nullptr }; - char *m_pFileData { nullptr }; - char *m_RequestHeaderResponse { nullptr }; - - uint32_t m_nContentLength { 0 }; - uint32_t m_nFileDataLength { 0 }; - uint32_t m_nRequestContentLength { 0 }; + HttpDeamonHandleRequest *pHandleRequest[TCP_MAX_TCBS_ALLOWED]; int32_t m_nHandle { -1 }; - uint32_t m_nBytesReceived { 0 }; - - http::Status m_Status { http::Status::UNKNOWN_ERROR }; - http::RequestMethod m_RequestMethod { http::RequestMethod::UNKNOWN }; - - bool m_bContentTypeJson { false }; - bool m_IsAction { false }; - - static char m_Content[http::BUFSIZE]; + char *m_RequestHeaderResponse { nullptr }; }; #endif /* HTTPD_H_ */ diff --git a/lib-remoteconfig/include/httpd/httpdhandlerequest.h b/lib-remoteconfig/include/httpd/httpdhandlerequest.h new file mode 100755 index 0000000..56856a7 --- /dev/null +++ b/lib-remoteconfig/include/httpd/httpdhandlerequest.h @@ -0,0 +1,76 @@ +/** + * @file httpdhandlerequest.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HTTPD_HTTPDHANDLEREQUEST_H_ +#define HTTPD_HTTPDHANDLEREQUEST_H_ + +#include + +#include "http.h" + +#include "debug.h" + +class HttpDeamonHandleRequest { +public: + HttpDeamonHandleRequest(uint32_t nConnectionHandle, int32_t nHandle) : m_nConnectionHandle(nConnectionHandle), m_nHandle(nHandle) { + DEBUG_ENTRY + DEBUG_PRINTF("m_nConnectionHandle=%u", m_nConnectionHandle); + DEBUG_EXIT + } + + void HandleRequest(const uint32_t nBytesReceived, char *pRequestHeaderResponse); + +private: + http::Status ParseRequest(); + http::Status ParseMethod(char *pLine); + http::Status ParseHeaderField(char *pLine); + http::Status HandleGet(); + http::Status HandleGetTxt(); + http::Status HandlePost(bool hasDataOnly); + +private: + uint32_t m_nConnectionHandle; + int32_t m_nHandle; + uint32_t m_nContentLength { 0 }; + uint32_t m_nFileDataLength { 0 }; + uint32_t m_nRequestContentLength { 0 }; + uint32_t m_nBytesReceived { 0 }; + + const char *m_pContentType; + char *m_pUri { nullptr }; + char *m_pFileData { nullptr }; + char *m_RequestHeaderResponse { nullptr }; + + http::Status m_Status { http::Status::UNKNOWN_ERROR }; + http::RequestMethod m_RequestMethod { http::RequestMethod::UNKNOWN }; + + bool m_bContentTypeJson { false }; + bool m_IsAction { false }; + + static char m_Content[http::BUFSIZE]; +}; + + +#endif /* HTTPD_HTTPDHANDLEREQUEST_H_ */ diff --git a/lib-remoteconfig/include/remoteconfig.h b/lib-remoteconfig/include/remoteconfig.h index c26539c..2f711dc 100644 --- a/lib-remoteconfig/include/remoteconfig.h +++ b/lib-remoteconfig/include/remoteconfig.h @@ -2,7 +2,7 @@ * @file remoteconfig.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,7 @@ #define REMOTECONFIG_H_ #include +#include #if defined (NODE_ARTNET_MULTI) # define NODE_ARTNET @@ -48,12 +49,15 @@ # include "node.h" #endif -#include "configstore.h" - #if defined(ENABLE_TFTP_SERVER) # include "tftp/tftpfileserver.h" #endif +#if defined (ENABLE_HTTPD) +# include "httpd/httpd.h" +#endif + +#include "configstore.h" #include "network.h" namespace remoteconfig { @@ -77,6 +81,7 @@ enum class Node { RDMRESPONDER, LAST }; + enum class Output { DMX, RDM, @@ -94,11 +99,6 @@ enum class Output { LAST }; -enum { - DISPLAY_NAME_LENGTH = 24, - ID_LENGTH = (32 + remoteconfig::DISPLAY_NAME_LENGTH + 2) // +2, comma and \n -}; - enum class TxtFile { RCONFIG, NETWORK, @@ -130,11 +130,16 @@ enum class TxtFile { NODE, LAST }; + +enum { + DISPLAY_NAME_LENGTH = 24, + ID_LENGTH = (32 + remoteconfig::DISPLAY_NAME_LENGTH + 2) // +2, comma and \n +}; } // namespace remoteconfig class RemoteConfig { public: - RemoteConfig(remoteconfig::Node tType, remoteconfig::Output tMode, uint32_t nOutputs = 0); + RemoteConfig(const remoteconfig::Node node, const remoteconfig::Output output, const uint32_t nActiveOutputs = 0); ~RemoteConfig(); const char *GetStringNode() const; @@ -210,6 +215,10 @@ class RemoteConfig { } #endif +#if defined (ENABLE_HTTPD) + m_pHttpDaemon->Run(); +#endif + uint16_t nForeignPort; m_nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&s_pUdpBuffer)), &m_nIPAddressFrom, &nForeignPort); @@ -516,6 +525,10 @@ class RemoteConfig { #endif bool m_bEnableTFTP { false }; +#if defined (ENABLE_HTTPD) + HttpDaemon *m_pHttpDaemon { nullptr }; +#endif + static char *s_pUdpBuffer; static RemoteConfig *s_pThis; diff --git a/lib-remoteconfig/src/httpd/httpd.cpp b/lib-remoteconfig/src/httpd/httpd.cpp index 7cf21c3..d508031 100755 --- a/lib-remoteconfig/src/httpd/httpd.cpp +++ b/lib-remoteconfig/src/httpd/httpd.cpp @@ -29,516 +29,42 @@ #include #include "httpd/httpd.h" -#include "../http/content/json_switch.h" -#include "remoteconfig.h" -#include "remoteconfigjson.h" -#include "properties.h" -#include "sscan.h" -#include "propertiesconfig.h" - -#include "hardware.h" #include "network.h" #include "mdns.h" -#include "display.h" - -#if defined(RDM_CONTROLLER) -# include "artnetnode.h" -#endif - -#include "debug.h" - -#if defined ENABLE_CONTENT -extern uint32_t get_file_content(const char *fileName, char *pDst, http::contentTypes& contentType); -#endif -char HttpDaemon::m_Content[http::BUFSIZE]; +#include "../../lib-network/config/net_config.h" -using namespace http; - -static constexpr char s_contentType[static_cast(contentTypes::NOT_DEFINED)][32] = - { "text/html", "text/css", "text/javascript", "application/json" }; - -HttpDaemon::HttpDaemon() : m_pContentType(s_contentType[static_cast(contentTypes::TEXT_HTML)]) { +HttpDaemon::HttpDaemon() { DEBUG_ENTRY assert(m_nHandle == -1); m_nHandle = Network::Get()->TcpBegin(80); assert(m_nHandle != -1); - assert(MDNS::Get() != nullptr); - MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::HTTP); - - DEBUG_EXIT -} - -void HttpDaemon::HandleRequest(const uint32_t nConnectionHandle) { - const char *pStatusMsg = "OK"; - - DEBUG_PRINTF("%u: m_Status=%u, m_RequestMethod=%u", nConnectionHandle, static_cast(m_Status), static_cast(m_RequestMethod)); - - if (m_Status == Status::UNKNOWN_ERROR) { - m_Status = ParseRequest(); - if (m_Status == Status::OK) { - if (m_RequestMethod == RequestMethod::GET) { - m_Status = HandleGet(); - } else if (m_RequestMethod == RequestMethod::POST) { - m_Status = HandlePost(false); - if ((m_Status == Status::OK) && (m_nFileDataLength == 0)) { - DEBUG_PUTS("There is a POST header only -> no data"); - return; - } - } - } - } else if ((m_Status == Status::OK) && (m_RequestMethod == RequestMethod::POST)) { - m_Status = HandlePost(true); + for (uint32_t nIndex = 0; nIndex < TCP_MAX_TCBS_ALLOWED; nIndex++) { + pHandleRequest[nIndex] = new HttpDeamonHandleRequest(nIndex, m_nHandle); + assert(pHandleRequest[nIndex] != nullptr); } - if (m_Status != Status::OK) { - switch (m_Status) { - case Status::BAD_REQUEST: - pStatusMsg = "Bad Request"; - break; - case Status::NOT_FOUND: - pStatusMsg = "Not Found"; - break; - case Status::REQUEST_ENTITY_TOO_LARGE: - pStatusMsg = "Request Entity Too Large"; - break; - case Status::REQUEST_URI_TOO_LONG: - pStatusMsg = "Request-URI Too Long"; - break; - case Status::INTERNAL_SERVER_ERROR: - pStatusMsg = "Internal Server Error"; - break; - case Status::METHOD_NOT_IMPLEMENTED: - pStatusMsg = "Method Not Implemented"; - break; - case Status::VERSION_NOT_SUPPORTED: - pStatusMsg = "Version Not Supported"; - break; - default: - pStatusMsg = "Unknown Error"; - break; - } - - m_pContentType = s_contentType[static_cast(contentTypes::TEXT_HTML)]; - m_nContentLength = static_cast(snprintf(m_Content, BUFSIZE - 1U, - "\n" - "\n" - "%u %s\n" - "

%s

\n" - "\n", static_cast(m_Status), pStatusMsg, pStatusMsg)); - } - - uint8_t nLength; - const int nHeaderLength = snprintf(m_RequestHeaderResponse, BUFSIZE - 1U, - "HTTP/1.1 %u %s\r\n" - "Server: %s\r\n" - "Content-Type: %s\r\n" - "Content-Length: %u\r\n" - "Connection: close\r\n" - "\r\n", static_cast(m_Status), pStatusMsg, Hardware::Get()->GetBoardName(nLength), m_pContentType, m_nContentLength); - - Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_RequestHeaderResponse), static_cast(nHeaderLength), nConnectionHandle); - Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_Content), static_cast(m_nContentLength), nConnectionHandle); - DEBUG_PRINTF("m_nContentLength=%u", m_nContentLength); - - m_Status = Status::UNKNOWN_ERROR; - m_RequestMethod = RequestMethod::UNKNOWN; -} - -Status HttpDaemon::ParseRequest() { - char *pLine = m_RequestHeaderResponse; - uint32_t nLine = 0; - Status status = Status::UNKNOWN_ERROR; - m_bContentTypeJson = false; - m_nRequestContentLength = 0; - m_nFileDataLength = 0; - - for (uint32_t i = 0; i < m_nBytesReceived; i++) { - if (m_RequestHeaderResponse[i] == '\n') { - assert(i > 1); - m_RequestHeaderResponse[i - 1] = '\0'; - - if (nLine++ == 0) { - status = ParseMethod(pLine); - } else { - if (pLine[0] == '\0') { - assert((i + 1) <= m_nBytesReceived); - m_nFileDataLength = static_cast(m_nBytesReceived - 1 - i); - if (m_nFileDataLength > 0) { - m_pFileData = &m_RequestHeaderResponse[i + 1]; - m_pFileData[m_nFileDataLength] = '\0'; - } - return Status::OK; - } - status = ParseHeaderField(pLine); - } - - if (status != Status::OK) { - return status; - } - - pLine = &m_RequestHeaderResponse[++i]; - } - } - - return Status::OK; -} - -/** - * Supported: "METHOD uri HTTP/1.1" - * Where METHOD is "GET" or "POST" - */ - -Status HttpDaemon::ParseMethod(char *pLine) { - assert(pLine != nullptr); - char *pToken; - - if ((pToken = strtok(pLine, " ")) == nullptr) { - return Status::METHOD_NOT_IMPLEMENTED; - } - - if (strcmp(pToken, "GET") == 0) { - m_RequestMethod = RequestMethod::GET; - } else if (strcmp(pToken, "POST") == 0) { - m_RequestMethod = RequestMethod::POST; - } else { - return Status::METHOD_NOT_IMPLEMENTED; - } - - if ((pToken = strtok(nullptr, " ")) == nullptr) { - return Status::BAD_REQUEST; - } - - m_pUri = pToken; - - if ((pToken = strtok(nullptr, "/")) == nullptr || strcmp(pToken, "HTTP") != 0) { - return Status::BAD_REQUEST; - } - - if ((pToken = strtok(nullptr, " \n")) == nullptr) { - return Status::BAD_REQUEST; - } - - if (strcmp(pToken, "1.1") != 0) { - return Status::VERSION_NOT_SUPPORTED; - } - - return Status::OK; -} - -/** - * Only interested in "Content-Type" and - * "Content-Length" - * Where we check for "Content-Type: application/json" - */ - -Status HttpDaemon::ParseHeaderField(char *pLine) { - char *pToken; - - assert(pLine != 0); - if ((pToken = strtok(pLine, ":")) == nullptr) { - return Status::BAD_REQUEST; - } - - if (strcasecmp(pToken, "Content-Type") == 0) { - if ((pToken = strtok(nullptr, " ;")) == nullptr) { - return Status::BAD_REQUEST; - } - if (strcmp(pToken, "application/json") == 0) { - m_bContentTypeJson = true; - } - } else if (strcasecmp(pToken, "Content-Length") == 0) { - if ((pToken = strtok(nullptr, " ")) == nullptr) { - return Status::BAD_REQUEST; - } - - uint32_t nTmp = 0; - while (*pToken != '\0') { - auto nDigit = static_cast(*pToken++ - '0'); - if (nDigit > 9) { - return Status::BAD_REQUEST; - } - - nTmp *= 10; - nTmp += nDigit; - - if (nTmp > BUFSIZE) { - return Status::REQUEST_ENTITY_TOO_LARGE; - } - } - - m_nRequestContentLength = nTmp; - } + assert(MDNS::Get() != nullptr); + MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::HTTP); DEBUG_EXIT - return Status::OK; } -/** - * GET - */ - -Status HttpDaemon::HandleGet() { +HttpDaemon::~HttpDaemon() { DEBUG_ENTRY - uint32_t nLength = 0; + MDNS::Get()->ServiceRecordDelete(mdns::Services::HTTP); - if (memcmp(m_pUri, "/json/", 6) == 0) { - m_pContentType = s_contentType[static_cast(contentTypes::APPLICATION_JSON)]; - const auto *pGet = &m_pUri[6]; - switch (http::get_uint(pGet)) { - case http::json::get::LIST: - nLength = remoteconfig::json_get_list(m_Content, sizeof(m_Content)); - break; - case http::json::get::VERSION: - nLength = remoteconfig::json_get_version(m_Content, sizeof(m_Content)); - break; - case http::json::get::UPTIME: - if (!RemoteConfig::Get()->IsEnableUptime()) { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - nLength = remoteconfig::json_get_uptime(m_Content, sizeof(m_Content)); - break; - case http::json::get::DISPLAY: - nLength = remoteconfig::json_get_display(m_Content, sizeof(m_Content)); - break; - case http::json::get::DIRECTORY: - nLength = remoteconfig::json_get_directory(m_Content, sizeof(m_Content)); - break; -#if defined (RDM_CONTROLLER) - case http::json::get::RDM: - nLength = remoteconfig::rdm::json_get_rdm(m_Content, sizeof(m_Content)); - break; -#endif -#if defined (ENABLE_NET_PHYSTATUS) - case http::json::get::PHYSTATUS: - nLength = remoteconfig::net::json_get_phystatus(m_Content, sizeof(m_Content)); - break; -#endif - default: -#if defined (RDM_CONTROLLER) - if (memcmp(pGet, "rdm/", 4) == 0) { - const auto *pRdm = &pGet[4]; - const bool isQuestionMark = (pRdm[3] == '?'); // Handle /rdm/tod?X - if (isQuestionMark) { - auto *p = const_cast(pRdm); - p[3] = '\0'; - } - switch (http::get_uint(pRdm)) { - case http::json::get::QUEUE: - nLength = remoteconfig::rdm::json_get_queue(m_Content, sizeof(m_Content)); - break; - case http::json::get::PORTSTATUS: - nLength = remoteconfig::rdm::json_get_portstatus(m_Content, sizeof(m_Content)); - break; - case http::json::get::TOD: { - const auto *pTod = &pRdm[4]; - if (isQuestionMark && isalpha(static_cast(pTod[0]))) { - nLength = remoteconfig::rdm::json_get_tod(pTod[0], m_Content, sizeof(m_Content)); - } - } - break; - default: - break; - } - } else -#endif -#if !defined(DISABLE_FS) || defined (CONFIG_USB_HOST_MSC) - if (memcmp(pGet, "storage/", 8) == 0) { - const auto *pStorage = &pGet[8]; - switch (http::get_uint(pStorage)) { - case http::json::get::DIRECTORY: - nLength = remoteconfig::storage::json_get_directory(m_Content, sizeof(m_Content)); - break; - default: - break; - } - } else -#endif -#if defined (ENABLE_PHY_SWITCH) - if (memcmp(pGet, "dsa/", 4) == 0) { - const auto *pDsa = &pGet[4]; - switch (http::get_uint(pDsa)) { - case http::json::get::PORTSTATUS: - nLength = remoteconfig::dsa::json_get_portstatus(m_Content, sizeof(m_Content)); - break; - case http::json::get::VLANTABLE: - nLength = remoteconfig::dsa::json_get_vlantable(m_Content, sizeof(m_Content)); - break; - default: - break; - } - } else -#endif - { - return HandleGetTxt(); - - } - break; + for (uint32_t nIndex = 0; nIndex < TCP_MAX_TCBS_ALLOWED; nIndex++) { + if (pHandleRequest[nIndex] != nullptr) { + delete pHandleRequest[nIndex]; } } -#if defined (ENABLE_CONTENT) - else if (strcmp(m_pUri, "/") == 0) { - http::contentTypes contentType; - nLength = get_file_content("index.html", m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#if defined (RDM_CONTROLLER) - else if (strcmp(m_pUri, "/rdm") == 0) { - http::contentTypes contentType; - nLength = get_file_content("rdm.html", m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#endif -#if defined (ENABLE_PHY_SWITCH) - else if (strcmp(m_pUri, "/dsa") == 0) { - http::contentTypes contentType; - nLength = get_file_content("dsa.html", m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#endif - else { - http::contentTypes contentType; - nLength = get_file_content(&m_pUri[1], m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#endif - if (nLength == 0) { - DEBUG_EXIT - return Status::NOT_FOUND; - } - - m_nContentLength = nLength; + Network::Get()->TcpEnd(m_nHandle); DEBUG_EXIT - return Status::OK; -} - -Status HttpDaemon::HandleGetTxt() { - auto *pFileName = &m_pUri[6]; - const auto nLength = strlen(pFileName); - - if (nLength <= 4) { - return Status::BAD_REQUEST; - } - - if (strcmp(&pFileName[nLength - 4], ".txt") != 0) { - return Status::BAD_REQUEST; - } - - const auto bIsJSON = PropertiesConfig::IsJSON(); - - PropertiesConfig::EnableJSON(true); - const auto nBytes = RemoteConfig::Get()->HandleGet(reinterpret_cast(pFileName), BUFSIZE - 5U); - - PropertiesConfig::EnableJSON(bIsJSON); - - DEBUG_PRINTF("nBytes=%d", nBytes); - - if (nBytes <= 0) { - return Status::BAD_REQUEST; - } - - m_nContentLength = static_cast(nBytes); - memcpy(m_Content, reinterpret_cast(pFileName), nBytes); - - return Status::OK; -} - -/** - * POST - */ - -Status HttpDaemon::HandlePost(bool hasDataOnly) { - DEBUG_PRINTF("m_nBytesReceived=%d, m_nFileDataLength=%u, m_nRequestContentLength=%u -> hasDataOnly=%c", m_nBytesReceived, m_nFileDataLength, m_nRequestContentLength, hasDataOnly ? 'Y' : 'N'); - - if (!hasDataOnly) { - if (!m_bContentTypeJson) { - return Status::BAD_REQUEST; - } - - m_IsAction = (strcmp(m_pUri, "/json/action") == 0); - - if (!m_IsAction && (strcmp(m_pUri, "/json") != 0)) { - return Status::NOT_FOUND; - } - } - - const auto hasHeadersOnly = (!hasDataOnly && ((m_nBytesReceived < m_nRequestContentLength) || m_nFileDataLength == 0)); - - if (hasHeadersOnly) { - DEBUG_PUTS("hasHeadersOnly"); - return Status::OK; - } - - - if (hasDataOnly) { - m_pFileData = m_RequestHeaderResponse; - m_nFileDataLength = static_cast(m_nBytesReceived); - } - - DEBUG_PRINTF("%d|%.*s|->%d", m_nFileDataLength, m_nFileDataLength, m_pFileData, m_IsAction); - - if (m_IsAction) { - if (properties::convert_json_file(m_pFileData, m_nFileDataLength, true) <= 0) { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - - uint8_t value8; - - if (Sscan::Uint8(m_pFileData, "reboot", value8) == Sscan::OK) { - if (value8 != 0) { - if (!RemoteConfig::Get()->IsEnableReboot()) { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - DEBUG_PUTS("Reboot!"); - RemoteConfig::Get()->Reboot(); - __builtin_unreachable(); - } - } else if (Sscan::Uint8(m_pFileData, "display", value8) == Sscan::OK) { - Display::Get()->SetSleep(value8 == 0); - DEBUG_PRINTF("Display::Get()->SetSleep(%d)", value8 == 0); - } else if (Sscan::Uint8(m_pFileData, "identify", value8) == Sscan::OK) { - if (value8 != 0) { - Hardware::Get()->SetMode(hardware::ledblink::Mode::FAST); - } else { - Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); - } - DEBUG_PRINTF("identify=%d", value8 != 0); - } -#if defined (RDM_CONTROLLER) - else if (Sscan::Uint8(m_pFileData, "rdm", value8) == Sscan::OK) { - ArtNetNode::Get()->SetRdm(!(value8 != 1)); - DEBUG_PRINTF("rdm=%d", ArtNetNode::Get()->GetRdm()); - } -#endif - else { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - } else { - const auto bIsJSON = PropertiesConfig::IsJSON(); - - PropertiesConfig::EnableJSON(true); - RemoteConfig::Get()->HandleSet(m_pFileData, m_nFileDataLength); - - PropertiesConfig::EnableJSON(bIsJSON); - } - - m_pContentType = s_contentType[static_cast(contentTypes::TEXT_HTML)]; - m_nContentLength = static_cast(snprintf(m_Content, BUFSIZE - 1U, - "\n" - "\n" - "Submit\n" - "

OK

\n" - "\n")); - - return Status::OK; } diff --git a/lib-remoteconfig/src/httpd/httpdhandlerequest.cpp b/lib-remoteconfig/src/httpd/httpdhandlerequest.cpp new file mode 100755 index 0000000..c635408 --- /dev/null +++ b/lib-remoteconfig/src/httpd/httpdhandlerequest.cpp @@ -0,0 +1,536 @@ +/** + * @file httpdhandlerequest.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "httpd/httpdhandlerequest.h" + +#include "../http/content/json_switch.h" + +#include "remoteconfig.h" +#include "remoteconfigjson.h" +#include "properties.h" +#include "sscan.h" +#include "propertiesconfig.h" + +#include "hardware.h" +#include "network.h" +#include "mdns.h" +#include "display.h" + +#if defined(RDM_CONTROLLER) +# include "artnetnode.h" +#endif + +#include "debug.h" + +#if defined ENABLE_CONTENT +extern uint32_t get_file_content(const char *fileName, char *pDst, http::contentTypes& contentType); +#endif + +char HttpDeamonHandleRequest::m_Content[http::BUFSIZE]; + +static constexpr char s_contentType[static_cast(http::contentTypes::NOT_DEFINED)][32] = + { "text/html", "text/css", "text/javascript", "application/json" }; + +void HttpDeamonHandleRequest::HandleRequest(const uint32_t nBytesReceived, char *pRequestHeaderResponse) { +// m_pContentType = s_contentType[static_cast(http::contentTypes::TEXT_HTML)]; + m_nBytesReceived = nBytesReceived; + m_RequestHeaderResponse = pRequestHeaderResponse; + + const char *pStatusMsg = "OK"; + + DEBUG_PRINTF("%u: m_Status=%u, m_RequestMethod=%u", m_nConnectionHandle, static_cast(m_Status), static_cast(m_RequestMethod)); + + if (m_Status == http::Status::UNKNOWN_ERROR) { + m_Status = ParseRequest(); + if (m_Status == http::Status::OK) { + if (m_RequestMethod == http::RequestMethod::GET) { + m_Status = HandleGet(); + } else if (m_RequestMethod == http::RequestMethod::POST) { + m_Status = HandlePost(false); + if ((m_Status == http::Status::OK) && (m_nFileDataLength == 0)) { + DEBUG_PUTS("There is a POST header only -> no data"); + return; + } + } + } + } else if ((m_Status == http::Status::OK) && (m_RequestMethod == http::RequestMethod::POST)) { + m_Status = HandlePost(true); + } + + if (m_Status != http::Status::OK) { + switch (m_Status) { + case http::Status::BAD_REQUEST: + pStatusMsg = "Bad Request"; + break; + case http::Status::NOT_FOUND: + pStatusMsg = "Not Found"; + break; + case http::Status::REQUEST_ENTITY_TOO_LARGE: + pStatusMsg = "Request Entity Too Large"; + break; + case http::Status::REQUEST_URI_TOO_LONG: + pStatusMsg = "Request-URI Too Long"; + break; + case http::Status::INTERNAL_SERVER_ERROR: + pStatusMsg = "Internal Server Error"; + break; + case http::Status::METHOD_NOT_IMPLEMENTED: + pStatusMsg = "Method Not Implemented"; + break; + case http::Status::VERSION_NOT_SUPPORTED: + pStatusMsg = "Version Not Supported"; + break; + default: + pStatusMsg = "Unknown Error"; + break; + } + + m_pContentType = s_contentType[static_cast(http::contentTypes::TEXT_HTML)]; + m_nContentLength = static_cast(snprintf(m_Content, http::BUFSIZE - 1U, + "\n" + "\n" + "%u %s\n" + "

%s

\n" + "\n", static_cast(m_Status), pStatusMsg, pStatusMsg)); + } + + uint8_t nLength; + const int nHeaderLength = snprintf(m_RequestHeaderResponse, http::BUFSIZE - 1U, + "HTTP/1.1 %u %s\r\n" + "Server: %s\r\n" + "Content-Type: %s\r\n" + "Content-Length: %u\r\n" + "Connection: close\r\n" + "\r\n", static_cast(m_Status), pStatusMsg, Hardware::Get()->GetBoardName(nLength), m_pContentType, m_nContentLength); + + Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_RequestHeaderResponse), static_cast(nHeaderLength), m_nConnectionHandle); + Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_Content), static_cast(m_nContentLength), m_nConnectionHandle); + DEBUG_PRINTF("m_nContentLength=%u", m_nContentLength); + + m_Status = http::Status::UNKNOWN_ERROR; + m_RequestMethod = http::RequestMethod::UNKNOWN; +} + +http::Status HttpDeamonHandleRequest::ParseRequest() { + char *pLine = m_RequestHeaderResponse; + uint32_t nLine = 0; + http::Status status = http::Status::UNKNOWN_ERROR; + m_bContentTypeJson = false; + m_nRequestContentLength = 0; + m_nFileDataLength = 0; + + for (uint32_t i = 0; i < m_nBytesReceived; i++) { + if (m_RequestHeaderResponse[i] == '\n') { + assert(i > 1); + m_RequestHeaderResponse[i - 1] = '\0'; + + if (nLine++ == 0) { + status = ParseMethod(pLine); + } else { + if (pLine[0] == '\0') { + assert((i + 1) <= m_nBytesReceived); + m_nFileDataLength = static_cast(m_nBytesReceived - 1 - i); + if (m_nFileDataLength > 0) { + m_pFileData = &m_RequestHeaderResponse[i + 1]; + m_pFileData[m_nFileDataLength] = '\0'; + } + return http::Status::OK; + } + status = ParseHeaderField(pLine); + } + + if (status != http::Status::OK) { + return status; + } + + pLine = &m_RequestHeaderResponse[++i]; + } + } + + return http::Status::OK; +} + +/** + * Supported: "METHOD uri HTTP/1.1" + * Where METHOD is "GET" or "POST" + */ + +http::Status HttpDeamonHandleRequest::ParseMethod(char *pLine) { + assert(pLine != nullptr); + char *pToken; + + if ((pToken = strtok(pLine, " ")) == nullptr) { + return http::Status::METHOD_NOT_IMPLEMENTED; + } + + if (strcmp(pToken, "GET") == 0) { + m_RequestMethod = http::RequestMethod::GET; + } else if (strcmp(pToken, "POST") == 0) { + m_RequestMethod = http::RequestMethod::POST; + } else { + return http::Status::METHOD_NOT_IMPLEMENTED; + } + + if ((pToken = strtok(nullptr, " ")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + m_pUri = pToken; + + if ((pToken = strtok(nullptr, "/")) == nullptr || strcmp(pToken, "HTTP") != 0) { + return http::Status::BAD_REQUEST; + } + + if ((pToken = strtok(nullptr, " \n")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + if (strcmp(pToken, "1.1") != 0) { + return http::Status::VERSION_NOT_SUPPORTED; + } + + return http::Status::OK; +} + +/** + * Only interested in "Content-Type" and + * "Content-Length" + * Where we check for "Content-Type: application/json" + */ + +http::Status HttpDeamonHandleRequest::ParseHeaderField(char *pLine) { + DEBUG_ENTRY + char *pToken; + + assert(pLine != 0); + if ((pToken = strtok(pLine, ":")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + if (strcasecmp(pToken, "Content-Type") == 0) { + if ((pToken = strtok(nullptr, " ;")) == nullptr) { + return http::Status::BAD_REQUEST; + } + if (strcmp(pToken, "application/json") == 0) { + m_bContentTypeJson = true; + } + } else if (strcasecmp(pToken, "Content-Length") == 0) { + if ((pToken = strtok(nullptr, " ")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + uint32_t nTmp = 0; + while (*pToken != '\0') { + auto nDigit = static_cast(*pToken++ - '0'); + if (nDigit > 9) { + return http::Status::BAD_REQUEST; + } + + nTmp *= 10; + nTmp += nDigit; + + if (nTmp > http::BUFSIZE) { + return http::Status::REQUEST_ENTITY_TOO_LARGE; + } + } + + m_nRequestContentLength = nTmp; + } + + DEBUG_EXIT + return http::Status::OK; +} + +/** + * GET + */ + +http::Status HttpDeamonHandleRequest::HandleGet() { + DEBUG_ENTRY + + uint32_t nLength = 0; + + if (memcmp(m_pUri, "/json/", 6) == 0) { + m_pContentType = s_contentType[static_cast(http::contentTypes::APPLICATION_JSON)]; + const auto *pGet = &m_pUri[6]; + switch (http::get_uint(pGet)) { + case http::json::get::LIST: + nLength = remoteconfig::json_get_list(m_Content, sizeof(m_Content)); + break; + case http::json::get::VERSION: + nLength = remoteconfig::json_get_version(m_Content, sizeof(m_Content)); + break; + case http::json::get::UPTIME: + if (!RemoteConfig::Get()->IsEnableUptime()) { + DEBUG_PUTS("Status::BAD_REQUEST"); + return http::Status::BAD_REQUEST; + } + nLength = remoteconfig::json_get_uptime(m_Content, sizeof(m_Content)); + break; + case http::json::get::DISPLAY: + nLength = remoteconfig::json_get_display(m_Content, sizeof(m_Content)); + break; + case http::json::get::DIRECTORY: + nLength = remoteconfig::json_get_directory(m_Content, sizeof(m_Content)); + break; +#if defined (RDM_CONTROLLER) + case http::json::get::RDM: + nLength = remoteconfig::rdm::json_get_rdm(m_Content, sizeof(m_Content)); + break; +#endif +#if defined (ENABLE_NET_PHYSTATUS) + case http::json::get::PHYSTATUS: + nLength = remoteconfig::net::json_get_phystatus(m_Content, sizeof(m_Content)); + break; +#endif + default: +#if defined (RDM_CONTROLLER) + if (memcmp(pGet, "rdm/", 4) == 0) { + const auto *pRdm = &pGet[4]; + const bool isQuestionMark = (pRdm[3] == '?'); // Handle /rdm/tod?X + if (isQuestionMark) { + auto *p = const_cast(pRdm); + p[3] = '\0'; + } + switch (http::get_uint(pRdm)) { + case http::json::get::QUEUE: + nLength = remoteconfig::rdm::json_get_queue(m_Content, sizeof(m_Content)); + break; + case http::json::get::PORTSTATUS: + nLength = remoteconfig::rdm::json_get_portstatus(m_Content, sizeof(m_Content)); + break; + case http::json::get::TOD: { + const auto *pTod = &pRdm[4]; + if (isQuestionMark && isalpha(static_cast(pTod[0]))) { + nLength = remoteconfig::rdm::json_get_tod(pTod[0], m_Content, sizeof(m_Content)); + } + } + break; + default: + break; + } + } else +#endif +#if !defined(DISABLE_FS) || defined (CONFIG_USB_HOST_MSC) + if (memcmp(pGet, "storage/", 8) == 0) { + const auto *pStorage = &pGet[8]; + switch (http::get_uint(pStorage)) { + case http::json::get::DIRECTORY: + nLength = remoteconfig::storage::json_get_directory(m_Content, sizeof(m_Content)); + break; + default: + break; + } + } else +#endif +#if defined (ENABLE_PHY_SWITCH) + if (memcmp(pGet, "dsa/", 4) == 0) { + const auto *pDsa = &pGet[4]; + switch (http::get_uint(pDsa)) { + case http::json::get::PORTSTATUS: + nLength = remoteconfig::dsa::json_get_portstatus(m_Content, sizeof(m_Content)); + break; + case http::json::get::VLANTABLE: + nLength = remoteconfig::dsa::json_get_vlantable(m_Content, sizeof(m_Content)); + break; + default: + break; + } + } else +#endif + { + return HandleGetTxt(); + + } + break; + } + } +#if defined (ENABLE_CONTENT) + else if (strcmp(m_pUri, "/") == 0) { + http::contentTypes contentType; + nLength = get_file_content("index.html", m_Content, contentType); + m_pContentType = s_contentType[static_cast(contentType)]; + } +#if defined (RDM_CONTROLLER) + else if (strcmp(m_pUri, "/rdm") == 0) { + http::contentTypes contentType; + nLength = get_file_content("rdm.html", m_Content, contentType); + m_pContentType = s_contentType[static_cast(contentType)]; + } +#endif +#if defined (ENABLE_PHY_SWITCH) + else if (strcmp(m_pUri, "/dsa") == 0) { + http::contentTypes contentType; + nLength = get_file_content("dsa.html", m_Content, contentType); + m_pContentType = s_contentType[static_cast(contentType)]; + } +#endif + else { + http::contentTypes contentType; + nLength = get_file_content(&m_pUri[1], m_Content, contentType); + m_pContentType = s_contentType[static_cast(contentType)]; + } +#endif + + if (nLength == 0) { + DEBUG_EXIT + return http::Status::NOT_FOUND; + } + + m_nContentLength = nLength; + + DEBUG_EXIT + return http::Status::OK; +} + +http::Status HttpDeamonHandleRequest::HandleGetTxt() { + auto *pFileName = &m_pUri[6]; + const auto nLength = strlen(pFileName); + + if (nLength <= 4) { + return http::Status::BAD_REQUEST; + } + + if (strcmp(&pFileName[nLength - 4], ".txt") != 0) { + return http::Status::BAD_REQUEST; + } + + const auto bIsJSON = PropertiesConfig::IsJSON(); + + PropertiesConfig::EnableJSON(true); + const auto nBytes = RemoteConfig::Get()->HandleGet(reinterpret_cast(pFileName), http::BUFSIZE - 5U); + + PropertiesConfig::EnableJSON(bIsJSON); + + DEBUG_PRINTF("nBytes=%d", nBytes); + + if (nBytes <= 0) { + return http::Status::BAD_REQUEST; + } + + m_nContentLength = static_cast(nBytes); + memcpy(m_Content, reinterpret_cast(pFileName), nBytes); + + return http::Status::OK; +} + +/** + * POST + */ + +http::Status HttpDeamonHandleRequest::HandlePost(bool hasDataOnly) { + DEBUG_PRINTF("m_nBytesReceived=%d, m_nFileDataLength=%u, m_nRequestContentLength=%u -> hasDataOnly=%c", m_nBytesReceived, m_nFileDataLength, m_nRequestContentLength, hasDataOnly ? 'Y' : 'N'); + + if (!hasDataOnly) { + if (!m_bContentTypeJson) { + return http::Status::BAD_REQUEST; + } + + m_IsAction = (strcmp(m_pUri, "/json/action") == 0); + + if (!m_IsAction && (strcmp(m_pUri, "/json") != 0)) { + return http::Status::NOT_FOUND; + } + } + + const auto hasHeadersOnly = (!hasDataOnly && ((m_nBytesReceived < m_nRequestContentLength) || m_nFileDataLength == 0)); + + if (hasHeadersOnly) { + DEBUG_PUTS("hasHeadersOnly"); + return http::Status::OK; + } + + + if (hasDataOnly) { + m_pFileData = m_RequestHeaderResponse; + m_nFileDataLength = static_cast(m_nBytesReceived); + } + + DEBUG_PRINTF("%d|%.*s|->%d", m_nFileDataLength, m_nFileDataLength, m_pFileData, m_IsAction); + + if (m_IsAction) { + if (properties::convert_json_file(m_pFileData, m_nFileDataLength, true) <= 0) { + DEBUG_PUTS("Status::BAD_REQUEST"); + return http::Status::BAD_REQUEST; + } + + uint8_t value8; + + if (Sscan::Uint8(m_pFileData, "reboot", value8) == Sscan::OK) { + if (value8 != 0) { + if (!RemoteConfig::Get()->IsEnableReboot()) { + DEBUG_PUTS("Status::BAD_REQUEST"); + return http::Status::BAD_REQUEST; + } + DEBUG_PUTS("Reboot!"); + RemoteConfig::Get()->Reboot(); + __builtin_unreachable(); + } + } else if (Sscan::Uint8(m_pFileData, "display", value8) == Sscan::OK) { + Display::Get()->SetSleep(value8 == 0); + DEBUG_PRINTF("Display::Get()->SetSleep(%d)", value8 == 0); + } else if (Sscan::Uint8(m_pFileData, "identify", value8) == Sscan::OK) { + if (value8 != 0) { + Hardware::Get()->SetMode(hardware::ledblink::Mode::FAST); + } else { + Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); + } + DEBUG_PRINTF("identify=%d", value8 != 0); + } +#if defined (RDM_CONTROLLER) + else if (Sscan::Uint8(m_pFileData, "rdm", value8) == Sscan::OK) { + ArtNetNode::Get()->SetRdm(!(value8 != 1)); + DEBUG_PRINTF("rdm=%d", ArtNetNode::Get()->GetRdm()); + } +#endif + else { + DEBUG_PUTS("Status::BAD_REQUEST"); + return http::Status::BAD_REQUEST; + } + } else { + const auto bIsJSON = PropertiesConfig::IsJSON(); + + PropertiesConfig::EnableJSON(true); + RemoteConfig::Get()->HandleSet(m_pFileData, m_nFileDataLength); + + PropertiesConfig::EnableJSON(bIsJSON); + } + + m_pContentType = s_contentType[static_cast(http::contentTypes::TEXT_HTML)]; + m_nContentLength = static_cast(snprintf(m_Content, http::BUFSIZE - 1U, + "\n" + "\n" + "Submit\n" + "

OK

\n" + "\n")); + + return http::Status::OK; +} diff --git a/lib-remoteconfig/src/remoteconfig.cpp b/lib-remoteconfig/src/remoteconfig.cpp index 87a37a7..9244aff 100644 --- a/lib-remoteconfig/src/remoteconfig.cpp +++ b/lib-remoteconfig/src/remoteconfig.cpp @@ -2,7 +2,7 @@ * @file remoteconfig.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -137,12 +137,10 @@ #if defined(OUTPUT_DMX_STEPPER) /* sparkfun.txt */ # include "sparkfundmxparams.h" -# include "storesparkfundmx.h" /* motor%.txt */ # include "modeparams.h" # include "motorparams.h" # include "l6470params.h" -# include "storemotors.h" #endif #if defined (OUTPUT_DMX_SERIAL) @@ -244,7 +242,7 @@ RemoteConfig *RemoteConfig::s_pThis; RemoteConfig::ListBin RemoteConfig::s_RemoteConfigListBin; char *RemoteConfig::s_pUdpBuffer; -RemoteConfig::RemoteConfig(remoteconfig::Node node, remoteconfig::Output output, uint32_t nActiveOutputs): +RemoteConfig::RemoteConfig(const remoteconfig::Node node, const remoteconfig::Output output, const uint32_t nActiveOutputs): m_tNode(node), m_tOutput(output), m_nActiveOutputs(nActiveOutputs) @@ -273,6 +271,11 @@ RemoteConfig::RemoteConfig(remoteconfig::Node node, remoteconfig::Output output, # if defined(ENABLE_TFTP_SERVER) MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::TFTP); # endif + +# if defined (ENABLE_HTTPD) + m_pHttpDaemon = new HttpDaemon; + assert(m_pHttpDaemon != nullptr); +# endif #endif DEBUG_EXIT @@ -282,6 +285,12 @@ RemoteConfig::~RemoteConfig() { DEBUG_ENTRY #if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# if defined (ENABLE_HTTPD) + if (m_pHttpDaemon != nullptr) { + delete m_pHttpDaemon; + } +# endif + MDNS::Get()->ServiceRecordDelete(mdns::Services::CONFIG); #endif @@ -477,12 +486,12 @@ void RemoteConfig::HandleDisplaySet() { const auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::DISPLAY)].nLength; - if (m_nBytesReceived != (nCmdLength + 1)) { + if (m_nBytesReceived != (nCmdLength + 1U)) { DEBUG_EXIT return; } - Display::Get()->SetSleep(s_pUdpBuffer[nCmdLength + 1] == '0'); + Display::Get()->SetSleep(s_pUdpBuffer[nCmdLength + 1U] == '0'); DEBUG_PRINTF("%c", s_pUdpBuffer[nCmdLength + 1]); DEBUG_EXIT @@ -509,14 +518,14 @@ void RemoteConfig::HandleRdmSet() { const auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::RDM)].nLength; - if (m_nBytesReceived != (nCmdLength + 1)) { + if (m_nBytesReceived != (nCmdLength + 1U)) { DEBUG_EXIT return; } - ArtNetNode::Get()->SetRdm(s_pUdpBuffer[nCmdLength + 1] != '0'); + ArtNetNode::Get()->SetRdm(s_pUdpBuffer[nCmdLength + 1U] != '0'); - DEBUG_PRINTF("%c", s_pUdpBuffer[nCmdLength + 1]); + DEBUG_PRINTF("%c", s_pUdpBuffer[nCmdLength + 1U]); DEBUG_EXIT } @@ -788,7 +797,7 @@ void RemoteConfig::HandleGetDisplayTxt(uint32_t& nSize) { void RemoteConfig::HandleGetSparkFunTxt(uint32_t& nSize) { DEBUG_ENTRY - SparkFunDmxParams sparkFunParams(StoreSparkFunDmx::Get()); + SparkFunDmxParams sparkFunParams; sparkFunParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -800,28 +809,28 @@ void RemoteConfig::HandleGetMotorTxt(uint32_t nMotorIndex, uint32_t& nSize) { uint32_t nSizeSparkFun = 0; - SparkFunDmxParams sparkFunParams(StoreSparkFunDmx::Get()); + SparkFunDmxParams sparkFunParams; sparkFunParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSizeSparkFun, nMotorIndex); DEBUG_PRINTF("nSizeSparkFun=%d", nSizeSparkFun); uint32_t nSizeMode = 0; - ModeParams modeParams(StoreMotors::Get()); + ModeParams modeParams; modeParams.Save(nMotorIndex, s_pUdpBuffer + nSizeSparkFun, remoteconfig::udp::BUFFER_SIZE - nSizeSparkFun, nSizeMode); DEBUG_PRINTF("nSizeMode=%d", nSizeMode); uint32_t nSizeMotor = 0; - MotorParams motorParams(StoreMotors::Get()); + MotorParams motorParams; motorParams.Save(nMotorIndex, s_pUdpBuffer + nSizeSparkFun + nSizeMode, remoteconfig::udp::BUFFER_SIZE - nSizeSparkFun - nSizeMode, nSizeMotor); DEBUG_PRINTF("nSizeMotor=%d", nSizeMotor); uint32_t nSizeL6470 = 0; - L6470Params l6470Params(StoreMotors::Get()); + L6470Params l6470Params; l6470Params.Save(nMotorIndex, s_pUdpBuffer + nSizeSparkFun + nSizeMode + nSizeMotor, remoteconfig::udp::BUFFER_SIZE - nSizeSparkFun - nSizeMode - nSizeMotor, nSizeL6470); DEBUG_PRINTF("nSizeL6470=%d", nSizeL6470); @@ -1103,8 +1112,7 @@ void RemoteConfig::HandleSetDisplayTxt() { void RemoteConfig::HandleSetSparkFunTxt() { DEBUG_ENTRY - assert(StoreSparkFunDmx::Get() != nullptr); - SparkFunDmxParams sparkFunDmxParams(StoreSparkFunDmx::Get()); + SparkFunDmxParams sparkFunDmxParams; sparkFunDmxParams.Load(s_pUdpBuffer, m_nBytesReceived); DEBUG_EXIT @@ -1114,18 +1122,16 @@ void RemoteConfig::HandleSetMotorTxt(uint32_t nMotorIndex) { DEBUG_ENTRY DEBUG_PRINTF("nMotorIndex=%d", nMotorIndex); - assert(StoreSparkFunDmx::Get() != nullptr); - SparkFunDmxParams sparkFunDmxParams(StoreSparkFunDmx::Get()); + SparkFunDmxParams sparkFunDmxParams; sparkFunDmxParams.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); - assert(StoreMotors::Get() != nullptr); - ModeParams modeParams(StoreMotors::Get()); + ModeParams modeParams; modeParams.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); - MotorParams motorParams(StoreMotors::Get()); + MotorParams motorParams; motorParams.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); - L6470Params l6470Params(StoreMotors::Get()); + L6470Params l6470Params; l6470Params.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); DEBUG_EXIT @@ -1236,12 +1242,12 @@ void RemoteConfig::HandleTftpSet() { const auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::TFTP)].nLength; - if (m_nBytesReceived != (nCmdLength + 1)) { + if (m_nBytesReceived != (nCmdLength + 1U)) { DEBUG_EXIT return; } - m_bEnableTFTP = (s_pUdpBuffer[nCmdLength + 1] != '0'); + m_bEnableTFTP = (s_pUdpBuffer[nCmdLength + 1U] != '0'); if (m_bEnableTFTP) { Display::Get()->SetSleep(false); diff --git a/lib-ws28xx/Makefile.GD32 b/lib-ws28xx/Makefile.GD32 index 963e9f3..4482c8a 100644 --- a/lib-ws28xx/Makefile.GD32 +++ b/lib-ws28xx/Makefile.GD32 @@ -1,7 +1,7 @@ DEFINES=USE_SPI_DMA #DEFINES+=NDEBUG -EXTRA_INCLUDES=../lib-device/include ../lib-hal/include +EXTRA_INCLUDES= EXTRA_SRCDIR=src/patterns src/pixel src/gd32/gpio src/gd32/i2s