diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 97d412de184e0..6de2f774e951d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -94,6 +94,38 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \ imx8qm-mek-dsi-rm67191.dtb imx8qm-lpddr4-val-dp.dtb\ imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-var-dart-wifi-dp.dtb \ + imx8mq-var-dart-wifi-hdmi.dtb \ + imx8mq-var-dart-wifi-lvds.dtb \ + imx8mq-var-dart-wifi-lvds-dp.dtb \ + imx8mq-var-dart-wifi-lvds-hdmi.dtb \ + imx8mq-var-dart-wifi-hdmi-cb12.dtb \ + imx8mq-var-dart-wifi-lvds-cb12.dtb \ + imx8mq-var-dart-wifi-lvds-hdmi-cb12.dtb \ + imx8mq-var-dart-sd-dp.dtb \ + imx8mq-var-dart-sd-hdmi.dtb \ + imx8mq-var-dart-sd-lvds.dtb \ + imx8mq-var-dart-sd-lvds-dp.dtb \ + imx8mq-var-dart-sd-lvds-hdmi.dtb \ + imx8mq-var-dart-sd-hdmi-cb12.dtb \ + imx8mq-var-dart-sd-lvds-cb12.dtb \ + imx8mq-var-dart-sd-lvds-hdmi-cb12.dtb \ + imx8mq-var-dart-m4-wifi-dp.dtb \ + imx8mq-var-dart-m4-wifi-hdmi.dtb \ + imx8mq-var-dart-m4-wifi-lvds.dtb \ + imx8mq-var-dart-m4-wifi-lvds-dp.dtb \ + imx8mq-var-dart-m4-wifi-lvds-hdmi.dtb \ + imx8mq-var-dart-m4-wifi-hdmi-cb12.dtb \ + imx8mq-var-dart-m4-wifi-lvds-cb12.dtb \ + imx8mq-var-dart-m4-wifi-lvds-hdmi-cb12.dtb \ + imx8mq-var-dart-m4-sd-dp.dtb \ + imx8mq-var-dart-m4-sd-hdmi.dtb \ + imx8mq-var-dart-m4-sd-lvds.dtb \ + imx8mq-var-dart-m4-sd-lvds-dp.dtb \ + imx8mq-var-dart-m4-sd-lvds-hdmi.dtb \ + imx8mq-var-dart-m4-sd-hdmi-cb12.dtb \ + imx8mq-var-dart-m4-sd-lvds-cb12.dtb \ + imx8mq-var-dart-m4-sd-lvds-hdmi-cb12.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-cb12.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-cb12.dtsi new file mode 100644 index 0000000000000..007cb10dae667 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-cb12.dtsi @@ -0,0 +1,23 @@ +&iomuxc { + imx8m-var-dart { + csi2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x19 + >; + }; + }; +}; + +&ov5640_mipi2 { + rst-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 0>; + fsl,spi-num-chipselects = <1>; + + can0: can@1 { + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-common.dtsi new file mode 100644 index 0000000000000..5414d7d69f0b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-common.dtsi @@ -0,0 +1,1106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017-2018 Pengutronix, Lucas Stach + * Copyright 2018-2020 Variscite Ltd. + */ + +/dts-v1/; + +#include +#include "imx8mq.dtsi" + +/ { + compatible = "variscite,imx8m-dart", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_audio: audio_vdd { + compatible = "regulator-fixed"; + regulator-name = "wm8904_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + can0_osc: can0_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + sound-wm8904 { + compatible = "fsl,imx-audio-wm8904"; + model = "imx-wm8904"; + audio-cpu = <&sai3>; + audio-codec = <&wm8904>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Mic Jack", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + status = "okay"; + }; + + sound-hdmi { + compatible = "fsl,imx8mq-evk-cdnhdmi", + "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <1>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif2>; + spdif-in; + status = "disabled"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 1000000 0>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + up { + label = "Up"; + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + down { + label = "Down"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + emmc { + label = "eMMC"; + gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&A53_0 { + cpu-supply = <®_cpu_dvfs>; +}; + +&A53_1 { + cpu-supply = <®_cpu_dvfs>; +}; + +&A53_2 { + cpu-supply = <®_cpu_dvfs>; +}; + +&A53_3 { + cpu-supply = <®_cpu_dvfs>; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x19 + >; + }; + + pinctrl_csi2: csi2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 + MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x19 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0xc1 + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0xc1 + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0xc1 + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0xc1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_wdog: wdog1grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x46 + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x80 + >; + }; + + pinctrl_ethphy: ethphygrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xc1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13 + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x13 + >; + }; + + pinctrl_can: cangrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0xc0 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0xc1 + >; + }; + + pinctrl_gpio_keys: keygrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0xc6 + MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0xc6 + MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0xc6 + MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0xc6 + >; + }; + + pinctrl_leds: ledgrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xc6 + MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0xc6 + MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0xc6 + MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0xc6 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* WIFI_PWR_VSEL */ + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xc1 /* WIFI_PWR_ON */ + MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0xc1 /* WIFI_REG_ON */ + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0xc1 /* WIFI_CLK_32K */ + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0xc1 /* BT_REG_ON */ + MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1 /* BT_BUF_EN */ + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16 + >; + }; + + pinctrl_lvds: lvdsgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0xc1 + >; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi1_mipi_ep: endpoint@1 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_csi_2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi2_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi2_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi2_mipi_ep: endpoint@1 { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&fec1 { + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>; + clock-names = "mclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + gpio-cfg = < + 0x0018 /* GPIO1 => DMIC_CLK */ + 0xffff /* GPIO2 => don't touch */ + 0xffff /* GPIO3 => don't touch */ + 0xffff /* GPIO4 => don't touch */ + >; + status = "okay"; + }; + + dsi_lvds_bridge: sn65dsi84@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + ti,dsi-lanes = <3>; + ti,lvds-format = <1>; + ti,lvds-bpp = <24>; + ti,lvds-channels = <1>; + ti,width-mm = <154>; + ti,height-mm = <87>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds>; + status = "disabled"; + + display-timings { + lvds { + clock-frequency = <39000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + port { + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + reg_cpu_dvfs: tps62361@60 { + reg = <0x60>; + compatible = "ti,tps62361"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-name = "arm-supply"; + regulator-boot-on; + regulator-always-on; + ti,enable-force-pwm; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* DS1337 RTC module */ + rtc@68 { + status = "okay"; + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + /* Capacitive touch controller */ + ft5x06_ts: ft5x06_ts@38 { + status = "disabled"; + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + /* USB-C controller */ + typec_ptn5150: typec@3d { + status = "okay"; + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + int-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + ov5640_mipi1: ov5640_mipi1@3c { + status = "okay"; + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; +/* Disabled CLKO2, since DART-MX8M camera expansion board uses + * its own oscillator. Enable CLK02 if your desing requres it + */ +#if 0 + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <24000000>; +#endif + csi_id = <0>; + pwn-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio5 28 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + ov5640_mipi2: ov5640_mipi2@3c { + status = "okay"; + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2>; + + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; +/* Disabled CLKO2, since DART-MX8M camera expansion board uses + * its own oscillator. Enable CLK02 if your design requres it + */ +#if 0 + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <24000000>; +#endif + csi_id = <1>; + pwn-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + hard-wired = <1>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "disabled"; +}; + +/* Console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +/* Header */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +/* Bluetooth */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; + assigned-clocks = <&clk IMX8MQ_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + status = "disabled"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <&sw4_reg>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + extcon = <&typec_ptn5150>; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "disabled"; +}; + +&spdif2 { + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "disabled"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&vpu { + status = "okay"; +}; + +&gpu3d { + status = "okay"; +}; + +&irqsteer { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&mu { + status = "okay"; +}; + +&csi1_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&csi2_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; +}; + +&mipi_dsi { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* DCSS Port (IN) */ + port@0 { + reg = <0>; + }; + /* MIPI DSI Port (OUT)*/ + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, + <&gpio1 12 GPIO_ACTIVE_HIGH>, + <&gpio2 20 GPIO_ACTIVE_HIGH>; + status = "okay"; + + /* Resistive touch controller */ + ads7846@0 { + reg = <0>; + compatible = "ti,ads7846"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + status = "disabled"; + }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&can0_osc>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + status = "okay"; + }; + + /* Test SPI device */ + spidev@2 { + reg = <2>; + compatible = "var,spidev"; + spi-max-frequency = <12000000>; + status = "okay"; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-dp.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-dp.dtsi new file mode 100644 index 0000000000000..1bfde545c5d57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-dp.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + disp-dev = "hdmi_disp"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-dp"; + lane-mapping = <0xc6>; + + status = "okay"; + + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; + + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + + dp_on_hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "dp_on"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-hdmi.dtsi new file mode 100644 index 0000000000000..bdba5ac4a2a8c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-hdmi.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +/ { + sound-hdmi { + status = "okay"; + }; +}; + +&dcss { + status = "okay"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-hdmi"; + lane-mapping = <0xe4>; + status = "okay"; + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + + hdmi_on_hog { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "hdmi_on"; + }; +}; + +&sai4 { + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-lvds-dcss.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-lvds-dcss.dtsi new file mode 100644 index 0000000000000..19c2eba8281de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-lvds-dcss.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + + +&irqsteer { + status = "okay"; +}; + +/delete-node/&hdmi; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&dsi_lvds_bridge { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + ports { + port@0 { + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&ft5x06_ts { + status = "okay"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-lvds-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-lvds-lcdif.dtsi new file mode 100644 index 0000000000000..5d5f3c0ba7fc1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-lvds-lcdif.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +&irqsteer { + status = "okay"; +}; + +&lcdif { + status = "okay"; + max-memory-bandwidth = <314676293>; /* 1280x1024-32@60 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port@0 { + lcdif_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&dsi_lvds_bridge { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + ports { + port@0 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&ft5x06_ts { + status = "okay"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-dp.dts new file mode 100644 index 0000000000000..384a1f40a6000 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-dp.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-sd-dp.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+SD+DP"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-hdmi-cb12.dts new file mode 100644 index 0000000000000..50475b6e43432 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-hdmi-cb12.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-sd-hdmi-cb12.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 M4+SD+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-hdmi.dts new file mode 100644 index 0000000000000..995144409f334 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-hdmi.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-sd-hdmi.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+SD+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-cb12.dts new file mode 100644 index 0000000000000..88125b4a49150 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-cb12.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-sd-lvds-cb12.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 M4+SD+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-dp.dts new file mode 100644 index 0000000000000..995aed3c6b52e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-dp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-dp.dtsi" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+SD+LVDS+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-hdmi-cb12.dts new file mode 100644 index 0000000000000..b4c1cdd0ab9c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-hdmi-cb12.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-m4.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 M4+SD+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-hdmi.dts new file mode 100644 index 0000000000000..def2764541d4d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds-hdmi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+SD+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds.dts new file mode 100644 index 0000000000000..755de1b98550a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-sd-lvds.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-sd-lvds.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+SD+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-dp.dts new file mode 100644 index 0000000000000..57681a3dfeabc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-dp.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-wifi-dp.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+WIFI+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-hdmi-cb12.dts new file mode 100644 index 0000000000000..bf8dc05c4f0c7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-hdmi-cb12.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-wifi-hdmi-cb12.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 M4+WIFI+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-hdmi.dts new file mode 100644 index 0000000000000..8f9d8721fd4ac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-hdmi.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-wifi-hdmi.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+WIFI+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-cb12.dts new file mode 100644 index 0000000000000..7c617601a5264 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-cb12.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-wifi-lvds-cb12.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 M4+WIFI+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-dp.dts new file mode 100644 index 0000000000000..9aa6cfc8ee3dd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-dp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2019-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-dp.dtsi" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+WIFI+LVDS+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-hdmi-cb12.dts new file mode 100644 index 0000000000000..2afe683f82df3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-hdmi-cb12.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2019-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-m4.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 M4+WIFI+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-hdmi.dts new file mode 100644 index 0000000000000..911848d88a43f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds-hdmi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2019-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+WIFI+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds.dts new file mode 100644 index 0000000000000..23f731f2b3798 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4-wifi-lvds.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-wifi-lvds.dts" +#include "imx8mq-var-dart-m4.dtsi" + +/ { + model = "Variscite DART-MX8M M4+WIFI+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4.dtsi new file mode 100644 index 0000000000000..7f327466bf5b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-m4.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2019-2020 Variscite Ltd. + */ + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x7e000000 { + no-map; + reg = <0 0x7e000000 0 0x1000000>; + }; + + rpmsg_reserved: rpmsg@0x40000000 { + no-map; + reg = <0 0x40200000 0 0x200000>; + }; + + vdev0vring0: vdev0vring0@40000000 { + compatible = "shared-dma-pool"; + reg = <0 0x40000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@40008000 { + compatible = "shared-dma-pool"; + reg = <0 0x40008000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@40400000 { + compatible = "shared-dma-pool"; + reg = <0 0x40400000 0 0x100000>; + no-map; + }; + + }; + + imx8mq-cm4 { + compatible = "fsl,imx8mq-cm4"; + rsc-da = <0x40000000>; + clocks = <&clk IMX8MQ_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0x40000000~0x4000ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0x40000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "okay"; +}; + +&tmu { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-dp.dts new file mode 100644 index 0000000000000..8f60637184ef2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-dp.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-dp.dtsi" + +/ { + model = "Variscite DART-MX8M SD+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-hdmi-cb12.dts new file mode 100644 index 0000000000000..688f3a77cc12a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-hdmi-cb12.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 SD+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-hdmi.dts new file mode 100644 index 0000000000000..a175e4a95dd05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-hdmi.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" + +/ { + model = "Variscite DART-MX8M SD+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-cb12.dts new file mode 100644 index 0000000000000..71f487680313e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-cb12.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-dcss.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 SD+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-dp.dts new file mode 100644 index 0000000000000..2daaf30487de2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-dp.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-dp.dtsi" + +/ { + model = "Variscite DART-MX8M SD+LVDS+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-hdmi-cb12.dts new file mode 100644 index 0000000000000..5b9d39fc0cdbc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-hdmi-cb12.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 SD+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-hdmi.dts new file mode 100644 index 0000000000000..ab8340c723e12 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds-hdmi.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" + +/ { + model = "Variscite DART-MX8M SD+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds.dts new file mode 100644 index 0000000000000..ccb96443802f0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd-lvds.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-sd.dtsi" +#include "imx8mq-var-dart-lvds-dcss.dtsi" + +/ { + model = "Variscite DART-MX8M SD+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd.dtsi new file mode 100644 index 0000000000000..60148443370cc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-sd.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +/ { + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_eth_phy: eth_phy { + compatible = "regulator-fixed"; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* SD card voltage select pin */ +&iomuxc { + pinctrl_usdhc2_vsel: usdhc2grpvsel { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + pinctrl_usdhc2_cd: usdhc2grpcd { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; +}; + +/* SD card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>, <&pinctrl_usdhc2_vsel>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>, <&pinctrl_usdhc2_vsel>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>, <&pinctrl_usdhc2_vsel>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_ethphy>; + phy-supply = <®_eth_phy>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-dp.dts new file mode 100644 index 0000000000000..f576d77b0d987 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-dp.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-dp.dtsi" + +/ { + model = "Variscite DART-MX8M WIFI+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-hdmi-cb12.dts new file mode 100644 index 0000000000000..e7db3b0c1fdbb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-hdmi-cb12.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 WIFI+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-hdmi.dts new file mode 100644 index 0000000000000..89045825a7112 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-hdmi.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" + +/ { + model = "Variscite DART-MX8M WIFI+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-cb12.dts new file mode 100644 index 0000000000000..8a5845989ca0a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-cb12.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-dcss.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 WIFI+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-dp.dts new file mode 100644 index 0000000000000..250275a68fbc1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-dp.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-dp.dtsi" + +/ { + model = "Variscite DART-MX8M WIFI+LVDS+DP"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-hdmi-cb12.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-hdmi-cb12.dts new file mode 100644 index 0000000000000..2de744c10e15c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-hdmi-cb12.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" +#include "imx8mq-var-dart-cb12.dtsi" + +/ { + model = "Variscite DART-MX8M CB-1.2 WIFI+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-hdmi.dts new file mode 100644 index 0000000000000..7e6d11c175506 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds-hdmi.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-lcdif.dtsi" +#include "imx8mq-var-dart-hdmi.dtsi" + +/ { + model = "Variscite DART-MX8M WIFI+LVDS+HDMI"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds.dts b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds.dts new file mode 100644 index 0000000000000..96574731e9cfd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi-lvds.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +#include "imx8mq-var-dart-common.dtsi" +#include "imx8mq-var-dart-wifi.dtsi" +#include "imx8mq-var-dart-lvds-dcss.dtsi" + +/ { + model = "Variscite DART-MX8M WIFI+LVDS"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi.dtsi new file mode 100644 index 0000000000000..5f03316dac292 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-var-dart-wifi.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright 2018-2020 Variscite Ltd. + */ + +/* Bluetooth */ +&uart4 { + status = "okay"; +}; + +/* Set WIFI SDIO voltage at 1.8V */ +&gpio1 { + wifi_vsel_hog { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "wifi_vsel"; + }; +}; + +/* WIFI */ +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; +}; diff --git a/arch/arm64/configs/imx8mq_var_dart_defconfig b/arch/arm64/configs/imx8mq_var_dart_defconfig new file mode 100644 index 0000000000000..db4e2ecaf64e8 --- /dev/null +++ b/arch/arm64/configs/imx8mq_var_dart_defconfig @@ -0,0 +1,830 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_ARCH_MXC=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23144 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NUMA=y +CONFIG_SECCOMP=y +CONFIG_COMPAT=y +# CONFIG_EFI is not set +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_IMX_DSP=m +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_KSM=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_NET_SCHED=y +CONFIG_NET_CLS_CGROUP=m +CONFIG_NETLINK_DIAG=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_MCP251XFD_SANITY=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_LEDS=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCM=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_LEDS=y +CONFIG_PCI=y +CONFIG_PCI_IMX6=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_MTD=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_SPI_NOR=m +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NVME=m +CONFIG_SRAM=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=m +# CONFIG_SATA_PMP is not set +CONFIG_SATA_AHCI=m +CONFIG_AHCI_IMX=m +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_FEC=m +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_AT803X_PHY=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_BRCMFMAC=m +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_RT2X00=m +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ATKBD=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_PWRKEY=y +CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2_ALPS is not set +# CONFIG_MOUSE_PS2_BYD is not set +# CONFIG_MOUSE_PS2_LOGIPS2PP is not set +# CONFIG_MOUSE_PS2_SYNAPTICS is not set +# CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS is not set +# CONFIG_MOUSE_PS2_CYPRESS is not set +# CONFIG_MOUSE_PS2_TRACKPOINT is not set +# CONFIG_MOUSE_PS2_FOCALTECH is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_CT36X_WLD is not set +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM_CAVIUM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_SLAVE=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_FSL_LPSPI=m +CONFIG_SPI_FSL_QUADSPI=m +CONFIG_SPI_NXP_FLEXSPI=m +CONFIG_SPI_IMX=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_POWER_AVS=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX_THERMAL=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=y +CONFIG_MFD_IMX_AUDIOMIX=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_BD718XX=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_TPS62360=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_IMX8_MIPI_CSI2_YAV=m +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_OV5640=y +# CONFIG_CXD2880_SPI_DRV is not set +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA18250 is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MSI001 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_AF9033 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_DW_HDMI_GP_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_I2C_SN65DSI83=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_MXSFB=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_SOUND=y +CONFIG_SND=m +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_PCI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_DAI=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_MICFIL=m +CONFIG_SND_SOC_IMX_MQS=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_SOC_IMX_PDM_MIC=m +CONFIG_SND_SOC_IMX_CDNHDMI=m +CONFIG_SND_SOC_IMX_XCVR=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_CONN_GPIO=m +CONFIG_USB=m +# CONFIG_USB_PCI is not set +CONFIG_USB_OTG=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_XHCI_HCD=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=m +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_OF_SIMPLE is not set +CONFIG_USB_CHIPIDEA=m +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_NOP_USB_XCEIV=m +CONFIG_USB_GPIO_VBUS=m +CONFIG_USB_MXS_PHY=m +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=m +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_GADGET_UAC1=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_UCSI=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_SWITCH_GPIO=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LEDS_TRIGGER_AUDIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_DMA=m +CONFIG_IMX_SDMA=m +CONFIG_MXS_DMA=y +# CONFIG_MX3_IPU is not set +CONFIG_UIO=y +# CONFIG_VIRTIO_MENU is not set +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_CAPTURE=y +# CONFIG_GMSL_MAX9286 is not set +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_HWSPINLOCK=y +# CONFIG_HISILICON_ERRATUM_161010101 is not set +CONFIG_MAILBOX=y +CONFIG_IMX_MBOX=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_IMX_SCU_SOC=y +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_USB_GPIO=m +CONFIG_IIO=y +CONFIG_IMX8QXP_ADC=y +CONFIG_PWM=y +CONFIG_PWM_IMX27=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_MIXEL_MIPI_DPHY=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y +CONFIG_FSL_IMX8_DDR_PMU=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_TEE=m +CONFIG_OPTEE=m +CONFIG_MUX_MMIO=y +CONFIG_MXC_HANTRO=m +CONFIG_MXC_HANTRO_845=m +CONFIG_MXC_HANTRO_845_H1=m +CONFIG_MXC_GPU_VIV=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_HUGETLBFS=y +CONFIG_CONFIGFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y