Skip to content
master
Switch branches/tags
Code

Latest commit

 

Git stats

Files

Permalink
Failed to load latest commit information.
Type
Name
Latest commit message
Commit time
 
 
 
 
 
 
 
 
 
 
 
 

Computer

My hardware implementation of a fully-functioning computer with a custom-designed ISA, written in Verilog.

WIP

Verilog version is work-in-progress.

About

Custom ISA computer designed in Logisim and then rewritten in Verilog

Resources

Releases

No releases published

Packages

No packages published