From 4e5f30858bc130dcc2d6934aacf3ace562855e12 Mon Sep 17 00:00:00 2001
From: Yutetsu TAKATSUKASA <y.takatsukasa@gmail.com>
Date: Wed, 5 Jan 2022 08:37:20 +0900
Subject: [PATCH] Fix #3258 of internal error with inout port (#3268)

* Tests: Modify t_tri_inout to reproduce #3258

* Set direction of __en accorting to its main signal direction

* Update Changes
---
 Changes                      | 1 +
 src/V3Tristate.cpp           | 9 ++++++---
 test_regress/t/t_tri_inout.v | 9 ++++++++-
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/Changes b/Changes
index daa68384ba..413c4a827d 100644
--- a/Changes
+++ b/Changes
@@ -36,6 +36,7 @@ Verilator 4.217 devel
 * Fix $random not updating seed (#3238). [Julie Schwartz]
 * Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz]
 * Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD]
+* Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA]
 
 
 Verilator 4.216 2021-12-05
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index 21097a627d..d09acd2725 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -546,8 +546,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             UINFO(9, "     TRISTATE propagates up with " << lhsp << endl);
             // Create an output enable port (__en)
             // May already be created if have foo === 1'bz somewhere
-            envarp = getCreateEnVarp(invarp);
-            envarp->varType2Out();
+            envarp = getCreateEnVarp(invarp);  // direction will be sen in visit(AstPin*)
             //
             outvarp->user1p(envarp);
             outvarp->user3p(invarp->user3p());  // AstPull* propagation
@@ -1162,7 +1161,11 @@ class TristateVisitor final : public TristateBaseVisitor {
                 AstVar* const enVarp = new AstVar(nodep->fileline(), VVarType::MODULETEMP,
                                                   nodep->name() + "__en" + cvtToStr(m_unique++),
                                                   VFlagBitPacked(), enModVarp->width());
-                enModVarp->direction(VDirection::INPUT);
+                if (inDeclProcessing) {  // __en(from-resolver-const) or __en(from-resolver-wire)
+                    enModVarp->varType2In();
+                } else {
+                    enModVarp->varType2Out();
+                }
                 UINFO(9, "       newenv " << enVarp << endl);
                 AstPin* const enpinp
                     = new AstPin(nodep->fileline(), nodep->pinNum(),
diff --git a/test_regress/t/t_tri_inout.v b/test_regress/t/t_tri_inout.v
index d466259cd7..d6624b04d8 100644
--- a/test_regress/t/t_tri_inout.v
+++ b/test_regress/t/t_tri_inout.v
@@ -11,7 +11,7 @@ module top (input A, input B, input SEL, output Y1, output Y2, output Z);
 endmodule
 
 module pass (input A, input OE, inout Z, output Y);
-   io io(.A(A), .OE(OE), .Z(Z), .Y(Y));
+   io_noinline io(.A(A), .OE(OE), .Z(Z), .Y(Y));
    assign Z = 1'bz;
 endmodule
 
@@ -20,3 +20,10 @@ module io (input A, input OE, inout Z, output Y);
    assign Y = Z;
    assign Z = 1'bz;
 endmodule
+
+module io_noinline (input A, input OE, inout Z, output Y);
+   /*verilator no_inline_module*/
+   assign Z = (OE) ? A : 1'bz;
+   assign Y = Z;
+   assign Z = 1'bz;
+endmodule