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Reset fails to respond when driven from vector containing clock enable #1036

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veripoolbot opened this issue Feb 14, 2016 · 3 comments
Open

Reset fails to respond when driven from vector containing clock enable #1036

veripoolbot opened this issue Feb 14, 2016 · 3 comments

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@veripoolbot veripoolbot commented Feb 14, 2016


Author Name: Neil Turton
Original Redmine Issue: 1036 from https://www.veripool.org
Original Date: 2016-02-14


In the attached test, the active low reset output fails to go high when the active high input goes low.

There are several work-arounds. One is to define the FIXIT macro which modifies the test code. Another is to remove the clock_enable comment. Another is to delete slave_clk.

To reproduce, save the attached files in the current directory and run the commands:
make
./obj_dir/Verror9

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@veripoolbot veripoolbot commented Feb 14, 2016


Original Redmine Comment
Author Name: Neil Turton
Original Date: 2016-02-14T17:37:10Z


There's a formatting problem in the commands to reproduce the issue. There should be two commands (separated by a new line which got removed). So, "make ; ./obj_dir/Verror9" would do.

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@veripoolbot veripoolbot commented Feb 24, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-02-24T02:22:48Z


Attributes such as the clock enables and clocks themselves are propagated signal-by-signal rather than bit-of-signal. So what's going on here is the clock enable attribute also gets associated with the reset. This is certainly a bug, but fairly fundamental so unfortunately is unlikely to be resolved any time soon, sorry.

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@veripoolbot veripoolbot commented Feb 24, 2016


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2016-02-24T14:42:24Z


This looks very similar to a problem we had with vectors of clocks:

http://www.veripool.org/issues/1009-Verilator-Non-cutable-ordering-loop-when-using-an-array-of-clocks

I've been slacking on cleaning this up for pushing back upstream, but the GitHub link has the code that we are currently using to address the issue. I haven't tried your code, however, my suspicion is that it will not work for you. But it should be trivial to apply the same technique for clock enable signals (as opposed to clocks).

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