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assignment to a packed array variable formed from a concatenation #1042

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veripoolbot opened this issue Feb 26, 2016 · 3 comments
Closed

assignment to a packed array variable formed from a concatenation #1042

veripoolbot opened this issue Feb 26, 2016 · 3 comments

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@veripoolbot veripoolbot commented Feb 26, 2016


Author Name: steven prigg
Original Redmine Issue: 1042 from https://www.veripool.org


I have a structure defined:

typedef struct packed {
logic [15:0] ESR;
logic [15:0] LS;
logic [15:0] LE;
logic [15:0] OR0;
logic [15:0] OR1;
logic [15:0] OR2;
logic [15:0] ORA;
} regs_struct;

this then forms a port definition of a module (as an output):

module syb_registers (
output regs_struct regs, // registers passed out as structure

when trying to assign to regs.ESR in the following way:
assign regs.ESR = {ESR_int[15:7],ESP};

where ESP[6:0] and ESR_int[15:0] are driven from clocked always@ blocks, the assignment fails even though ESR_int and ESP present the correct values.
i.e. regs.ESR is always '0

a workaround is:
wire [15:0] ESR_collected;
assign ESR_collected[15:7] = ESR_int[15:7];
assign ESR_collected[6:0] = ESP;
assign regs.ESR = ESR_collected;

here the assignment to regs.ESR is successful.

The observed behaviour differs from simulation results from leading CAD vendors.

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@veripoolbot veripoolbot commented Feb 26, 2016


Original Redmine Comment
Author Name: steven prigg
Original Date: 2016-02-26T11:38:38Z


correct formatting of code fragments:

typedef struct packed { 
     logic [15:0] ESR; 
     logic [15:0] LS; 
     logic [15:0] LE; 
     logic [15:0] OR0; 
     logic [15:0] OR1; 
     logic [15:0] OR2; 
     logic [15:0] ORA; } regs_struct;

workaround:
wire [15:0] ESR_collected; 
assign ESR_collected[15:7] = ESR_int[15:7]; 
assign ESR_collected[6:0] = ESP; 
assign regs.ESR = ESR_collected;


apologies.

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@veripoolbot veripoolbot commented Feb 27, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-02-27T14:49:32Z


Can you please provide a test case in test_regress format as described in the manual? Then hopefully will be a quick fix.

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@veripoolbot veripoolbot commented Apr 2, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-02T12:57:21Z


Closing due to age and no regression test; feel free to file another bug if this is still a problem with the most recent release.

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