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how to ignore the warning? #1073

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veripoolbot opened this issue Jul 12, 2016 · 5 comments
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how to ignore the warning? #1073

veripoolbot opened this issue Jul 12, 2016 · 5 comments

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@veripoolbot veripoolbot commented Jul 12, 2016


Author Name: nan wu
Original Redmine Issue: 1073 from https://www.veripool.org
Original Date: 2016-07-12


I am a new user. There will be warnings and error When there is a delay(such as '#10') in the verilog module. It shows" Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. "
So I added "lint_off -msg STMTDLY" in file named t_vlt_warn.vlt. But it didn't work.
Please help me !
Thanks very much!

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@veripoolbot veripoolbot commented Jul 12, 2016


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2016-07-12T07:20:57Z


Generally two ways to disable warning.

You can add some comments in the verilog source where the warning is reported, then the particular warning will be ignored.

/* verilator lint_off STMTDLY */
ssdfd  // code where the warning is report
/* verilator lint_on STMTDLY */

Another way is to disable all STMTDLY warning by adding

-Wno-STMTDLY

option when you invoke Verilator.

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@veripoolbot veripoolbot commented Jul 12, 2016


Original Redmine Comment
Author Name: nan wu
Original Date: 2016-07-12T08:16:27Z


%Warning-STMTDLY: our.v:20: Unsupported: Ignoring delay on this delayed statement.

The problem is solved, but I found that the delay(such as "#10") has been optimized and ignored. It didn't work.
How to make it not ignore the delay ?

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@veripoolbot veripoolbot commented Jul 12, 2016


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2016-07-12T09:50:07Z


Short answer: you can't.

Long answer: Verilator simulates synthesizable verilog code and @#10@ is not synthesizable.

Please read a bit more about documentation.

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@veripoolbot veripoolbot commented Jul 12, 2016


Original Redmine Comment
Author Name: nan wu
Original Date: 2016-07-12T13:00:17Z


I am sorry. I have saw that Verilator simulates synthesizable verilog code in documentation. But there still is a foolish question in my mind--how to simulate(provide input)? We write testbench by verilogHDL when using ModelSim, does it need use SystemC/C++ to create the testbench if we use Verilator? Then the testbench will be very complex in order to test all the situations, but the authority said it just need write a touch of C code and Makefiles after synthesizable verilog is migrated to C++ or SystemC.

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@veripoolbot veripoolbot commented Jul 14, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-07-14T02:52:33Z


No change needed. See also the errors and warnings section of the manual, to which I made a tweak in git to mention config files.

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