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Author Name: Jan Egil Ruud
I have a rather complex problem where Verilator creates a wrong simulation result, and I've attached some basic verilog code to help explaining the issue.
In my design there is a clock bus where one clock is the main clock (clk_bus in the attached code), and the other clocks are peripheral clocks (clk_bus[2:0]) that can be enabled or disabled with clk_en[2:0]. The clock source for the peripheral clock is the main clock (clk_bus), which means that one of the clocks in the bus is the source of the others. I have a Incisive (Cadence) simulation that simulates this correctly, but with Verilator some registers are updated one cycle early. My workaround has been to separate the main clock from the clk_bus. Then the design simulates correctly with Verilator. Since this design is rather complex I have not been able to create a proper failing test case.
Original Redmine Comment
I'm not entirely sure, but this may be related to "Issue #1009":http://www.veripool.org/issues/1009-Verilator-Non-cutable-ordering-loop-when-using-an-array-of-clocks#change-3385. In the issue, I proposed a patch which decomposes clock vectors during Verilation, but never got around to reworking it after Wilson's comments. Even though it hasn't be been upstreamed, we are currently running with this patch. So you might want to try it out to see if that fixes your problem until I get around to following through on this one.