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Simulation errors with clock bus #1121

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veripoolbot opened this issue Jan 3, 2017 · 4 comments
Closed

Simulation errors with clock bus #1121

veripoolbot opened this issue Jan 3, 2017 · 4 comments

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@veripoolbot veripoolbot commented Jan 3, 2017


Author Name: Jan Egil Ruud
Original Redmine Issue: 1121 from https://www.veripool.org


I have a rather complex problem where Verilator creates a wrong simulation result, and I've attached some basic verilog code to help explaining the issue.

In my design there is a clock bus where one clock is the main clock (clk_bus[3] in the attached code), and the other clocks are peripheral clocks (clk_bus[2:0]) that can be enabled or disabled with clk_en[2:0]. The clock source for the peripheral clock is the main clock (clk_bus[3]), which means that one of the clocks in the bus is the source of the others. I have a Incisive (Cadence) simulation that simulates this correctly, but with Verilator some registers are updated one cycle early. My workaround has been to separate the main clock from the clk_bus. Then the design simulates correctly with Verilator. Since this design is rather complex I have not been able to create a proper failing test case.

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@veripoolbot veripoolbot commented Jan 3, 2017


Original Redmine Comment
Author Name: Jan Egil Ruud
Original Date: 2017-01-03T11:42:45Z


(Forgot the attachment of course...)

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@veripoolbot veripoolbot commented Jan 3, 2017


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2017-01-03T14:08:21Z


I'm not entirely sure, but this may be related to "Issue #1009":http://www.veripool.org/issues/1009-Verilator-Non-cutable-ordering-loop-when-using-an-array-of-clocks#change-3385. In the issue, I proposed a patch which decomposes clock vectors during Verilation, but never got around to reworking it after Wilson's comments. Even though it hasn't be been upstreamed, we are currently running with this patch. So you might want to try it out to see if that fixes your problem until I get around to following through on this one.

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@veripoolbot veripoolbot commented Jan 4, 2017


Original Redmine Comment
Author Name: Jan Egil Ruud
Original Date: 2017-01-04T08:21:33Z


Thanks. I'll give it a try and let you know.

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@veripoolbot veripoolbot commented Dec 17, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-12-17T23:01:40Z


Closing due to age, please file a new issue if you are still having problems.

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