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Verilator doesn't detect multiple assignment #1184

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veripoolbot opened this issue Jul 18, 2017 · 0 comments
Open

Verilator doesn't detect multiple assignment #1184

veripoolbot opened this issue Jul 18, 2017 · 0 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jul 18, 2017


Author Name: Dan Gisselquist
Original Redmine Issue: 1184 from https://www.veripool.org


Consider the following code, first posted on the forum:

module tst(i_clk, i_val, o_a, o_b);
         input   wire    i_clk;
         input   wire    i_val;
         output  reg     o_a, o_b;

         always @(posedge i_clk)
                 if ((i_val)&&(!o_a))
                         o_b <= 1'b0;

         always @(posedge i_clk)
                 if ((i_val)&&(o_a))
                         o_b <= 1'b1;

         always @(posedge i_clk)
                 o_a <= i_val;

endmodule
</code>

Notice how o_b is being set to contradictory values. I'd like to recommend that Verilator check for this.

I've searched through V3Delayed.cpp, seen the MULTIDRIVEN logic, thought to try to fix it but ... I'm still struggling to figure out what's going on. ;) I know, it can't be too hard ... I know what an AST is, I know what a parser is, etc., I just ... haven't figured it out yet. Oh, ok, here it is ... just found the defn of an ActiveAST ... I think I see the problem now, I just don't (yet) know how I might fix it.

Dan

Dan

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