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Support for interfaces in top level ports #1185

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veripoolbot opened this issue Jul 19, 2017 · 2 comments
Closed

Support for interfaces in top level ports #1185

veripoolbot opened this issue Jul 19, 2017 · 2 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jul 19, 2017


Author Name: Kevin Kiningham (@kkiningh)
Original Redmine Issue: 1185 from https://www.veripool.org


I'd like to add support for interfaces in top level ports. A simple test cast:

@interface bus_if(input wire clock);
logic data;

modport slave(input data);
modport master(output data);
endinterface

module top(bus_if.slave bus);

endmodule@

Current git HEAD (ca26596) currently fails with the following:

kkiningh@kkiningh:~/Workspace/$ ./verilator/build/bin/verilator test.sv -cc
%Error: test.sv:8: Unsupported: Interfaced port on top level module
%Error: test.sv:8: Parent cell's interface is not found: bus_if
%Error: Exiting due to 2 error(s)
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /home/kkiningh/Workspace/verilator/build/bin/verilator_bin test.sv -cc

How much work would it be to support this feature? Can you give me a few hints on how to get started? I've looked in verilator/src/V3LinkParse.cpp and can see where the error is generated but cannot figure out how to proceed. Also, can you expand a bit on what the comment on line 198 is talking about ("What breaks later is we don't have a Scope/Cell representing the interface to attach to")?

Thanks!

@veripoolbot
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@veripoolbot veripoolbot commented Jul 23, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-07-23T01:51:45Z


Interfaces work in Verilator by creating a variable on both the upper and lower scope that links into an instantiated interface (CELL in the AST). The top doesn't have any upper scope to contain this. The other problem would be how would you access the variables from C? Verilator doesn't presently create structs that C can use, so it's not obvious what this would look like.

You could of course make wrapper code that flattened the interfaces into normal signals for C. I realize this isn't clean of course.

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@veripoolbot veripoolbot commented Oct 9, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-09T01:03:12Z


This is unlikely to be supported in the medium term due to the complexities of mapping into C++. A wrapper is suggested instead.

If someone wants to contribute a fix, we can discuss.

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