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Can't override parameter defined as "type xxxx" through command line with "-G" #1192

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veripoolbot opened this issue Aug 25, 2017 · 6 comments
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@veripoolbot veripoolbot commented Aug 25, 2017


Author Name: Enzo Chi
Original Redmine Issue: 1192 from https://www.veripool.org


Verilator support type as parameter as "parameter type DATA_T = byte" but can't override it from command line with "-G"

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@veripoolbot veripoolbot commented Aug 25, 2017


Original Redmine Comment
Author Name: Enzo Chi
Original Date: 2017-08-25T02:01:28Z


I have a simple test file:

module dummy #(parameter type DATA_T = byte)
(
input DATA_T din,
output DATA_T dout
);

 assign dout = din + 1'b1;

endmodule // dummy

It can be compiled as: verilator --cc dummy.sv
But report error when: verilator --cc dummy.sv -GDATA_T=int

Error message:

%Error: Parameters from the command line were not found in the design: DATA_T

%Error: Command Failed verilator/3_906/bin/verilator_bin --cc dummy.sv '-GDATA_T=byte'

Verilator Version: 3.906

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@veripoolbot veripoolbot commented Aug 29, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T02:56:25Z


This is slightly painful to fix as the parser is all that understands the types, not the command line parser. Would this be OK to only work for simple built in non-sized types ("int" etc)? Any idea if it works with other simulators?

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@veripoolbot veripoolbot commented Aug 29, 2017


Original Redmine Comment
Author Name: Enzo Chi
Original Date: 2017-08-29T11:02:11Z


I don't have other simulator with me. I may try it later on the edaplayground.com

Only support simple built in non-sized types will not be good enough for me. Because I would expect to pass different type of packed structs here (or logic vector which synthesis tool supports).

I am not good at software, about the parser issue, I can understand, but is it possible to do something like just replace the original type with override one to temporary files and the parse them.

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@veripoolbot veripoolbot commented Aug 29, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T12:33:57Z


The simplest thing would be to do this:

ifndef PARAM_TYPE define PARAM_TYPE logic
endif parameter type foo_t = PARAM_TYPE;

Then use -DPARAM_TYPE=int.

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@veripoolbot veripoolbot commented Aug 29, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T12:36:36Z


And if you can't edit the source, Verilog-Mode can easily make a wrapper you then edit.

module ModnameStub (/AUTOARG/);
/AUTOINOUTPARAM("Modname")/
/AUTOINOUTMODULE("Modname")/
/AUTOWIRE/
Modname sub (.*);
endmodule

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@veripoolbot veripoolbot commented Nov 18, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-18T22:56:38Z


As far as I can tell this isn't supported in other simulators, so unless someone wants to commit a relatively complicated patch, the best bet is the `ifdef trick mentioned earlier.

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