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Feature request: Nested module definitions #1195

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veripoolbot opened this issue Aug 30, 2017 · 2 comments
Closed

Feature request: Nested module definitions #1195

veripoolbot opened this issue Aug 30, 2017 · 2 comments

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@veripoolbot veripoolbot commented Aug 30, 2017


Author Name: Rob Stoddard
Original Redmine Issue: 1195 from https://www.veripool.org


I have run into this issue where two modules with the same names can create a conflict. Since I'm dealing with a lot of NIH IP, the solution cannot be merely to "don't name two modules the same thing." I can however ensure that modules are scoped by nesting them inside of a module that wraps each IP in the design. To that end, the SystemVerilog feature of nested module definitions would be a very nice thing to have in Verilator. For example, I would like to be able to do this:

module top ();
  wire a, b, c;
  module nested;
     assign c = a & b; 
  endmodule
  nested nested_i ();
endmodule
</code>

How hard would this be to add?

Thank you
Rob Stoddard

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@veripoolbot veripoolbot commented Aug 30, 2017


Original Redmine Comment
Author Name: Rob Stoddard
Original Date: 2017-08-30T17:38:07Z


There is an article defining this feature of the language at http://invionics.com/systemverilog-part1/

Furthermore, the 1800-2012 specification shows this feature in section 23.4, Nested Modules, using the example:

// This example shows how the flip-flop can be structured into 3 RS latches.
module dff_nested(input d, ck, pr, clr, output q, nq);
  wire q1, nq1, nq2;
  module ff1;
     nand g1b (nq1, d, clr, q1);
     nand g1a (q1, ck, nq2, nq1);
  endmodule
  ff1 i1();
  module ff2;
     wire q2; // This wire can be encapsulated in ff2
     nand g2b (nq2, ck, clr, q2);
     nand g2a (q2, nq1, pr, nq2);
  endmodule
  ff2 i2();
  module ff3;
     nand g3a (q, nq2, clr, nq);
     nand g3b (nq, q1, pr, q);
  endmodule
  ff3 i3();
endmodule
</code>
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@veripoolbot veripoolbot commented Aug 30, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-30T18:30:11Z


Nested modules are a language abomination that the IEEE should have known better not to add. Most of the commercial tools I am aware of do not support them, and so it's very unlikely Verilator ever will. Sorry.

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