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`define macro including `", `\`", and `` has issues for empty strings #1225

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veripoolbot opened this issue Oct 4, 2017 · 3 comments
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@veripoolbot veripoolbot commented Oct 4, 2017


Author Name: Odd Magne Reitan
Original Redmine Issue: 1225 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Run code at bottom as verilator -E -P test.sv

  1. The intension is that $display(ITEM(CPU,)); should produce "CPU" but, the macro expansion leaves 3 "" characters which verilator has problem with and issues:
    %Error: test.sv:35: `" not terminated at EOF
    %Error: Internal Error: test.sv:35: ../V3PreProc.cpp:1207: Bad case

Synopsys VCS and Cadence Incisive correctly outputs "CPU" in this case.

  1. Using `` to avoid space when concatenating a text to make up a define works in Verilator when FAMILY is defined to something - like the out-commented "Artix". However, if the string is empty it depends; if Newline after FAMILY it does not output the expected "XILINX_", but it does if some one or more space characters are added before newline.

As it is defined, but to an empty text, it shoudl output "XILINX_".

Note in particular that issue 1 is not solved by adding white-spaces like $display(`ITEM(CPU, ));

`define ITEM(SUB,UNIT) `STRING(SUB``UNIT)


module test ();
`define STRING( A ) `"A`"

//`define FAMILY Artix
`define FAMILY

 `define XILINX_```FAMILY
     
  initial
     begin
       $display(`ITEM(RAM,0));
       $display(`ITEM(CPU,));
       
`ifdef XILINX_Artix
       $display("XILINX_Artix is defined");
`endif      
`ifdef XILINX_
       $display("XILINX_ is defined");
`endif      
`ifdef XILINX_FAMILY
       $display("XILINX_FAMILY is defined");
`endif      
     end // initial begin
  
endmodule // test

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@veripoolbot veripoolbot commented Oct 5, 2017


Original Redmine Comment
Author Name: Odd Magne Reitan
Original Date: 2017-10-05T14:19:20Z


A more interesting special-case of issue 2 is the code below. Run as verilator -E -P test.sv and it will output

%Error: test.sv:12: Expecting symbol to terminate ; whitespace etc cannot follow . Found: EOF
%Error: Exiting due to 1 error(s)

Note: Adding a module or something removes this error; that is why it was not visible in the original testcase. Typically `defines are contained within a file which is listed in a manifest file sourced by the -F option. The issue is also visible then.

a) For a parser, `` is followd by something else than whitespace; FAMILY. Hence, the error message is not right. That FAMILY expands to whitespace or CR is a different story.
b) No CAD tools seems to have a problem with this construct.
c) Problem exist if FAMILY is either undefined or defined to nothing.

//`define FAMILY Artix
//`define FAMILY

`ifdef FAMILY
 `define XILINX_```FAMILY
`endif
 

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@veripoolbot veripoolbot commented Oct 7, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-10-07T18:10:54Z


Thanks for the good report & test.

Fixed in git towards 3.914.

Matching bug in Verilog-Perl, fixed in git towards 3.446.

Please give it a try to make sure there's not another missing case (had similar issue with "`foo```bar(param)" )

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@veripoolbot veripoolbot commented Oct 14, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-10-14T20:22:30Z


In 3.914.

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