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Author Name: Odd Magne Reitan
Original Assignee: Wilson Snyder (@wsnyder)
In a verilog project, common structures like defines, macro functions, system verilog functions and tasks may be contained within one or more include files. Any file that makes use these common structures include the include file. A common way to ensure the definitions take place only once is to include in the top of the include file:
However, if the same include file is included from different files, it seems like verilator in precompile mode (-E option) forget the `define INC1 and includes the content of inc1.sv also second time.
This duplication will (dependent of the content of the include file) lead to error if the precompiled output file is simulated in a simulator. If the include file is included twice or more from within the same file, the module "dummy" will be included only once as expected.
Original Redmine Comment
In your example it looked like the `define was ignored, but really it was repeating the first file's output twice. This only occurred with -E which is why it likely hadn't been noticed. Thanks for the report.
Fixed in git towards 3.914.