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Nested interface reference not found due to inline optimization #1250

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veripoolbot opened this issue Dec 13, 2017 · 2 comments
Closed

Nested interface reference not found due to inline optimization #1250

veripoolbot opened this issue Dec 13, 2017 · 2 comments
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@veripoolbot veripoolbot commented Dec 13, 2017


Author Name: Arjen Roodselaar
Original Redmine Issue: 1250 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


When a parent module instantiates an interface (or passes an interface from its parent) to a child module, nested interface references are not found if the child and parent modules do not use the same port name for the interface reference. The following is a somewhat minimal reproduction of the problem:

/* if1.sv */
interface if1;

logic s1;

endinterface : if1

/* if2.sv */
interface if2;

if1 a;
logic s2;

endinterface : if2;

/* mod1.sv */
module mod1

(
  if2 foo
);

logic l1, l2;

always_comb @(*) begin
  l1 = foo.a.s1;
  l2 = foo.s2;
end

endmodule : mod1

/* top.sv */
module top;

if2 if2_0;

assign if2_0.a.s1 = 0;
assign if2_0.s2 = 1;

mod1 mod1_instance(
  .foo (if2_0)
);

endmodule : top;

This results in the following error:

%Error: mod1.sv:11: Can't find definition of 'foo' in dotted signal: foo.a.s1
%Error:      Known scopes under 's1': <no cells found>
%Error: Internal Error: mod1.sv:11: ../V3Const.cpp:1531: Not linked
%Error: Command Failed /Users/arjen/dev/verilator/bin/verilator_bin -cc --trace --compiler clang -sv +1800-2012ext+sv -y . top.sv

Compilation succeeds if the offending line is commented out, or if all occurrences of "foo" in mod1 are replaced with if2_0. Please advice if this is expected and I am simply trying to do something that is not supported.

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@veripoolbot veripoolbot commented Dec 14, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-12-14T00:52:17Z


This was a bug in the inliner, thanks for the example.

Fixed in git towards 3.917.

always_comb @(*) begin

This is illegal syntax. I fixed Verilator to error out on this (it was ignored by mistake.)

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@veripoolbot veripoolbot commented Jan 2, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-02T23:15:47Z


In 3.918.

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