Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

verilator generates infinite loop #1254

Closed
veripoolbot opened this issue Dec 22, 2017 · 2 comments
Closed

verilator generates infinite loop #1254

veripoolbot opened this issue Dec 22, 2017 · 2 comments
Assignees

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented Dec 22, 2017


Author Name: Alex Solomatnikov
Original Redmine Issue: 1254 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Verilog:

     forever begin
#ifndef VERILATOR
       @(posedge clock) trace_count += 64'd1;
#endif
     end

C:

while (1) {
}

It would be better to error out.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Dec 27, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-12-27T02:35:23Z


Reasonable enough, added to git towards 3.917.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Jan 2, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-02T23:15:09Z


In 3.918.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
2 participants
You can’t perform that action at this time.