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Unlinked error on input-only tristate comparisons #1267

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veripoolbot opened this issue Jan 24, 2018 · 5 comments
Closed

Unlinked error on input-only tristate comparisons #1267

veripoolbot opened this issue Jan 24, 2018 · 5 comments
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@veripoolbot veripoolbot commented Jan 24, 2018


Author Name: Alexis G
Original Redmine Issue: 1267 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


I am using basic Altera's IPcores such as 220model.v (for lpm_mult) and altera_mf.v (for scfifo).

Code snippet:

%Error: Internal Error: /home/work/gitmodelsim/sim_lib/220model.v:3009: ../V3Tristate.cpp:1123: Unlinked
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /home/extssd/git/verilator//bin/verilator_bin -Wall +1364-2001ext+v --cc /home/work/gitmodelsim/sim_lib/220model.v --top-module lpm_mult --exe lpm_mult.cpp
</code>
module lpm_mult (
     dataa,  // Multiplicand. (Required)
     datab,  // Multiplier. (Required)
     sum,    // Partial sum.
     aclr,   // Asynchronous clear for pipelined usage.
     sclr,   // Synchronous clear for pipelined usage.
     clock,  // Clock for pipelined usage.
     clken,  // Clock enable for pipelined usage.
     result  // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
);

// GLOBAL PARAMETER DECLARATION
     parameter lpm_widtha = 1; // Width of the dataa[] port. (Required)
     parameter lpm_widthb = 1; // Width of the datab[] port. (Required)
     parameter lpm_widthp = 1; // Width of the result[] port. (Required)
     parameter lpm_widths = 1; // Width of the sum[] port. (Required)
     parameter lpm_representation  = "UNSIGNED"; // Type of multiplication performed
     parameter lpm_pipeline  = 0; // Number of clock cycles of latency
     parameter lpm_type = "lpm_mult";
     parameter lpm_hint = "UNUSED";

// INPUT PORT DECLARATION
     input  [lpm_widtha-1:0] dataa;
     input  [lpm_widthb-1:0] datab;
     input  [lpm_widths-1:0] sum;  =====================> here is the line 3009
     input  aclr;
     input  sclr;
     input  clock;
     input  clken;
...
</code>

The compilation of the lpm_mult only results in this error with --debugi-V3LinkDot 9:

- V3LinkDot.cpp:2191:    BEGIN 0x27a11b0 <e26718> {d3229} u1=0x295fcd0 [UNNAMED]
- V3LinkDot.cpp:2196:    cur=se0x295fcd0
- V3LinkDot.cpp:2200:    cur=se0x2967580
- V3LinkDot.cpp:2200:    cur=se0x296a6e0
- V3LinkDot.cpp:2200:    cur=se0x24e6b20
- V3LinkDot.cpp:1587:   MODULE 0x26ee430 <e69135> {d2985} u1=0x24d8d40 u4=0x1  TOP_lpm_mult  L1 [P]
- V3LinkDot.cpp:1632: (Backto) Link Cell: CELL 0x26f1620 <e69138> {d2985} u1=0x24e6b20  lpm_mult -> MODULE 0x2770dc0 <e69137> {d2985} u1=0x24e6b20 u4=0x1  lpm_mult  L2
%Error: Internal Error: /home/work/gitmodelsim/sim_lib/220model.v:3009: ../V3Tristate.cpp:1123: Unlinked
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /home/extssd/git/verilator//bin/verilator_bin -Wall +1364-2001ext+v --cc /home/work/gitmodelsim/sim_lib/220model.v --top-module lpm_mult --exe lpm_mult.cpp --debugi-V3LinkDot 9
</code>

I will try to investigate by myself but if you have any idea, you're welcome.

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@veripoolbot veripoolbot commented Jan 24, 2018


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2018-01-24T13:21:53Z


The Altera libraries have some seemingly meaningless Verilog nastiness in them. We put these scripts together to get around some of these issues:
https://github.com/twosigma/verilator_support

I'm not sure if it will work out of the box for you, but hopefully it gets you pointed in the right direction.

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@veripoolbot veripoolbot commented Jan 24, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-24T13:57:02Z


Todd, thanks for the pointer.

Alexis, as to this specific error, if you can provide a small completely standalone test that shows this issue, I'll take a look.

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@veripoolbot veripoolbot commented Jan 25, 2018


Original Redmine Comment
Author Name: Alexis G
Original Date: 2018-01-25T00:33:14Z


Todd, thanks for that.
Indeed, it doesn't work out of the box. I need to make some changes in the lpm_mult.v but I keep getting GET_PARAMETER_VALUE warnings that end in error.

Wilson, it's pretty basic, you can find the 220model.v attached (seems it doesn't work) and just run:
verilator -Wall +1364-2001ext+v --cc 220model.v --top-module lpm_mult --exe lpm_mult.cpp

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@veripoolbot veripoolbot commented Jan 25, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-25T03:32:10Z


Fixed in git towards 3.919. I also tested all other models in the library.

However, basically the tristate comparison they have will add an extra __en input to your model you might not expect. This also slows things down. It's much better to update Todd's script to remove the compare against Z in sum (they should have known better when writing it...)

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@veripoolbot veripoolbot commented Feb 2, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-02-02T01:17:10Z


In 3.920.

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