Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

vcd trace splits packed data type when it comes through a typedef #1276

Closed
veripoolbot opened this issue Feb 13, 2018 · 7 comments
Closed

vcd trace splits packed data type when it comes through a typedef #1276

veripoolbot opened this issue Feb 13, 2018 · 7 comments

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented Feb 13, 2018


Author Name: Christopher Russell
Original Redmine Issue: 1276 from https://www.veripool.org


In our verilog code, we have something similar to the below typedef:

typedef logic foo;

We then create both signal and structs using this typedef:

typedef struct {
  foo [7:0] field;
} bar;

If I look at bar.field in the vcd file generated, it is split into 8 separate bits.

However, if I just create the struct like below:

typedef struct {
  logic [7:0] field;
} bar;

I see what I expect in the vcd which is a unified 8 bit field.

Is there a way to recognize a typedef for the native bit, logic, reg, etc. and not cause this splitting?

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Feb 14, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-02-14T12:25:58Z


I don't see this behavior. Please add to test_regress/t/t_trace_complex.v to show the problem.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Mar 9, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-09T04:58:26Z


Still awaiting a test case... Thanks

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Aug 25, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-08-25T14:40:45Z


Closing as no test case, feel free to post one and reopen.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Aug 4, 2019


Original Redmine Comment
Author Name: Christopher Russell
Original Date: 2019-08-04T15:32:30Z


Sorry for the extremely delayed response. This is still affecting VCD output. I think I've distilled it to a much simpler test case. Structs are not actually necessary.

typedef logic foo;

module bar (
input foo [15:0] in,
output foo [15:0] out
);

assign out = in;

endmodule


If I look in the vcd, I will see this:

     $var wire  1 %+ out(0) $end
     $var wire  1 %, out(1) $end
     $var wire  1 %5 out(10) $end
     $var wire  1 %6 out(11) $end
     $var wire  1 %7 out(12) $end
     $var wire  1 %8 out(13) $end
     $var wire  1 %9 out(14) $end
     $var wire  1 %: out(15) $end
     $var wire  1 %- out(2) $end
     $var wire  1 %. out(3) $end
     $var wire  1 %/ out(4) $end
     $var wire  1 %0 out(5) $end
     $var wire  1 %1 out(6) $end
     $var wire  1 %2 out(7) $end
     $var wire  1 %3 out(8) $end
     $var wire  1 %4 out(9) $end

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Aug 4, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-08-04T17:48:04Z


I don't see this. Are you sure you're using the most recent version? If so, please submit a complete test case in test_regress format.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Aug 4, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-08-04T17:49:15Z


Specifically I get:

$var wire 16 % in [15:0] $end
$var wire 16 & out [15:0] $end
@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Aug 8, 2019


Original Redmine Comment
Author Name: Christopher Russell
Original Date: 2019-08-08T22:31:47Z


I'll try to pull the latest version and see what happens. It's been a while since I updated verilator. I'll update once I confirm.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
1 participant
You can’t perform that action at this time.