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vcd trace splits packed data type when it comes through a typedef #1276
Author Name: Christopher Russell
In our verilog code, we have something similar to the below typedef:
We then create both signal and structs using this typedef:
If I look at bar.field in the vcd file generated, it is split into 8 separate bits.
However, if I just create the struct like below:
I see what I expect in the vcd which is a unified 8 bit field.
Is there a way to recognize a typedef for the native bit, logic, reg, etc. and not cause this splitting?
Original Redmine Comment
Sorry for the extremely delayed response. This is still affecting VCD output. I think I've distilled it to a much simpler test case. Structs are not actually necessary.
If I look in the vcd, I will see this: