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instantiate SystemC model in Verilog dut #1277
Author Name: Steven Milburn
I'm trying to verilate a system with the following hierarchy:
sim_main.cpp as a testbench instantiating dut.v, which instantiates core.cpp, a systemC model.
I get an error that verilator cannot find file containing module "core". It has looked in a bunch of places looking at extensions [none], .v, and .sv.
My command line is:
In this flow, I was going to link in the sim_main.cpp part later with a g++ command.
Is this type of hierarchy workable with SystemC? If so, can someone please explain what I'm missing to make verilator find the systemC model for core?
Original Redmine Comment
You cannot have SystemC underneath Verilog, unless you use DPI/VPI to make some sort of harness similar to what you would have to do with a commercial Verilog simulator.