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instantiate SystemC model in Verilog dut #1277

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veripoolbot opened this issue Feb 14, 2018 · 1 comment
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instantiate SystemC model in Verilog dut #1277

veripoolbot opened this issue Feb 14, 2018 · 1 comment

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@veripoolbot veripoolbot commented Feb 14, 2018


Author Name: Steven Milburn
Original Redmine Issue: 1277 from https://www.veripool.org


Hello,

I'm trying to verilate a system with the following hierarchy:

sim_main.cpp as a testbench instantiating dut.v, which instantiates core.cpp, a systemC model.

I get an error that verilator cannot find file containing module "core". It has looked in a bunch of places looking at extensions [none], .v, and .sv.

My command line is:
verilator -Wall --sc dut.v core_model/core.cpp -Icore_model/include

In this flow, I was going to link in the sim_main.cpp part later with a g++ command.

Is this type of hierarchy workable with SystemC? If so, can someone please explain what I'm missing to make verilator find the systemC model for core?

Thanks

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@veripoolbot veripoolbot commented Feb 14, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-02-14T12:17:01Z


You cannot have SystemC underneath Verilog, unless you use DPI/VPI to make some sort of harness similar to what you would have to do with a commercial Verilog simulator.

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