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scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks #1286

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veripoolbot opened this issue Mar 8, 2018 · 3 comments
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@veripoolbot veripoolbot commented Mar 8, 2018


Author Name: Joel Holdsworth
Original Redmine Issue: 1286 from https://www.veripool.org


Verilator gets stuck allocating huge amounts of memory when processing SystemVerilog code like this...

module test(input reset);

parameter MEM_POWER_SIZE = 16;
logic [7:0] memory [0:2**MEM_POWER_SIZE-1];

always @(negedge reset) begin
  memory = '{2**MEM_POWER_SIZE{'0}};
end

endmodule

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@veripoolbot veripoolbot commented Mar 9, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-09T04:45:02Z


Verilator needs enough memory to fit the entire model, times some inefficiency factor.

The fix could be to throw an error on very large structures (which of course should instead be sparse models), but it's hard to determine what is too large as that depends on system constraints. So my inclination is to leave it as is, but other ideas are welcome.

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@veripoolbot veripoolbot commented Mar 9, 2018


Original Redmine Comment
Author Name: Joel Holdsworth
Original Date: 2018-03-09T17:10:54Z


It would be nice to get an error or a warning. I only figured out the source of the problem by reading the file & line-number out of the AST in gdb.

I could try making the RAM block smaller. At the moment it's allocating more system RAM than I have; at least 2Gb. I'm not sure to what extent the test suite relies on this block being the size it is.

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@veripoolbot veripoolbot commented Mar 10, 2018


Original Redmine Comment
Author Name: Joel Holdsworth
Original Date: 2018-03-10T04:21:31Z


The block was 16Mb in size. Fortunately nothing in the test suite needs this much memory, so I reduced it to 64kB, and now Verilator is much happier

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