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scr1 test suite: assert properties don't work #1290

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veripoolbot opened this issue Mar 10, 2018 · 7 comments
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scr1 test suite: assert properties don't work #1290

veripoolbot opened this issue Mar 10, 2018 · 7 comments
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@veripoolbot veripoolbot commented Mar 10, 2018


Author Name: Joel Holdsworth
Original Redmine Issue: 1290 from https://www.veripool.org

Original Assignee: John Coiner (@jcoiner)


The following SystemVerilog code fails to build...

module test();

mycheck : assert property (
  1'b1
) else begin
  $error("WTF");
end

endmodule

...with the following error...

%Error: test_assert_property.sv:4: syntax error, unexpected assert, expecting cover
%Error: Cannot continue
%Error: Command Failed /usr/local/bin/verilator_bin -sv --lint-only test_assert_property.sv

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@veripoolbot veripoolbot commented Mar 10, 2018


Original Redmine Comment
Author Name: John Coiner (@jcoiner)
Original Date: 2018-03-10T17:55:43Z


Hi Joel,

I'm working on issue 785 which could be considered a dup:

https://www.veripool.org/issues/785-Verilator-Support-for-SystemVerilog-assertions

Though that issue is old, I'm actively working it this week.

Do you really need support for non-edge-triggered asserts? Right now I already have support for edge-triggered asserts of this form:

assert property ((@ posedge clk) expr) [ else statements... ];

... with 'edge' and 'negedge' also supported. I don't have purely combinational asserts working yet, that's more work.

Thanks,

John

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@veripoolbot veripoolbot commented Mar 10, 2018


Original Redmine Comment
Author Name: John Coiner (@jcoiner)
Original Date: 2018-03-10T18:13:20Z


For that matter, does verilog even permit unclocked 'assert property' statements? I'm no language lawyer, and I don't have access to a IEEE spec or a copy of "the binary spec" aka VCS or NC.

Online slide decks I've found only show examples of clocked assertions, though.

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@veripoolbot veripoolbot commented Mar 10, 2018


Original Redmine Comment
Author Name: Joel Holdsworth
Original Date: 2018-03-10T18:22:45Z


You're right - the scr1 tests are all clocked. My example was a bit too simplified!

Great news that you're working on this this week. I'll be glad to test your patches with scr1.

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@veripoolbot veripoolbot commented Mar 10, 2018


Original Redmine Comment
Author Name: John Coiner (@jcoiner)
Original Date: 2018-03-10T18:29:32Z


Thanks. I discovered that concurrent asserts are always clocked in verilog.

So this is a dup of 785.

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@veripoolbot veripoolbot commented Mar 10, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-10T22:50:25Z


John, thanks for looking.

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@veripoolbot veripoolbot commented Mar 11, 2018


Original Redmine Comment
Author Name: John Coiner (@jcoiner)
Original Date: 2018-03-11T14:55:42Z


Here's the fix.

commit c8cf2af (HEAD -> master, origin/master, origin/HEAD)
Author: Wilson Snyder wsnyder@wsnyder.org
Date: Sun Mar 11 10:37:20 2018 -0400

 Support assert properties, #�, #�.
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@veripoolbot veripoolbot commented Mar 12, 2018


Original Redmine Comment
Author Name: John Coiner (@jcoiner)
Original Date: 2018-03-12T23:44:12Z


Fixed in git towards 3.922

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