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Parameter with type string cause compile error when passed to $readmemh(...) #1328

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veripoolbot opened this issue Aug 11, 2018 · 4 comments
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@veripoolbot veripoolbot commented Aug 11, 2018


Author Name: Arjen Roodselaar
Original Redmine Issue: 1328 from https://www.veripool.org


With my limited understanding of the SV type system I expect the following to work:

`default_nettype none

module single_port_rom
#(
  parameter integer ADDR_WIDTH = 8,
  parameter integer DATA_WIDTH = 8,
  parameter string HEX_FILE_PATH = ""
)
(
  output logic [(DATA_WIDTH-1):0] q,
  input logic [ADDR_WIDTH-1:0] addr,
  input logic clk
);

logic [DATA_WIDTH-1:0] data[2**ADDR_WIDTH-1:0];

initial begin
  $readmemh(HEX_FILE_PATH, data);
end

...

endmodule
</code>

When compiling the resulting C++ I end up with the following error:

buck-out/gen/hdl/w65c816/test/Vmicro65_bench.cpp/Vmicro65_bench.cpp:127:5: error: use of undeclared identifier 'VL_READMEM_N'
     VL_READMEM_N (true,8,1024, 0,2, std::string("hdl/w65c816/test/micro65_rom.txt")
     ^
1 error generated.

This compiled with Verilator master and Clang 5.0.1.

Removing the type from the parameter seems to work as expected (but I like types). I am more than happy to look for a fix and provide a patch, but was not sure whether or not this is intended behavior.

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@veripoolbot veripoolbot commented Aug 12, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-08-12T10:24:11Z


I suspect it is legal to use a string instead of Verilog bitvector-as-string.

Could you attempt a patch, and also add to the existing readmem test_regress to test it please?

The fix probably is just to add a function to verilated.h with the expected arguments (std::string) then call the internal READMEM also declared in verilated.h.

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@veripoolbot veripoolbot commented Aug 21, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-08-21T22:28:12Z


Are you sure you're using the latest version, I can't recreate this and suspect it may have been fixed in 3.922.

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@veripoolbot veripoolbot commented Oct 5, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-10-05T00:29:42Z


Didn't hear back so assuming fixed, reopen and attach a test case if fails on latest release.

@veripoolbot veripoolbot closed this Oct 5, 2018
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@veripoolbot veripoolbot commented Dec 12, 2018


Original Redmine Comment
Author Name: Arjen Roodselaar
Original Date: 2018-12-12T06:18:06Z


Apologies for the radio silence. Life got in the way of hobby and I wasn't able to look at this. Unfortunately this was actually an error caused by how I compile Verilator generated models and I can confirm this works as intended.

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