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Adding support for passing by reference #1360

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veripoolbot opened this issue Oct 11, 2018 · 2 comments
Closed

Adding support for passing by reference #1360

veripoolbot opened this issue Oct 11, 2018 · 2 comments

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@veripoolbot veripoolbot commented Oct 11, 2018


Author Name: Jake Longo
Original Redmine Issue: 1360 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Verilator currently doesn't support passing variables by reference and results in:

[UNKNOWN]: Unsupported: SystemVerilog 2005 reserved word not implemented: ref

This would be quite useful to have if it allows us to avoid creating temporary variables and copying them across when attempting to store results from tasks/functions in structures.

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@veripoolbot veripoolbot commented Oct 31, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-10-31T00:56:49Z


Fixed in git towards 4.008.

I added only a few simple tests, I expect some problems as you try to use refs. Please file a new bug on any problems and try to update the new test_regress/t/t_var_ref.pl test to show the problem(s). Thanks!

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@veripoolbot veripoolbot commented Dec 1, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-12-01T20:17:25Z


In 4.008.

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