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False BLKANDNBLK error for different signals in a vector #1365

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veripoolbot opened this issue Nov 6, 2018 · 1 comment
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False BLKANDNBLK error for different signals in a vector #1365

veripoolbot opened this issue Nov 6, 2018 · 1 comment

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@veripoolbot
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@veripoolbot veripoolbot commented Nov 6, 2018


Author Name: Al Grant
Original Redmine Issue: 1365 from https://www.veripool.org


module conflict(input clk, input b, output wire [1:0] a);
  reg [1:0] r;
  always @(posedge clk)
     r[0] <= b;
  always @*
     r[1] = 1'b0;
  assign a = r;
endmodule

fails with

%Error-BLKANDNBLK: conflict.v:2: Unsupported: Blocked and non-blocking assignments to same variable: conflict.r

This is surely legal as they are distinct signals.

Also, it would be helpful if the erorr message could reference the line of the two assignments (and, if in a generate loop, the value of genvars), instead of just the declaration.

@veripoolbot
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@veripoolbot veripoolbot commented Nov 7, 2018


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-11-07T18:42:49Z


Please see #�.

I understand this is annoying, but is a fairly high effort limitation to resolve so hasn't been worked on.

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