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x-assign and x-initial 'unique' setting appears not to work #1399

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veripoolbot opened this issue Feb 16, 2019 · 4 comments
Closed

x-assign and x-initial 'unique' setting appears not to work #1399

veripoolbot opened this issue Feb 16, 2019 · 4 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Feb 16, 2019


Author Name: Stan Sokorac
Original Redmine Issue: 1399 from https://www.veripool.org


In this simple example, x-assign unique and x-initial unique do not appear to work... both X assignment and uninitialized variable get all zeros.

Verilog:

module foo();
  wire[31:0] uninit;
  reg[31:0] assignx;
  initial begin
     $display("uininit: 0x%x", uninit);
     assignx = 32'hx;
     $display("assignx: 0x%x", uninit);
  end 
endmodule
</code>

Testbench:

#include "Vinitial.h"
int main(int argc, char *argv[])
{ 
  Vinitial S;
  S.eval();
  return 0;
}
</code>

Verilator command:

verilator --cc --Mdir out --x-assign unique --x-initial unique initial.sv

Output:

uininit: 0x00000000
assignx: 0x00000000

I tried throwing in new Verilated:randSeed(123), +verilator+seed, srand48(), just in case there was some default path when no seed is provided, but none of those had any effect.

This is on the latest version from git.

@veripoolbot
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@veripoolbot veripoolbot commented Feb 26, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-02-26T23:58:59Z


Running the model with "+verilator+seed+50 +verilator+rand+reset+2" this seems to print random values for me, perhaps you aren't calling the C++ call to parse parameters? If you still have problems please attach an example. (BTW you probably wanted to use assignx in your second display.)

@veripoolbot
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@veripoolbot veripoolbot commented Feb 28, 2019


Original Redmine Comment
Author Name: Stan Sokorac
Original Date: 2019-02-28T14:19:05Z


I've fixed the second display... assignx does indeed work (I was printing the uninit value twice), but uninitialized value is still all zeros. I've attached the full example - unpack and run 'make build; make run'. I get the following output:

out/sim +verilator+seed+14934534 +verilator+rand+reset+2
uininit: 0x00000000
assignx: 0x01c7c40c

@veripoolbot
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@veripoolbot veripoolbot commented Mar 2, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-02T01:08:42Z


You need to call Verilated::commandArgs before you construct the model, I'll clarify this in the docs.

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@veripoolbot veripoolbot commented Mar 2, 2019


Original Redmine Comment
Author Name: Stan Sokorac
Original Date: 2019-03-02T01:19:17Z


Got it! I can confirm that it works now. Thanks!

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