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Support concatenation select #1408

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veripoolbot opened this issue Mar 13, 2019 · 3 comments
Closed

Support concatenation select #1408

veripoolbot opened this issue Mar 13, 2019 · 3 comments

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@veripoolbot veripoolbot commented Mar 13, 2019


Author Name: Alexander Junk
Original Redmine Issue: 1408 from https://www.veripool.org


When trying to verilate multimux_out_2.v with

verilator --pins-bv 2 -sc multimux_out_2.v 

I get the error

%Error: multimux_out_2.v:34: syntax error, unexpected '[', expecting ',' or ';'
%Error: Exiting due to 1 error(s)

The assignment that is not working is:

assign \m3.q = { \m2.q , \m1.q }[select[0] +: 1];

When I replace the concatenation with an intermediate signal, everything works.

Yosys Open SYnthesis Suite also crashes when trying to import the design.
See issue: [[https://github.com/YosysHQ/yosys/issues/870]]

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@veripoolbot veripoolbot commented Mar 13, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-13T23:52:36Z


Two of the big three simulators do not appear to support select of concatenation of expressions, until they do I'm reluctant to add this as there are some complications. Perhaps someone else can provide a patch?

I added an error message that this is unsupported behavior versus a syntax error.

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@veripoolbot veripoolbot commented Mar 14, 2019


Original Redmine Comment
Author Name: Alexander Junk
Original Date: 2019-03-14T10:09:44Z


Wilson Snyder wrote:

Two of the big three simulators do not appear to support select of concatenation of expressions, until they do I'm reluctant to add this as there are some complications. Perhaps someone else can provide a patch?

I added an error message that this is unsupported behavior versus a syntax error.

Thank you. The design was exported to verilog from yosys, which apparently generated the unsupported statement. I did not know that indexing does not work on a concatenation directly which is why I opened an issue here as well. So it is definitely a problem with the generated verilog not the parser.

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@veripoolbot veripoolbot commented May 9, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-09T23:25:37Z


As earlier commented, not supported by big simulators, so not fixing for now; if the others support this will revisit.

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