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Having trouble assigning signals of interfaces to regs within for loop #1418

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veripoolbot opened this issue Apr 12, 2019 · 3 comments
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@veripoolbot veripoolbot commented Apr 12, 2019


Author Name: Junyi Xie
Original Redmine Issue: 1418 from https://www.veripool.org


Hi Wilson,

I experienced errors when I tried to assign signals of an interfaces array to 2-d regs.
Attached are example files which can generate the errors below:

%Error: interface_for_loop_tb.sv:32: Expecting expression to be constant, but variable isn't const: i
%Error: interface_for_loop_tb.sv:32: Could not expand constant selection inside dotted reference: i
%Error: interface_for_loop_tb.sv:33: Expecting expression to be constant, but variable isn't const: i
%Error: interface_for_loop_tb.sv:33: Could not expand constant selection inside dotted reference: i

Appreciate your help.

Regards,
Junyi Xie

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@veripoolbot veripoolbot commented Apr 12, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-04-12T20:35:52Z


Verilator currently requires interface (or cell) references must be statically unrolled. This is currently a fairly fundamental assumption that is unlikely to be improved in the near term (so not leaving this bug open).

To work around it move your for loop to become a generate loop outside the always.

And thanks for your good bug report, that makes it a lot easier to help.

     for (genvar i = 0; i < 2; i++)
     begin
         always_comb
         begin
             buffer_a[i] = in_intfs[i].a;
             buffer_b[i] = in_intfs[i].b;
         end
     end

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@veripoolbot veripoolbot commented Apr 12, 2019


Original Redmine Comment
Author Name: Junyi Xie
Original Date: 2019-04-12T20:54:53Z


This is reasonable.
Thanks for the quick reply by the way!

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@veripoolbot veripoolbot commented Apr 15, 2019


Original Redmine Comment
Author Name: Junyi Xie
Original Date: 2019-04-15T14:26:34Z


Hi Wilson,
We come across a Xilinx page that suggests having for loop inside always_comb helps to save runtime.

https://www.xilinx.com/support/answers/55302.html

This might be interesting for your investigation.

We will for now use the style you recommended though.

Thanks!

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