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2 issues with unsized x/z constants #1423
Author Name: Udi Finkelstein
Original Assignee: Wilson Snyder (@wsnyder)
Verilator is complaining about this code snippet, even if SV mode:
This fails both as t.sv and t.v
But according to the quotes below, it is legal, even if not pretty.
In addition, the following code snippet:
In Verilog-1995, this indeed should be limited to 32 bits, but in SV, unsized constants should be expanded to any width.
According to 5.7.1 in IEEE1800-2017:
So , according to this, in SV 'hx is expanded to any width, and in Verilog-95, it is extended to 32 bits only.
As for the usage of X/Z with 'd, here is part of the BNF from A.8.7 (same IEEE1800-2017 doc):
To summarize the BNF below, decimal numbers may be made of multiple decimal digits (no X/Z),
Original Redmine Comment
"'dx" was accidentally unsupported, fixed this in git towards 4.014.
The extension to match the spec I'll look at. I suspect there will still be a warning message, but the behavior if the warning is suppressed will change to match the spec.
As you note the best style is really to use "'x" instead.