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Verilator does not complain about invalid parameter declaration #1424

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veripoolbot opened this issue Apr 30, 2019 · 7 comments
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Verilator does not complain about invalid parameter declaration #1424

veripoolbot opened this issue Apr 30, 2019 · 7 comments
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@veripoolbot veripoolbot commented Apr 30, 2019


Author Name: Peter Gerst
Original Redmine Issue: 1424 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Verilator fails to trow syntax error on parameter declaration without constant expression, like this:

parameter param1; /* constant expression is missing */

See the following example codes.

parameter_lint.v:

module parameter_lint (
     input wire CLK,
     input wire RST,
     input wire in0,
     output reg out0
);

parameter param0 = 0;
parameter param1;

always @(posedge CLK) begin
     if (RST) begin
         out0 <= 0;
     end else begin
         out0 <= in0;
     end
end

endmodule


parameter_main.v:

module parameter_main(
     input wire CLK,
     input wire RST,
     input wire in0,
     output reg out0
);

parameter_lint #(
     .param1 (1'd0),
     .param0 (1'd0)
) inst0 (
     .CLK (CLK),
     .RST (RST),
     .in0 (in0),
     .out0 (out0)
);

endmodule


Verilator is called in the following way:


$ verilator --lint-only -Wall parameter_main.v


The command above finishes without error. If I comment out the assignment of param1 in instantiation of parameter_lint module in parameter_main.v I get internal error.

$ verilator --lint-only -Wall parameter_main.v
%Error: Internal Error: parameter_lint.v:9: ../V3Param.cpp:277: Parameter without initial value
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /usr/local/bin/verilator_bin --lint-only -Wall parameter_main.v


I used verilator release 4.012 built under cygwin.

Normally i used to call Verilator with specifying verilog 2001 language standard that needs constant expression in parameter declaration. (Xilinx syntheser i used supports this standard.) It seems to be valid for SystemVerilog 2017 as well (http://ecee.colorado.edu/~mathys/ecen2350/IntelSoftware/pdf/IEEE_Std1800-2017_8299595.pdf, page 120).

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@veripoolbot veripoolbot commented Apr 30, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-04-30T10:19:21Z


Parameter without initial values are legal in SystemVerilog 2017, this is not disabled when requesting earlier versions (and you request a earlier version anyhow).

I think everything is working as intended, except that the Internal Error should instead be a user error that the provided parameter was not provided (IEEE 2017 6.20.1).

Agree?

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@veripoolbot veripoolbot commented Apr 30, 2019


Original Redmine Comment
Author Name: Peter Gerst
Original Date: 2019-04-30T11:15:52Z


From the referenced documentation it seems to me that initial value can be omitted only in exceptional cases, but I must confess that I am far from an expert. :)

For my FPGA design I want to catch syntax errors and possible coding failures as soon as possible. For this I use verilator to lint sources before implementation that saves (and already saved) me lot of potential headaches.

In the demonstrated case I get syntax error from the Xilinx syntheser after a successful linting with verilator. The aim of this issue was to point this out.

More explicit I used this for linting:

$ verilator --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY <TOP_module>

Is it possible to add warning message for Verilog 2001? Or would it be overkill to implement this?

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@veripoolbot veripoolbot commented Apr 30, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-04-30T11:19:44Z


Makes sense. Will do this then:

  1. Add error when no initial value in pre-SV-2012.
  2. Otherwise, change internal error to user error.
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@veripoolbot veripoolbot commented Apr 30, 2019


Original Redmine Comment
Author Name: Peter Gerst
Original Date: 2019-04-30T12:43:17Z


Sounds perfect. Thank you!

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@veripoolbot veripoolbot commented Apr 30, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-04-30T23:17:02Z


Fixed in git towards 4.014.

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@veripoolbot veripoolbot commented May 9, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-09T01:37:26Z


In 4.014.

@veripoolbot veripoolbot closed this May 9, 2019
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@veripoolbot veripoolbot commented May 9, 2019


Original Redmine Comment
Author Name: Peter Gerst
Original Date: 2019-05-09T07:03:25Z


It works. Thank you very much!

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