Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

deferred assertion support #1449

Closed
veripoolbot opened this issue May 29, 2019 · 6 comments
Closed

deferred assertion support #1449

veripoolbot opened this issue May 29, 2019 · 6 comments

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented May 29, 2019


Author Name: Charles Eddleston
Original Redmine Issue: 1449 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


System verilog deferred assertions are treated as syntax errors:
http://systemverilog.us/vf/deferred_assertion.pdf

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 29, 2019


Original Redmine Comment
Author Name: Charles Eddleston
Original Date: 2019-05-29T19:54:48Z


Error message:
syntax error, unexpected final, expecting '(' or property

code:
assert final ( !intf_data_in_64_4.tlast ) else begin
$error( "[RTL-ASSERT] %0t: %m unexpected TLAST (DATA)", $time );

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 29, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-29T22:31:44Z


Seems straight forward to add this. Might you be willing to attempt a patch, or at least a self-checking test checked against another simulator in verilator's test_regress format? Thanks

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 30, 2019


Original Redmine Comment
Author Name: Charles Eddleston
Original Date: 2019-05-30T02:58:26Z


Yeah, I'm not the best with linux, but given instructions, I would be happy to apply the patch and test it out. I'm using ventilator for LINT checks, we use VCS for simulation...so my testing would just be ensuring that both assert #0 and assert final are no longer flagged in LINT.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 30, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-30T03:14:47Z


I mean might you be able to come up with a patch that fixes the sources yourself, and/or provide a test_regress style verilog file?

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 31, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-31T11:35:03Z


Realized all that was needed was parser code pulled from Verilog-Perl.

Fixed in git towards 4.016.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Jun 16, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-16T13:58:31Z


In 4.016.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
2 participants
You can’t perform that action at this time.