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Support for loop index into generated arrays #1454

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veripoolbot opened this issue Jun 3, 2019 · 3 comments
Open

Support for loop index into generated arrays #1454

veripoolbot opened this issue Jun 3, 2019 · 3 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jun 3, 2019


Author Name: X Yyy
Original Redmine Issue: 1454 from https://www.veripool.org


module test(input clk,
             input rst
             );

    generate genvar idx;
       for (idx = 0; idx < 10; idx = idx + 1) begin : prefix
          reg [7:0] r;
       end
    endgenerate

    integer         idx1;
    
    always @(posedge clk)
      if (~rst) begin
         for (idx1 = 0; idx1 < 10; idx1 = idx1 + 1) begin
            prefix[idx1].r <= 0;
         end
      end
    
endmodule

For the example above, Verilator fails with the following messages:

%Error: vtst.v:16: Expecting expression to be constant, but variable isn't const: idx1
%Error: vtst.v:16: Could not expand constant selection inside dotted reference: idx1
%Error: vtst.v:16: Can't find definition of 'r' in dotted signal: prefix__BRA__??__KET__.r
%Error:      Known scopes under 'r': <no cells found>
%Error: Exiting due to 3 error(s)

Looks like constant elaboration is attempted before the for loop is unrolled. Interestingly, Icarus fails in a very similar way here. Yosys handles this module correctly though, as well as Xilinx and Altera tools.

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@veripoolbot veripoolbot commented Jun 3, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-03T22:32:30Z


Verilator doesn't presently support runtime indexing into cells or named blocks. It does support generated indexing. To work around this, change your for loop to be a generate loop.

 for (idx1 = 0; idx1 < 10; idx1 = idx1 + 1) begin
     always @(posedge clk)
      if (~rst) begin
            prefix[idx1].r <= 0;
         end
     end

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@veripoolbot veripoolbot commented Jun 4, 2019


Original Redmine Comment
Author Name: X Yyy
Original Date: 2019-06-04T09:22:09Z


Ok, then the issue is even deeper - why the synthesisable (i.e., constant-bound) behavioural for loops in Verilator are not generated (i.e., not expanded in compilation time), to match the semantics of the synthesised subset of Verilog? What's the reason for keeping them as runtime loops?

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@veripoolbot veripoolbot commented Jun 4, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-04T11:05:10Z


Verilator will unroll both kinds of loops. Generate loops are unrolled at a different stage, elaboration, which is a requirement of the language.

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