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signal redeclaration is not reported #1462

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veripoolbot opened this issue Jun 12, 2019 · 4 comments
Closed

signal redeclaration is not reported #1462

veripoolbot opened this issue Jun 12, 2019 · 4 comments
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@veripoolbot veripoolbot commented Jun 12, 2019


Author Name: Peter Gerst
Original Redmine Issue: 1462 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


I am using verilator to lint verilog modules which will be then synthesized by Xilinx tools. Prior to synthesis verilator is called with --lint-only mode to find errors and potential failures.

The following code makes Xinlinx syntheser to complain about signal re-declaration:

module output_wire (
     input wire CLK,
     input wire RESET,
     input wire in0,

     output wire out0,
     output reg  out1
);

wire out0;
reg  out1;


assign out0 = (RESET) ? 1'b0 : in0;

always @(posedge CLK) begin
     if (RESET) begin
         out1 <= 1'b0;
     end else begin
         out1 <= in0;
     end
end

endmodule


In contrast verilator does not warn about anything:

verilator --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY output_wire.v

I also noticed that wire and reg signals are handled differently by verilator. See the following example:

module output_wire (
     input wire CLK,
     input wire RESET,
     input wire in0,
     /* output wire [1:0] out0, */
     /* output reg  [1:0] out1 */
     output wire out0,
     output reg  out1
);

/* wire out0; */
/* reg  out1; */
/* wire [1:0] out0; */
reg  [1:0] out1;

assign out0 = (RESET) ? 1'b0 : in0;

always @(posedge CLK) begin
     if (RESET) begin
         out1 <= 1'b0;
     end else begin
         out1 <= in0;
     end
end

endmodule


This module is found to be okay by verilator although the differently declared out1 but if I uncommented line "/* wire [1:0] out0; */" and commented line "reg [1:0] out1;" I got:

$ verilator --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY output_wire.v
%Warning-WIDTH: output_wire.v:16: Operator COND expects 2 bits on the Conditional True, but Conditional True's CONST '1'h0' generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: output_wire.v:16: Operator COND expects 2 bits on the Conditional False, but Conditional False's VARREF 'in0' generates 1 bits.
%Error: Exiting due to 2 warning(s)
%Error: Command Failed /usr/local/bin/verilator_bin --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY output_wire.v

verilator version:

$ verilator --version
Verilator 4.014 2019-05-08 rev UNKNOWN_REV

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@veripoolbot veripoolbot commented Jun 12, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-12T23:17:56Z


Yes, some duplicates weren't reported.

Fixed in git towards 4.015.

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@veripoolbot veripoolbot commented Jun 16, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-16T13:59:40Z


In 4.016.

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@veripoolbot veripoolbot commented Jun 17, 2019


Original Redmine Comment
Author Name: Peter Gerst
Original Date: 2019-06-17T10:11:34Z


I tried the first example with version 4.016 but it did not worked. Verilator did not raise warning or error on duplicated signals.
Verilator was compiled on cygwin 3.0.7 with gcc 7.4.0.

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@veripoolbot veripoolbot commented Jun 22, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-22T16:50:53Z


Thanks for checking, was missing many other cases, and also warning on duplicated ports.

Fixed in git towards 4.017.

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