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signal redeclaration is not reported #1462
Author Name: Peter Gerst
Original Assignee: Wilson Snyder (@wsnyder)
I am using verilator to lint verilog modules which will be then synthesized by Xilinx tools. Prior to synthesis verilator is called with --lint-only mode to find errors and potential failures.
The following code makes Xinlinx syntheser to complain about signal re-declaration:
In contrast verilator does not warn about anything:
I also noticed that wire and reg signals are handled differently by verilator. See the following example:
This module is found to be okay by verilator although the differently declared out1 but if I uncommented line "/* wire [1:0] out0; */" and commented line "reg [1:0] out1;" I got:
Original Redmine Comment
I tried the first example with version 4.016 but it did not worked. Verilator did not raise warning or error on duplicated signals.