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Memory not updating in for loop #1472

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veripoolbot opened this issue Jun 26, 2019 · 2 comments
Closed

Memory not updating in for loop #1472

veripoolbot opened this issue Jun 26, 2019 · 2 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jun 26, 2019


Author Name: Somya Dashora
Original Redmine Issue: 1472 from https://www.veripool.org


We are facing an issue with following verilog code

Snippets of the relevant portion of code is shown below :


module DUT (
         
             //signal declaration
        
             ) ;

input Clear_Signal;
input rst ;
reg [3:0] Dist_Ram [ 0 : RAM_DEPTH ] ;

integer i;


     always @ ( posedge clk )
        begin
            if ( !rst )
           begin
              for( i=0 ; i < RAM_DEPTH ; i=i+1 ) // reset RAM with zeros
                 Dist_Ram [ i ] <= {  4{ 1'b0 } };
              end
        
             else
               begin
                  if ( Clear_Signal )                                       
                    begin
                       for ( i=0 ; i < RAM_DEPTH ; i = i+1 )
                                 Dist_Ram [ i ] <= 4'd0 ;
                    end
                
                // ---- Some Code Followed . . .
                .
                .
                .
                .
                .


endmodule


The problem i am facing is that when signal Clear_Signal is asserted the Dist_Ram should have all zero as it content.

But on displaying the content we get

 Dist_Ram[0] = 1001  // Some data written 
 Dist_Ram[1] = 1011  // by some code
 Dist_Ram[2] = 1010  // 
 .
 .
 .
 .
 .
 Dist_Ram[9] = 1001

This in not as expected.

However the same code on Questa Sim-64 Version 10.6a results in

 Dist_Ram[0] = 0000
 Dist_Ram[1] = 0000
 Dist_Ram[2] = 0000
 .
 .
 .
 .
 .
 Dist_Ram[9] = 0000

Which is desired and expected.

We think this might be due the common loop variable 'i' which we are using to unroll the for loop - in both cases of rst and Clear_Signal.

The verilator version on which the code was run is :

Verilator 4.016 2019-06-16 rev UNKNOWN_REV

The command that was run is

verilator --x-assign fast --x-initial fast -O3
-CFLAGS ""
-Wno-style -Wno-lint -Wno-BLKLOOPINIT -Wno-STMTDLY -Wno-UNOPTFLAT
-Mdir ./Verilator_obj
--cc -y src -y tb_v Top.v --exe ./tb_c/main.cpp &&
make -j -C ./Verilator_obj -f VmkTop.mk &&
./Verilator_obj/VmkTop

Please could you let us know a way to resolve this.

@veripoolbot
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@veripoolbot veripoolbot commented Jun 26, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-26T22:50:02Z


Please attach a complete standalone example so I can try it, thanks. Ideally this would be in test_regress format as described in the documentation, but a tar/zip file that runs standalone could work.

@veripoolbot
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@veripoolbot veripoolbot commented Oct 9, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-09T00:41:36Z


Thanks for filing this, feel free to reopen if a complete test case can be provided.

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