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Author Name: Somya Dashora
We are facing an issue with following verilog code
Snippets of the relevant portion of code is shown below :
The problem i am facing is that when signal Clear_Signal is asserted the Dist_Ram should have all zero as it content.
But on displaying the content we get
This in not as expected.
However the same code on Questa Sim-64 Version 10.6a results in
Which is desired and expected.
We think this might be due the common loop variable 'i' which we are using to unroll the for loop - in both cases of rst and Clear_Signal.
The verilator version on which the code was run is :
Verilator 4.016 2019-06-16 rev UNKNOWN_REV
The command that was run is
verilator --x-assign fast --x-initial fast -O3
Please could you let us know a way to resolve this.
Original Redmine Comment
Please attach a complete standalone example so I can try it, thanks. Ideally this would be in test_regress format as described in the documentation, but a tar/zip file that runs standalone could work.