How to get no `line pragmas in preprocessor

[veripoolbot]

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Author Name: Aliaksei Chapyzhenka
Original Redmine Issue: 1473 from https://www.veripool.org

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As I understand, Verilator preprocessor inserts line pragmas instead of include and other directives.
It can appear in any place of the Verilog code and it makes Verilog parser job harder.
Example: tree-sitter/tree-sitter-verilog#18
Could we have a preprocessor option to disable `line insertion?

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-26T22:42:28Z

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Please see the -P option in the manual.

If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code.

[veripoolbot]

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Original Redmine Comment
Author Name: Aliaksei Chapyzhenka
Original Date: 2019-06-26T23:57:50Z

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Wilson Snyder wrote:

Please see the -P option in the manual.

If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code.

Great. Thank you.