How to get no `line pragmas in preprocessor #1473
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Original Redmine Comment Please see the -P option in the manual. If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code. |
Original Redmine Comment Wilson Snyder wrote:
Great. Thank you. |
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Author Name: Aliaksei Chapyzhenka
Original Redmine Issue: 1473 from https://www.veripool.org
As I understand, Verilator preprocessor inserts
line pragmas instead of
include and other directives.It can appear in any place of the Verilog code and it makes Verilog parser job harder.
Example: tree-sitter/tree-sitter-verilog#18
Could we have a preprocessor option to disable `line insertion?
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