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Parameter of an array of enumeration values breaks conditionals inside a generate block #1484

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veripoolbot opened this issue Jul 30, 2019 · 3 comments

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@veripoolbot veripoolbot commented Jul 30, 2019


Author Name: John Martin (@emmicro-us)
Original Redmine Issue: 1484 from https://www.veripool.org


This was tested using the Verilator 4.016 release. When using a parameter that is an array of enumeration values inside an if (or case) condition of a generate block triggers the following errors:
%Error: test.sv:48: Illegal assignment of constant to unpacked array
%Error: test.sv:48: Generate If condition must evaluate to constant

When changing the array to be packed Verilator will throw only warnings; however the generate block does not evaluate the condition correctly. Attached is a test case that demonstrates this. The example simulates correctly with Incisive and synthesizes with Design Compiler. Icarus Verilog and Yosys unfortunately don't support this syntax.

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@veripoolbot veripoolbot commented Jul 30, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-07-30T19:36:40Z


Thanks for the report & test. This is a duplicate of #�, on which work is currently in progress.

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@veripoolbot veripoolbot commented Nov 10, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-10T01:32:17Z


Note #� is fixed in git, now this example fails with

%Error: t/t_param_array6.v:58: Illegal assignment of constant to unpacked array

This is because of a mistake in the provided source, it should be

parameter OpType_t OP_MODULES[MAX_NUM_OPS] = '{

(Note the tick). With that change this test passes.

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@veripoolbot veripoolbot commented Nov 10, 2019


Original Redmine Comment
Author Name: John Martin (@emmicro-us)
Original Date: 2019-11-10T01:43:54Z


Silly mistake :( Thank you for looking at it!

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