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A strange code generated from a parametric module. #1488

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veripoolbot opened this issue Aug 6, 2019 · 2 comments
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A strange code generated from a parametric module. #1488

veripoolbot opened this issue Aug 6, 2019 · 2 comments

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@veripoolbot veripoolbot commented Aug 6, 2019


Author Name: Slava B
Original Redmine Issue: 1488 from https://www.veripool.org


I've seen a strange code generated from a parametric module. I minimized this scenario to a few lines:

module arbiter #(
     parameter VCD_PORT_NUMBER = 3
)
(
     input clk,
     output reg [VCD_PORT_NUMBER-1:0] in_ip2bus_ack,
     output reg [(VCD_PORT_NUMBER*32)-1:0] in_ip2bus_data
);
     always @ (posedge clk)
         begin
             in_ip2bus_ack = 3'b0;
             in_ip2bus_data = 96'b0;
         end
endmodule
</code>

The resulting translation is:

SC_MODULE(Varbiter) {
  public:

     sc_in<bool> clk;
     sc_out<uint32_t> in_ip2bus_ack;
     sc_out<sc_bv<96> > in_ip2bus_data;
...
}   
</code>

Why Verilator converted Verilog's 3-bit port (in_ip2bus_ack) into 32-bit port in SystemC. The conversion of 96-bit port (in_ip2bus_data) was correct. This is very misleading. Did I miss something?

Thanks,
Slava

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@veripoolbot veripoolbot commented Aug 6, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-08-06T13:35:32Z


uints are much faster so are the default. See the Connecting to SystemC part of the manual and the --pins-sc-uint/--sc-pins-biguint flags.

@veripoolbot veripoolbot closed this Aug 6, 2019
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@veripoolbot veripoolbot commented Aug 7, 2019


Original Redmine Comment
Author Name: Slava B
Original Date: 2019-08-07T05:18:07Z


Thank you very much, Wilson! I was not aware about --pins-sc-uint switch!

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