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A strange code generated from a parametric module. #1488
Author Name: Slava B
I've seen a strange code generated from a parametric module. I minimized this scenario to a few lines:
The resulting translation is:
Why Verilator converted Verilog's 3-bit port (in_ip2bus_ack) into 32-bit port in SystemC. The conversion of 96-bit port (in_ip2bus_data) was correct. This is very misleading. Did I miss something?