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[VerilogAMS]: Unknown Language Specified #1503

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veripoolbot opened this issue Sep 10, 2019 · 2 comments
Closed

[VerilogAMS]: Unknown Language Specified #1503

veripoolbot opened this issue Sep 10, 2019 · 2 comments

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@veripoolbot veripoolbot commented Sep 10, 2019


Author Name: Rohit Yadav
Original Redmine Issue: 1503 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Hi,

I am new to Verilator. I am interested in simulating several verilogams test cases with Verilator. I ran the following command to a simple vams file but Verilator fails with the following log:

#+begin_src bash
1. Run command
verilator -Wall --language VAMS --cc DAC6.vams
1. Error log
%Error: Unknown language specified: VAMS
%Error: Command Failed /nix/store/44qhhq29xqi8f3h6n1pmjnlzgpagwy4z-verilator-4.016/bin/verilator_bin -Wall --language VAMS --cc DAC6.vams
make: *** [Makefile:2: default] Error 10
#+end_src

#+begin_src vams :filename DAC6.vams
`include "disciplines.vams"
module DAC6 (Din,Aout, Vdd,Vss);
input [5:0] Din; // digital input bus
output Aout; // analog output
input Vdd,Vss; // reference supply for output
electrical Aout,Vdd,Vss;
parameter real tr=10n; // (sec) risetime for output changes
parameter real rout=1k; // (ohms) output resistance
real kout; // output as fraction of supply
real vout; // continuous analog output voltage
always begin
 if (^Din === 1âbx) kout=0; // if any bits invalid in Din, output is zero
 else kout = Din/63.0; // else compute scale factor for output
 @(Din); // repeat whenever Din changes
end
analog begin
 vout = V(Vdd,Vss)*transition(kout,0,tr,tr); // ramp to fraction of supply
 I(Aout,Vss) <+ (V(Aout,Vss)-vout)/rout; // drive output
voltage+resistance
end
endmodule
#+end_src

Standard verilog seems to be work fine but not vams.

I apologize if this has been answered before. I tried searching through the issues history but could not find any related to this.

Regards,
Rohit

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@veripoolbot veripoolbot commented Sep 11, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-11T11:19:42Z


Verilator supports almost no AMS, basically wreal and one or two functions, and this is unlikely to be improved even in the long term, sorry. See the manual for details.

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@veripoolbot veripoolbot commented Sep 11, 2019


Original Redmine Comment
Author Name: Rohit Yadav
Original Date: 2019-09-11T19:11:35Z


Thanks for the response. I apologize, since it was mentioned in the options, I thought may be it is supported, although it was listed that it will support very limited VAMS. Thanks again for looking into my issue.

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