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[Bug] cannot understand multi-dimensional array interfaces #1505

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veripoolbot opened this issue Sep 12, 2019 · 3 comments
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[Bug] cannot understand multi-dimensional array interfaces #1505

veripoolbot opened this issue Sep 12, 2019 · 3 comments

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@veripoolbot veripoolbot commented Sep 12, 2019


Author Name: Ânderson Ignacio Da Silva
Original Redmine Issue: 1505 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Verilator 4.018 cannot parse understand multi-dimensional array using interfaces structures from system verilog. The instantiation below cannot be parsed and raises syntax error of unexpected '['.

https://github.com/pulp-platform/apu_cluster/blob/master/sourcecode/apu_cluster.sv#L88

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@veripoolbot veripoolbot commented Sep 12, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-12T14:45:39Z


Agreed this is a mistake in translation of the IEEE grammar. Also applies to Verilog-Perl which will get fixed first.

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@veripoolbot veripoolbot commented Sep 12, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-12T22:24:20Z


Verilog-Perl fixed in version 3.468.

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@veripoolbot veripoolbot commented Sep 12, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-12T23:14:07Z


Thanks for the report.

I created a test case and this is not supported in the two commercial simulators I could check. Given that this was turning painful for Verilator I think development time is better spent elsewhere, so not supporting for now. Will reconsider if/when all of the major commercial simulators get there.

However, the error message should have been better as this was unintentionally a syntax error, so added an unsupported message towards version 4.020.

You might want to suggest that the pulp project use only a 1D array to make their code more portable.

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