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Improve --protect-lib performance #1520

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veripoolbot opened this issue Sep 24, 2019 · 0 comments

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area: performance area: usability effort: days type: feature-non-IEEE

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veripoolbot commented Sep 24, 2019

Author Name: Todd Strader (@toddstrader)
Original Redmine Issue: 1520 from https://www.veripool.org

Original Assignee: Todd Strader (@toddstrader)

Some possibilities:

Detect cones of logic and only fetch the outputs that are affected by a given input
Detect sequential outputs and only send inputs on clock edges
Detect posedge/negedge only sequential outputs so we don't have to update on every clock edge

veripoolbot added area: performance area: usability effort: days type: feature-non-IEEE labels

veripoolbot assigned toddstrader

yTakatsukasa mentioned this issue

Improve Verilating speed for large designs with repetition #2182

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yTakatsukasa mentioned this issue

Improve --hierarchical performance #2583

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